iodev/pcipnic.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: pcipnic.cc,v 1.28 2008/07/26 08:02:27 vruppert Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2003  Fen Systems Ltd.
   6 //  http://www.fensystems.co.uk/
   7 //
   8 //  This library is free software; you can redistribute it and/or
   9 //  modify it under the terms of the GNU Lesser General Public
  10 //  License as published by the Free Software Foundation; either
  11 //  version 2 of the License, or (at your option) any later version.
  12 //
  13 //  This library is distributed in the hope that it will be useful,
  14 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 //  Lesser General Public License for more details.
  17 //
  18 //  You should have received a copy of the GNU Lesser General Public
  19 //  License along with this library; if not, write to the Free Software
  20 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 /////////////////////////////////////////////////////////////////////////
  22
  23 // Define BX_PLUGGABLE in files that can be compiled into plugins.  For
  24 // platforms that require a special tag on exported symbols, BX_PLUGGABLE
  25 // is used to know when we are exporting symbols and when we are importing.
  26
  27 #define BX_PLUGGABLE
  28
  29 #include "iodev.h"
  30 #if BX_SUPPORT_PCI && BX_SUPPORT_PCIPNIC
  31
  32 #include "eth.h"
  33
  34 #define LOG_THIS thePNICDevice->
  35
  36 bx_pcipnic_c* thePNICDevice = NULL;
  37
  38 const Bit8u pnic_iomask[16] = {2, 0, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  39
  40 int libpcipnic_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
  41 {
  42   thePNICDevice = new bx_pcipnic_c();
  43   BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePNICDevice, BX_PLUGIN_PCIPNIC);
  44   return 0; // Success
  45 }
  46
  47 void libpcipnic_LTX_plugin_fini(void)
  48 {
  49   delete thePNICDevice;
  50 }
  51
  52 bx_pcipnic_c::bx_pcipnic_c()
  53 {
  54   put("PNIC");
  55   settype(PCIPNICLOG);
  56 }
  57
  58 bx_pcipnic_c::~bx_pcipnic_c()
  59 {
  60   BX_DEBUG(("Exit"));
  61 }
  62
  63 void bx_pcipnic_c::init(void)
  64 {
  65   bx_list_c *base;
  66
  67   // Read in values from config interface
  68   base = (bx_list_c*) SIM->get_param(BXPN_PNIC);
  69   memcpy(BX_PNIC_THIS s.macaddr, SIM->get_param_string("macaddr", base)->getptr(), 6);
  70
  71   BX_PNIC_THIS s.devfunc = 0x00;
  72   DEV_register_pci_handlers(this, &BX_PNIC_THIS s.devfunc, BX_PLUGIN_PCIPNIC,
  73                             "Experimental PCI Pseudo NIC");
  74
  75   for (unsigned i=0; i<256; i++) {
  76     BX_PNIC_THIS s.pci_conf[i] = 0x0;
  77   }
  78
  79   // This code ripped wholesale from ne2k.cc:
  80   // Attach to the simulated ethernet dev
  81   const char *ethmod = SIM->get_param_enum("ethmod", base)->get_selected();
  82   BX_PNIC_THIS ethdev = eth_locator_c::create(ethmod,
  83                                               SIM->get_param_string("ethdev", base)->getptr(),
  84                                               (const char *) SIM->get_param_string("macaddr", base)->getptr(),
  85                                               rx_handler,
  86                                               this,
  87                                               SIM->get_param_string("script", base)->getptr());
  88
  89   if (BX_PNIC_THIS ethdev == NULL) {
  90     BX_PANIC(("could not find eth module %s", ethmod));
  91     // if they continue, use null.
  92     BX_INFO(("could not find eth module %s - using null instead", ethmod));
  93
  94     BX_PNIC_THIS ethdev = eth_locator_c::create("null", NULL,
  95                                                 (const char *) SIM->get_param_string("macaddr", base)->getptr(),
  96                                                 rx_handler,
  97                                                 this, "");
  98     if (BX_PNIC_THIS ethdev == NULL)
  99       BX_PANIC(("could not locate null module"));
 100   }
 101
 102   BX_PNIC_THIS s.base_ioaddr = 0;
 103
 104   BX_INFO(("PCI Pseudo NIC initialized - I/O base and IRQ assigned by PCI BIOS"));
 105 }
 106
 107 void bx_pcipnic_c::reset(unsigned type)
 108 {
 109   unsigned i;
 110
 111   static const struct reset_vals_t {
 112     unsigned      addr;
 113     unsigned char val;
 114   } reset_vals[] = {
 115     { 0x00, PNIC_PCI_VENDOR & 0xff },
 116     { 0x01, PNIC_PCI_VENDOR >> 8 },
 117     { 0x02, PNIC_PCI_DEVICE & 0xff },
 118     { 0x03, PNIC_PCI_DEVICE >> 8 },
 119     { 0x04, 0x05 }, { 0x05, 0x00 },     // command_io
 120     { 0x06, 0x80 }, { 0x07, 0x02 },     // status
 121     { 0x08, 0x01 },                 // revision number
 122     { 0x09, 0x00 },                 // interface
 123     { 0x0a, 0x00 },                 // class_sub
 124     { 0x0b, 0x02 },                 // class_base Network Controller
 125     { 0x0D, 0x20 },                 // bus latency
 126     { 0x0e, 0x00 },                 // header_type_generic
 127     // address space 0x20 - 0x23
 128     { 0x20, 0x01 }, { 0x21, 0x00 },
 129     { 0x22, 0x00 }, { 0x23, 0x00 },
 130     { 0x3c, 0x00, },                // IRQ
 131     { 0x3d, BX_PCI_INTA },          // INT
 132     { 0x6a, 0x01 },                 // PNIC clock
 133     { 0xc1, 0x20 }                  // PIRQ enable
 134
 135   };
 136   for (i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
 137       BX_PNIC_THIS s.pci_conf[reset_vals[i].addr] = reset_vals[i].val;
 138   }
 139
 140   // Set up initial register values
 141   BX_PNIC_THIS s.rCmd = PNIC_CMD_NOOP;
 142   BX_PNIC_THIS s.rStatus = PNIC_STATUS_OK;
 143   BX_PNIC_THIS s.rLength = 0;
 144   BX_PNIC_THIS s.rDataCursor = 0;
 145   BX_PNIC_THIS s.recvIndex = 0;
 146   BX_PNIC_THIS s.recvQueueLength = 0;
 147   BX_PNIC_THIS s.irqEnabled = 0;
 148
 149   // Deassert IRQ
 150   set_irq_level(0);
 151 }
 152
 153 void bx_pcipnic_c::register_state(void)
 154 {
 155   unsigned i;
 156   char name[6];
 157
 158   bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pcipnic", "PCI Pseudo NIC State", 11);
 159   new bx_shadow_num_c(list, "irqEnabled", &BX_PNIC_THIS s.irqEnabled);
 160   new bx_shadow_num_c(list, "rCmd", &BX_PNIC_THIS s.rCmd);
 161   new bx_shadow_num_c(list, "rStatus", &BX_PNIC_THIS s.rStatus);
 162   new bx_shadow_num_c(list, "rLength", &BX_PNIC_THIS s.rLength);
 163   new bx_shadow_num_c(list, "rDataCursor", &BX_PNIC_THIS s.rDataCursor);
 164   new bx_shadow_num_c(list, "recvIndex", &BX_PNIC_THIS s.recvIndex);
 165   new bx_shadow_num_c(list, "recvQueueLength", &BX_PNIC_THIS s.recvQueueLength);
 166   bx_list_c *recvRL = new bx_list_c(list, "recvRingLength", PNIC_RECV_RINGS);
 167   for (i=0; i<PNIC_RECV_RINGS; i++) {
 168     sprintf(name, "%d", i);
 169     new bx_shadow_num_c(recvRL, name, &BX_PNIC_THIS s.recvRingLength[i]);
 170   }
 171   new bx_shadow_data_c(list, "rData", BX_PNIC_THIS s.rData, PNIC_DATA_SIZE);
 172   new bx_shadow_data_c(list, "recvRing", (Bit8u*)BX_PNIC_THIS s.recvRing, PNIC_RECV_RINGS*PNIC_DATA_SIZE);
 173   register_pci_state(list, BX_PNIC_THIS s.pci_conf);
 174 }
 175
 176 void bx_pcipnic_c::after_restore_state(void)
 177 {
 178   if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
 179                           &BX_PNIC_THIS s.base_ioaddr,
 180                           &BX_PNIC_THIS s.pci_conf[0x10],
 181                           16, &pnic_iomask[0], "PNIC")) {
 182     BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS s.base_ioaddr));
 183   }
 184 }
 185
 186 void bx_pcipnic_c::set_irq_level(bx_bool level)
 187 {
 188   DEV_pci_set_irq(BX_PNIC_THIS s.devfunc, BX_PNIC_THIS s.pci_conf[0x3d], level);
 189 }
 190
 191 // static IO port read callback handler
 192 // redirects to non-static class handler to avoid virtual functions
 193
 194 Bit32u bx_pcipnic_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
 195 {
 196 #if !BX_USE_PCIPNIC_SMF
 197   bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
 198   return class_ptr->read(address, io_len);
 199 }
 200
 201 Bit32u bx_pcipnic_c::read(Bit32u address, unsigned io_len)
 202 {
 203 #else
 204   UNUSED(this_ptr);
 205 #endif // !BX_USE_PCIPNIC_SMF
 206   Bit32u val = 0x0;
 207   Bit8u  offset;
 208
 209   BX_DEBUG(("register read from address 0x%04x - ", (unsigned) address));
 210
 211   offset = address - BX_PNIC_THIS s.base_ioaddr;
 212
 213   switch (offset) {
 214   case PNIC_REG_STAT:
 215     val = BX_PNIC_THIS s.rStatus;
 216     break;
 217
 218   case PNIC_REG_LEN:
 219     val = BX_PNIC_THIS s.rLength;
 220     break;
 221
 222   case PNIC_REG_DATA:
 223     if (BX_PNIC_THIS s.rDataCursor >= BX_PNIC_THIS s.rLength)
 224       BX_PANIC(("PNIC read at %u, beyond end of data register array",
 225                 BX_PNIC_THIS s.rDataCursor));
 226     val = BX_PNIC_THIS s.rData[BX_PNIC_THIS s.rDataCursor++];
 227     break;
 228
 229   default :
 230     val = 0; // keep compiler happy
 231     BX_PANIC(("unsupported io read from address=0x%04x!", (unsigned) address));
 232     break;
 233   }
 234
 235   BX_DEBUG(("val =  0x%04x", (Bit16u) val));
 236
 237   return(val);
 238 }
 239
 240 // static IO port write callback handler
 241 // redirects to non-static class handler to avoid virtual functions
 242
 243 void bx_pcipnic_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
 244 {
 245 #if !BX_USE_PCIPNIC_SMF
 246   bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
 247
 248   class_ptr->write(address, value, io_len);
 249 }
 250
 251 void bx_pcipnic_c::write(Bit32u address, Bit32u value, unsigned io_len)
 252 {
 253 #else
 254   UNUSED(this_ptr);
 255 #endif // !BX_USE_PCIPNIC_SMF
 256   Bit8u  offset;
 257
 258   BX_DEBUG(("register write to address 0x%04x - ", (unsigned) address));
 259
 260   offset = address - BX_PNIC_THIS s.base_ioaddr;
 261
 262   switch (offset) {
 263   case PNIC_REG_CMD:
 264     BX_PNIC_THIS s.rCmd = value;
 265     BX_PNIC_THIS exec_command();
 266     break;
 267
 268   case PNIC_REG_LEN:
 269     if (value > PNIC_DATA_SIZE)
 270       BX_PANIC(("PNIC bad length %u written to length register, max is %u",
 271                 value, PNIC_DATA_SIZE));
 272     BX_PNIC_THIS s.rLength = value;
 273     BX_PNIC_THIS s.rDataCursor = 0;
 274     break;
 275
 276   case PNIC_REG_DATA:
 277     if (BX_PNIC_THIS s.rDataCursor >= BX_PNIC_THIS s.rLength)
 278       BX_PANIC(("PNIC write at %u, beyond end of data register array",
 279                 BX_PNIC_THIS s.rDataCursor));
 280     BX_PNIC_THIS s.rData[BX_PNIC_THIS s.rDataCursor++] = value;
 281     break;
 282
 283   default:
 284     BX_PANIC(("unsupported io write to address=0x%04x!", (unsigned) address));
 285     break;
 286   }
 287 }
 288
 289 void bx_pcipnic_c::pnic_timer_handler(void *this_ptr)
 290 {
 291   bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) this_ptr;
 292   class_ptr->pnic_timer();
 293 }
 294
 295 // Called once every 1ms
 296 void bx_pcipnic_c::pnic_timer(void)
 297 {
 298   // Do nothing atm
 299
 300 }
 301
 302 // pci configuration space read callback handler
 303 Bit32u bx_pcipnic_c::pci_read_handler(Bit8u address, unsigned io_len)
 304 {
 305   Bit32u value = 0;
 306
 307   if (io_len > 4 || io_len == 0) {
 308     BX_ERROR(("Experimental PNIC PCI read register 0x%02x, len=%u !",
 309              (unsigned) address, (unsigned) io_len));
 310     return 0xffffffff;
 311   }
 312
 313   const char* pszName = "                  ";
 314   switch (address) {
 315     case 0x00: if (io_len == 2) {
 316                  pszName = "(vendor id)       ";
 317                } else if (io_len == 4) {
 318                  pszName = "(vendor + device) ";
 319                }
 320       break;
 321     case 0x04: if (io_len == 2) {
 322                  pszName = "(command)         ";
 323                } else if (io_len == 4) {
 324                  pszName = "(command+status)  ";
 325                }
 326       break;
 327     case 0x08: if (io_len == 1) {
 328                  pszName = "(revision id)     ";
 329                } else if (io_len == 4) {
 330                  pszName = "(rev.+class code) ";
 331                }
 332       break;
 333     case 0x0c: pszName = "(cache line size) "; break;
 334     case 0x20: pszName = "(base address)    "; break;
 335     case 0x28: pszName = "(cardbus cis)     "; break;
 336     case 0x2c: pszName = "(subsys. vendor+) "; break;
 337     case 0x30: pszName = "(rom base)        "; break;
 338     case 0x3c: pszName = "(interrupt line+) "; break;
 339     case 0x3d: pszName = "(interrupt pin)   "; break;
 340   }
 341
 342   // This odd code is to display only what bytes actually were read.
 343   char szTmp[9];
 344   char szTmp2[3];
 345   szTmp[0] = '\0';
 346   szTmp2[0] = '\0';
 347   for (unsigned i=0; i<io_len; i++) {
 348     value |= (BX_PNIC_THIS s.pci_conf[address+i] << (i*8));
 349     sprintf(szTmp2, "%02x", (BX_PNIC_THIS s.pci_conf[address+i]));
 350     strrev(szTmp2);
 351     strcat(szTmp, szTmp2);
 352   }
 353   strrev(szTmp);
 354   BX_DEBUG(("Experimental PNIC PCI read register 0x%02x %svalue 0x%s",
 355             address, pszName, szTmp));
 356   return value;
 357 }
 358
 359
 360 // pci configuration space write callback handler
 361 void bx_pcipnic_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
 362 {
 363   Bit8u value8, oldval;
 364   bx_bool baseaddr_change = 0;
 365
 366   if (((address >= 0x10) && (address < 0x20)) ||
 367       ((address > 0x23) && (address < 0x34)))
 368     return;
 369
 370   // This odd code is to display only what bytes actually were written.
 371   char szTmp[9];
 372   char szTmp2[3];
 373   szTmp[0] = '\0';
 374   szTmp2[0] = '\0';
 375   if (io_len <= 4) {
 376     for (unsigned i=0; i<io_len; i++) {
 377       value8 = (value >> (i*8)) & 0xFF;
 378       oldval = BX_PNIC_THIS s.pci_conf[address+i];
 379       switch (address+i) {
 380         case 0x3d: //
 381         case 0x05: // disallowing write to command hi-byte
 382         case 0x06: // disallowing write to status lo-byte (is that expected?)
 383           strcpy(szTmp2, "..");
 384           break;
 385         case 0x3c:
 386           if (value8 != oldval) {
 387             BX_INFO(("new irq line = %d", value8));
 388             BX_PNIC_THIS s.pci_conf[address+i] = value8;
 389           }
 390           break;
 391         case 0x20:
 392           value8 = (value8 & 0xfc) | 0x01;
 393         case 0x21:
 394         case 0x22:
 395         case 0x23:
 396           baseaddr_change = (value8 != oldval);
 397         default:
 398           BX_PNIC_THIS s.pci_conf[address+i] = value8;
 399           sprintf(szTmp2, "%02x", value8);
 400       }
 401       strrev(szTmp2);
 402       strcat(szTmp, szTmp2);
 403     }
 404     if (baseaddr_change) {
 405       if (DEV_pci_set_base_io(BX_PNIC_THIS_PTR, read_handler, write_handler,
 406                               &BX_PNIC_THIS s.base_ioaddr,
 407                               &BX_PNIC_THIS s.pci_conf[0x20],
 408                               16, &pnic_iomask[0], "PNIC")) {
 409         BX_INFO(("new base address: 0x%04x", BX_PNIC_THIS s.base_ioaddr));
 410       }
 411     }
 412   }
 413   strrev(szTmp);
 414   BX_DEBUG(("Experimental PNIC PCI write register 0x%02x value 0x%s", address, szTmp));
 415 }
 416
 417
 418 /*
 419  * Execute a hardware command.
 420  */
 421 void bx_pcipnic_c::exec_command(void)
 422 {
 423   Bit16u command = BX_PNIC_THIS s.rCmd;
 424   Bit16u ilength = BX_PNIC_THIS s.rLength;
 425   Bit8u *data    = BX_PNIC_THIS s.rData;
 426   // Default return values
 427   Bit16u status  = PNIC_STATUS_UNKNOWN_CMD;
 428   Bit16u olength = 0;
 429
 430   if (ilength != BX_PNIC_THIS s.rDataCursor)
 431     BX_PANIC(("PNIC command issued with incomplete data (should be %u, is %u)",
 432               ilength, BX_PNIC_THIS s.rDataCursor));
 433
 434   switch (command) {
 435   case PNIC_CMD_NOOP:
 436     status = PNIC_STATUS_OK;
 437     break;
 438
 439   case PNIC_CMD_API_VER:
 440     Bit16u api_version;
 441
 442     api_version = PNIC_API_VERSION;
 443     olength = sizeof(api_version);
 444     memcpy (data, &api_version, sizeof(api_version));
 445     status = PNIC_STATUS_OK;
 446     break;
 447
 448   case PNIC_CMD_READ_MAC:
 449     olength = sizeof (BX_PNIC_THIS s.macaddr);
 450     memcpy (data, BX_PNIC_THIS s.macaddr, olength);
 451     status = PNIC_STATUS_OK;
 452     break;
 453
 454   case PNIC_CMD_RESET:
 455     /* Flush the receive queue */
 456     BX_PNIC_THIS s.recvQueueLength = 0;
 457     status = PNIC_STATUS_OK;
 458     break;
 459
 460   case PNIC_CMD_XMIT:
 461     BX_PNIC_THIS ethdev->sendpkt(data, ilength);
 462     if (BX_PNIC_THIS s.irqEnabled) {
 463       set_irq_level(1);
 464     }
 465     status = PNIC_STATUS_OK;
 466     break;
 467
 468   case PNIC_CMD_RECV:
 469     if (BX_PNIC_THIS s.recvQueueLength > 0) {
 470       int idx = (BX_PNIC_THIS s.recvIndex - BX_PNIC_THIS s.recvQueueLength
 471                   + PNIC_RECV_RINGS) % PNIC_RECV_RINGS;
 472       olength = BX_PNIC_THIS s.recvRingLength[idx];
 473       memcpy (data, BX_PNIC_THIS s.recvRing[idx], olength);
 474       BX_PNIC_THIS s.recvQueueLength--;
 475     }
 476     if (! BX_PNIC_THIS s.recvQueueLength) {
 477       set_irq_level(0);
 478     }
 479     status = PNIC_STATUS_OK;
 480     break;
 481
 482   case PNIC_CMD_RECV_QLEN:
 483     Bit16u qlen;
 484
 485     qlen = BX_PNIC_THIS s.recvQueueLength;
 486     olength = sizeof(qlen);
 487     memcpy (data, &qlen, sizeof(qlen));
 488     status = PNIC_STATUS_OK;
 489     break;
 490
 491   case PNIC_CMD_MASK_IRQ:
 492     Bit8u enabled;
 493
 494     enabled = *((Bit8u*)data);
 495     BX_PNIC_THIS s.irqEnabled = enabled;
 496     if (enabled && BX_PNIC_THIS s.recvQueueLength) {
 497       set_irq_level(1);
 498     } else {
 499       set_irq_level(0);
 500     }
 501     status = PNIC_STATUS_OK;
 502     break;
 503
 504   case PNIC_CMD_FORCE_IRQ:
 505     set_irq_level(1);
 506     status = PNIC_STATUS_OK;
 507     break;
 508
 509   default:
 510     BX_ERROR(("Unknown PNIC command %x (data length %u)", command, ilength));
 511     status = PNIC_STATUS_UNKNOWN_CMD;
 512     break;
 513   }
 514
 515   // Set registers
 516   BX_PNIC_THIS s.rStatus = status;
 517   BX_PNIC_THIS s.rLength = olength;
 518   BX_PNIC_THIS s.rDataCursor = 0;
 519 }
 520
 521 /*
 522  * Callback from the eth system driver when a frame has arrived
 523  */
 524 void bx_pcipnic_c::rx_handler(void *arg, const void *buf, unsigned len)
 525 {
 526     // BX_DEBUG(("rx_handler with length %d", len));
 527   bx_pcipnic_c *class_ptr = (bx_pcipnic_c *) arg;
 528   class_ptr->rx_frame(buf, len);
 529 }
 530
 531 /*
 532  * rx_frame() - called by the platform-specific code when an
 533  * ethernet frame has been received. The destination address
 534  * is tested to see if it should be accepted, and if the
 535  * rx ring has enough room, it is copied into it and
 536  * the receive process is updated
 537  */
 538 void bx_pcipnic_c::rx_frame(const void *buf, unsigned io_len)
 539 {
 540   // Check packet length
 541   if (io_len > PNIC_DATA_SIZE) {
 542     BX_PANIC(("PNIC receive: data size %u exceeded buffer size %u",
 543        io_len, PNIC_DATA_SIZE));
 544     // Truncate if user continues
 545     io_len = PNIC_DATA_SIZE;
 546   }
 547   // Check receive ring is not full
 548   if (BX_PNIC_THIS s.recvQueueLength == PNIC_RECV_RINGS) {
 549     BX_ERROR(("PNIC receive: receive ring full, discarding packet"));
 550     return;
 551   }
 552   // Copy data to receive ring and record length
 553   memcpy (BX_PNIC_THIS s.recvRing[BX_PNIC_THIS s.recvIndex], buf, io_len);
 554   BX_PNIC_THIS s.recvRingLength[BX_PNIC_THIS s.recvIndex] = io_len;
 555   // Move to next ring entry
 556   BX_PNIC_THIS s.recvIndex = (BX_PNIC_THIS s.recvIndex + 1) % PNIC_RECV_RINGS;
 557   BX_PNIC_THIS s.recvQueueLength++;
 558
 559   // Generate interrupt if enabled
 560   if (BX_PNIC_THIS s.irqEnabled) {
 561     set_irq_level(1);
 562   }
 563 }
 564
 565 #endif // BX_SUPPORT_PCI && BX_SUPPORT_PCIPNIC