stage2/gelic.h

   1 /*  gelic.h - definitons for the debug.h - printf message logging via Lv-1 Ethernet
   2
   3 Copyright (C) 2010-2011  Hector Martin "marcan" <hector@marcansoft.com>
   4
   5 This code is licensed to you under the terms of the GNU GPL, version 2;
   6 see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
   7
   8 Portions taken from Linux (drivers/net/ps3_gelic_net.h):
   9
  10  *  PS3 Platfom gelic definitions.
  11  *
  12  * Copyright (C) 2010-2011 Hector Martin "marcan" <hector@marcansoft.com>
  13  *
  14  * Copyright (C) 2007 Sony Computer Entertainment Inc.
  15  * Copyright 2006, 2007 Sony Corporation.
  16  *
  17  * This file is based on: spider_net.h
  18  *
  19  * (C) Copyright IBM Corp. 2005
  20  *
  21  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
  22  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
  23 */
  24
  25 #ifndef GELIC_H
  26 #define GELIC_H
  27
  28 #include "types.h"
  29
  30  /* RX descriptor data_status bits */
  31 enum gelic_descr_rx_status {
  32         GELIC_DESCR_RXDMADU             = 0x80000000, /* destination MAC addr unknown */
  33         GELIC_DESCR_RXLSTFBF    = 0x40000000, /* last frame buffer            */
  34         GELIC_DESCR_RXIPCHK             = 0x20000000, /* IP checksum performed        */
  35         GELIC_DESCR_RXTCPCHK    = 0x10000000, /* TCP/UDP checksup performed   */
  36         GELIC_DESCR_RXWTPKT             = 0x00C00000, /*
  37                                                                                * wakeup trigger packet
  38                                                                                * 01: Magic Packet (TM)
  39                                                                                * 10: ARP packet
  40                                                                                * 11: Multicast MAC addr
  41                                                                                */
  42         GELIC_DESCR_RXVLNPKT    = 0x00200000, /* VLAN packet */
  43         /* bit 20..16 reserved */
  44         GELIC_DESCR_RXRRECNUM   = 0x0000ff00, /* reception receipt number */
  45         /* bit 7..0 reserved */
  46 };
  47
  48 #define GELIC_DESCR_DATA_STATUS_CHK_MASK        \
  49         (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
  50
  51  /* TX descriptor data_status bits */
  52 enum gelic_descr_tx_status {
  53         GELIC_DESCR_TX_TAIL     = 0x00000001, /* gelic treated this
  54                                                                        * descriptor was end of
  55                                                                        * a tx frame
  56                                                                        */
  57 };
  58
  59 /* RX descriptor data error bits */
  60 enum gelic_descr_rx_error {
  61         /* bit 31 reserved */
  62         GELIC_DESCR_RXALNERR    = 0x40000000, /* alignement error 10/100M */
  63         GELIC_DESCR_RXOVERERR   = 0x20000000, /* oversize error */
  64         GELIC_DESCR_RXRNTERR    = 0x10000000, /* Runt error */
  65         GELIC_DESCR_RXIPCHKERR  = 0x08000000, /* IP checksum  error */
  66         GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum  error */
  67         GELIC_DESCR_RXDRPPKT    = 0x00100000, /* drop packet */
  68         GELIC_DESCR_RXIPFMTERR  = 0x00080000, /* IP packet format error */
  69         /* bit 18 reserved */
  70         GELIC_DESCR_RXDATAERR   = 0x00020000, /* IP packet format error */
  71         GELIC_DESCR_RXCALERR    = 0x00010000, /* cariier extension length
  72                                                                                * error */
  73         GELIC_DESCR_RXCREXERR   = 0x00008000, /* carrier extention error */
  74         GELIC_DESCR_RXMLTCST    = 0x00004000, /* multicast address frame */
  75         /* bit 13..0 reserved */
  76 };
  77 #define GELIC_DESCR_DATA_ERROR_CHK_MASK         \
  78         (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
  79
  80 /* DMA command and status (RX and TX)*/
  81 enum gelic_descr_dma_status {
  82         GELIC_DESCR_DMA_COMPLETE            = 0x00000000, /* used in tx */
  83         GELIC_DESCR_DMA_BUFFER_FULL         = 0x00000000, /* used in rx */
  84         GELIC_DESCR_DMA_RESPONSE_ERROR      = 0x10000000, /* used in rx, tx */
  85         GELIC_DESCR_DMA_PROTECTION_ERROR    = 0x20000000, /* used in rx, tx */
  86         GELIC_DESCR_DMA_FRAME_END           = 0x40000000, /* used in rx */
  87         GELIC_DESCR_DMA_FORCE_END           = 0x50000000, /* used in rx, tx */
  88         GELIC_DESCR_DMA_CARDOWNED           = 0xa0000000, /* used in rx, tx */
  89         GELIC_DESCR_DMA_NOT_IN_USE          = 0xb0000000, /* any other value */
  90 };
  91
  92 #define GELIC_DESCR_DMA_STAT_MASK       (0xf0000000)
  93
  94 /* tx descriptor command and status */
  95 enum gelic_descr_tx_dma_status {
  96         /* [19] */
  97         GELIC_DESCR_TX_DMA_IKE                  = 0x00080000, /* IPSEC off */
  98         /* [18] */
  99         GELIC_DESCR_TX_DMA_FRAME_TAIL   = 0x00040000, /* last descriptor of
 100                                                                                                * the packet
 101                                                                                                */
 102         /* [17..16] */
 103         GELIC_DESCR_TX_DMA_TCP_CHKSUM   = 0x00020000, /* TCP packet */
 104         GELIC_DESCR_TX_DMA_UDP_CHKSUM   = 0x00030000, /* UDP packet */
 105         GELIC_DESCR_TX_DMA_NO_CHKSUM    = 0x00000000, /* no checksum */
 106
 107         /* [1] */
 108         GELIC_DESCR_TX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 109                                                                                                * due to chain end
 110                                                                                                */
 111 };
 112
 113 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM   \
 114         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 115         GELIC_DESCR_TX_DMA_NO_CHKSUM)
 116
 117 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM  \
 118         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 119         GELIC_DESCR_TX_DMA_TCP_CHKSUM)
 120
 121 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM  \
 122         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 123         GELIC_DESCR_TX_DMA_UDP_CHKSUM)
 124
 125 enum gelic_descr_rx_dma_status {
 126         /* [ 1 ] */
 127         GELIC_DESCR_RX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 128                                                                                                * due to chain end
 129                                                                                                */
 130 };
 131
 132 /* for lv1_net_control */
 133 enum gelic_lv1_net_control_code {
 134         GELIC_LV1_GET_MAC_ADDRESS               = 1,
 135         GELIC_LV1_GET_ETH_PORT_STATUS   = 2,
 136         GELIC_LV1_SET_NEGOTIATION_MODE  = 3,
 137         GELIC_LV1_GET_VLAN_ID                   = 4,
 138         GELIC_LV1_SET_WOL                               = 5,
 139         GELIC_LV1_GET_CHANNEL                   = 6,
 140         GELIC_LV1_POST_WLAN_CMD                 = 9,
 141         GELIC_LV1_GET_WLAN_CMD_RESULT   = 10,
 142         GELIC_LV1_GET_WLAN_EVENT                = 11,
 143 };
 144
 145 /* for GELIC_LV1_WOL_MAGIC_PACKET */
 146 enum gelic_lv1_wol_mp_arg {
 147         GELIC_LV1_WOL_MP_DISABLE        = 0,
 148         GELIC_LV1_WOL_MP_ENABLE         = 1,
 149 };
 150
 151 /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
 152 enum gelic_lv1_wol_match_arg {
 153         GELIC_LV1_WOL_MATCH_INDIVIDUAL  = 0,
 154         GELIC_LV1_WOL_MATCH_ALL         = 1,
 155 };
 156
 157 /* status returened from GET_ETH_PORT_STATUS */
 158 enum gelic_lv1_ether_port_status {
 159         GELIC_LV1_ETHER_LINK_UP         = 0x0000000000000001L,
 160         GELIC_LV1_ETHER_FULL_DUPLEX     = 0x0000000000000002L,
 161         GELIC_LV1_ETHER_AUTO_NEG        = 0x0000000000000004L,
 162
 163         GELIC_LV1_ETHER_SPEED_10        = 0x0000000000000010L,
 164         GELIC_LV1_ETHER_SPEED_100       = 0x0000000000000020L,
 165         GELIC_LV1_ETHER_SPEED_1000      = 0x0000000000000040L,
 166         GELIC_LV1_ETHER_SPEED_MASK      = 0x0000000000000070L,
 167 };
 168
 169 enum gelic_lv1_vlan_index {
 170         /* for outgoing packets */
 171         GELIC_LV1_VLAN_TX_ETHERNET_0    = 0x0000000000000002L,
 172         GELIC_LV1_VLAN_TX_WIRELESS      = 0x0000000000000003L,
 173
 174         /* for incoming packets */
 175         GELIC_LV1_VLAN_RX_ETHERNET_0    = 0x0000000000000012L,
 176         GELIC_LV1_VLAN_RX_WIRELESS      = 0x0000000000000013L,
 177 };
 178
 179 enum gelic_lv1_phy {
 180         GELIC_LV1_PHY_ETHERNET_0        = 0x0000000000000002L,
 181 };
 182
 183 /* size of hardware part of gelic descriptor */
 184 #define GELIC_DESCR_SIZE        (32)
 185
 186 enum gelic_port_type {
 187         GELIC_PORT_ETHERNET_0   = 0,
 188         GELIC_PORT_WIRELESS     = 1,
 189         GELIC_PORT_MAX
 190 };
 191
 192 struct gelic_descr {
 193         /* as defined by the hardware */
 194         u32 buf_addr;
 195         u32 buf_size;
 196         u32 next_descr_addr;
 197         u32 dmac_cmd_status;
 198         u32 result_size;
 199         u32 valid_size; /* all zeroes for tx */
 200         u32 data_status;
 201         u32 data_error; /* all zeroes for tx */
 202 } __attribute__((aligned(32)));
 203
 204 #endif