| blob | 519f70962e151c5f558dd48918ca57d14f206305 |
1 From 95b0363f57ca13c9421204b735926f4a99e2d844 Mon Sep 17 00:00:00 2001
2 From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
3 Date: Fri, 15 Aug 2008 01:55:54 +0300
4 Subject: [PATCH 05/10] TI DSP BRIDGE: Hardware Interfaces
6 Initial port from omapzoom
7 http://omapzoom.org/gf/project/omapbridge
9 For details,
10 http://omapzoom.org/gf/project/omapbridge/docman/?subdir=3
12 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
13 ---
14 drivers/dsp/bridge/hw/EasiBase.h | 179 +++++++++
15 drivers/dsp/bridge/hw/EasiGlobal.h | 42 +++
16 drivers/dsp/bridge/hw/GlobalTypes.h | 328 +++++++++++++++++
17 drivers/dsp/bridge/hw/IPIAccInt.h | 41 ++
18 drivers/dsp/bridge/hw/IVA2RegAcM.h | 28 ++
19 drivers/dsp/bridge/hw/MLBAccInt.h | 132 +++++++
20 drivers/dsp/bridge/hw/MLBRegAcM.h | 200 ++++++++++
21 drivers/dsp/bridge/hw/MMUAccInt.h | 79 ++++
22 drivers/dsp/bridge/hw/MMURegAcM.h | 267 ++++++++++++++
23 drivers/dsp/bridge/hw/PRCMAccInt.h | 300 +++++++++++++++
24 drivers/dsp/bridge/hw/PRCMRegAcM.h | 669 ++++++++++++++++++++++++++++++++++
25 drivers/dsp/bridge/hw/hw_defs.h | 73 ++++
26 drivers/dsp/bridge/hw/hw_dspssC64P.c | 55 +++
27 drivers/dsp/bridge/hw/hw_dspssC64P.h | 48 +++
28 drivers/dsp/bridge/hw/hw_mbox.c | 255 +++++++++++++
29 drivers/dsp/bridge/hw/hw_mbox.h | 358 ++++++++++++++++++
30 drivers/dsp/bridge/hw/hw_mmu.c | 607 ++++++++++++++++++++++++++++++
31 drivers/dsp/bridge/hw/hw_mmu.h | 178 +++++++++
32 drivers/dsp/bridge/hw/hw_prcm.c | 167 +++++++++
33 drivers/dsp/bridge/hw/hw_prcm.h | 168 +++++++++
34 20 files changed, 4174 insertions(+), 0 deletions(-)
35 create mode 100644 drivers/dsp/bridge/hw/EasiBase.h
36 create mode 100644 drivers/dsp/bridge/hw/EasiGlobal.h
37 create mode 100644 drivers/dsp/bridge/hw/GlobalTypes.h
38 create mode 100644 drivers/dsp/bridge/hw/IPIAccInt.h
39 create mode 100644 drivers/dsp/bridge/hw/IVA2RegAcM.h
40 create mode 100644 drivers/dsp/bridge/hw/MLBAccInt.h
41 create mode 100644 drivers/dsp/bridge/hw/MLBRegAcM.h
42 create mode 100644 drivers/dsp/bridge/hw/MMUAccInt.h
43 create mode 100644 drivers/dsp/bridge/hw/MMURegAcM.h
44 create mode 100644 drivers/dsp/bridge/hw/PRCMAccInt.h
45 create mode 100644 drivers/dsp/bridge/hw/PRCMRegAcM.h
46 create mode 100644 drivers/dsp/bridge/hw/hw_defs.h
47 create mode 100644 drivers/dsp/bridge/hw/hw_dspssC64P.c
48 create mode 100644 drivers/dsp/bridge/hw/hw_dspssC64P.h
49 create mode 100644 drivers/dsp/bridge/hw/hw_mbox.c
50 create mode 100644 drivers/dsp/bridge/hw/hw_mbox.h
51 create mode 100644 drivers/dsp/bridge/hw/hw_mmu.c
52 create mode 100644 drivers/dsp/bridge/hw/hw_mmu.h
53 create mode 100644 drivers/dsp/bridge/hw/hw_prcm.c
54 create mode 100644 drivers/dsp/bridge/hw/hw_prcm.h
56 diff --git a/drivers/dsp/bridge/hw/EasiBase.h b/drivers/dsp/bridge/hw/EasiBase.h
57 new file mode 100644
58 index 0000000..aa61d21
59 --- /dev/null
60 +++ b/drivers/dsp/bridge/hw/EasiBase.h
61 @@ -0,0 +1,179 @@
62 +/*
63 + * linux/drivers/dsp/bridge/hw/omap3/inc/EasiBase.h
64 + *
65 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
66 + *
67 + * Copyright (C) 2007 Texas Instruments, Inc.
68 + *
69 + * This package is free software; you can redistribute it and/or modify
70 + * it under the terms of the GNU General Public License version 2 as
71 + * published by the Free Software Foundation.
72 + *
73 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
74 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
75 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
76 + */
77 +
78 +#ifndef __EASIBASE_H
79 +#define __EASIBASE_H
80 +
81 +/* ----------------------------------------------------------------------------
82 +* DEFINE: ****_BASE_ID
83 +*
84 +* DESCRIPTION: These are registser BASE IDs that will be used to identify
85 +* errors when doing the EASI-Checker register tests
86 +*
87 +* NOTE: The values of these defines will be defined at a later stage.
88 +* TBD
89 +*
90 +* -----------------------------------------------------------------------------
91 +*/
92 +
93 +#define OSPL1_BASE_ID 0
94 +#define D3D1_BASE_ID 0
95 +#define MBSP1_BASE_ID 0
96 +#define MBSP2_BASE_ID 0
97 +#define MSDI1_BASE_ID 0
98 +#define RNG1_BASE_ID 0
99 +#define SHAM1_BASE_ID 0
100 +#define RFBI1_BASE_ID 0
101 +#define DISC1_BASE_ID 0
102 +#define DSS1_BASE_ID 0
103 +#define MLB1_BASE_ID 0
104 +#define IPI1_BASE_ID 0
105 +#define PDMA1_BASE_ID 0
106 +#define PRCM_BASE_ID 0
107 +#define SDMA1_BASE_ID 0
108 +#define SDRC1_BASE_ID 0
109 +#define ST1_BASE_ID 0
110 +#define SMS1_BASE_ID 0
111 +#define WDT1_BASE_ID 0
112 +#define WDT2_BASE_ID 0
113 +#define WDT3_BASE_ID 0
114 +#define WDT4_BASE_ID 0
115 +#define INTC1_BASE_ID 0
116 +#define INTC2_BASE_ID 0
117 +#define MMU1_BASE_ID 0
118 +#define GPMC1_BASE_ID 0
119 +#define GPT1_BASE_ID 0
120 +#define GPT2_BASE_ID 0
121 +#define GPT3_BASE_ID 0
122 +#define GPT4_BASE_ID 0
123 +#define GPT5_BASE_ID 0
124 +#define GPT6_BASE_ID 0
125 +#define GPT7_BASE_ID 0
126 +#define GPT8_BASE_ID 0
127 +#define GPT9_BASE_ID 0
128 +#define GPT10_BASE_ID 0
129 +#define GPT11_BASE_ID 0
130 +#define GPT12_BASE_ID 0
131 +#define WTR1_BASE_ID 0
132 +#define WTR2_BASE_ID 0
133 +#define WTR3_BASE_ID 0
134 +#define WTR4_BASE_ID 0
135 +#define I2C1_BASE_ID 0
136 +#define I2C2_BASE_ID 0
137 +#define T32K1_BASE_ID 0
138 +#define PRCM1_BASE_ID 0
139 +
140 +#define AES1_BASE_ID 0
141 +#define C2CF1_BASE_ID 0
142 +#define DSPF1_BASE_ID 0
143 +#define FAC1_BASE_ID 0
144 +#define GPMF1_BASE_ID 0
145 +#define GPIO1_BASE_ID 0
146 +#define GPIO2_BASE_ID 0
147 +#define GPIO3_BASE_ID 0
148 +#define GPIO4_BASE_ID 0
149 +#define HDQW1_BASE_ID 0
150 +#define PKA1_BASE_ID 0
151 +
152 +#define IM1_BASE_ID 0
153 +#define IM2_BASE_ID 0
154 +#define IM3_BASE_ID 0
155 +#define IM4_BASE_ID 0
156 +#define IM5_BASE_ID 0
157 +#define IM6_BASE_ID 0
158 +#define IM7_BASE_ID 0
159 +#define IM8_BASE_ID 0
160 +#define IMA1_BASE_ID 0
161 +#define IMTM1_BASE_ID 0
162 +#define IVAF1_BASE_ID 0
163 +#define LRCR1_BASE_ID 0
164 +#define LRCR2_BASE_ID 0
165 +#define LRCS1_BASE_ID 0
166 +#define LRCS2_BASE_ID 0
167 +#define RAMF1_BASE_ID 0
168 +#define ROMF1_BASE_ID 0
169 +#define TM1_BASE_ID 0
170 +#define TML1_BASE_ID 0
171 +#define TML2_BASE_ID 0
172 +#define TML3_BASE_ID 0
173 +#define TML4_BASE_ID 0
174 +#define TML5_BASE_ID 0
175 +#define TML6_BASE_ID 0
176 +
177 +
178 +
179 +/* ----------------------------------------------------------------------------
180 +* DEFINE: ***_BASE_EASIL1
181 +*
182 +* DESCRIPTION: These are registser BASE EASIl1 numbers that can be used to
183 +* identify what EASI C functions have been called.
184 +*
185 +* NOTE: The values of these defines will be defined at a later stage.
186 +* TBD
187 +*
188 +* -----------------------------------------------------------------------------
189 +*/
190 +
191 +#define OSPL1_BASE_EASIL1 0
192 +#define D3D_BASE_EASIL1 0
193 +#define MBSP_BASE_EASIL1 0
194 +#define MSDI_BASE_EASIL1 0
195 +#define RNG_BASE_EASIL1 0
196 +#define SHAM_BASE_EASIL1 0
197 +#define RFBI_BASE_EASIL1 0
198 +#define DISC_BASE_EASIL1 0
199 +#define DSS_BASE_EASIL1 0
200 +#define MLB_BASE_EASIL1 0
201 +#define IPI_BASE_EASIL1 0
202 +#define PDMA_BASE_EASIL1 0
203 +#define SDMA_BASE_EASIL1 0
204 +#define SDRC_BASE_EASIL1 0
205 +#define ST_BASE_EASIL1 0
206 +#define SMS_BASE_EASIL1 0
207 +#define WDT1_BASE_EASIL1 0
208 +#define INTC1_BASE_EASIL1 0
209 +#define INTC2_BASE_EASIL1 0
210 +#define MMU1_BASE_EASIL1 0
211 +#define GPMC_BASE_EASIL1 0
212 +#define GPT_BASE_EASIL1 0
213 +#define WTR_BASE_EASIL1 0
214 +#define MBSP2_BASE_EASIL1 0
215 +#define I2C1_BASE_EASIL1 0
216 +#define I2C2_BASE_EASIL1 0
217 +#define T32K1_BASE_EASIL1 0
218 +#define PRCM1_BASE_EASIL1 0
219 +
220 +#define AES1_BASE_EASIL1 0
221 +#define C2CF1_BASE_EASIL1 0
222 +#define DSPF1_BASE_EASIL1 0
223 +#define FAC1_BASE_EASIL1 0
224 +#define GPMF1_BASE_EASIL1 0
225 +#define GPIO1_BASE_EASIL1 0
226 +#define HDQW1_BASE_EASIL1 0
227 +#define PKA1_BASE_EASIL1 0
228 +
229 +#define IMA_BASE_EASIL1 0
230 +#define IM_BASE_EASIL1 0
231 +#define IMTM_BASE_EASIL1 0
232 +#define IVAF_BASE_EASIL1 0
233 +#define LRCR_BASE_EASIL1 0
234 +#define LRCS_BASE_EASIL1 0
235 +#define RAMF_BASE_EASIL1 0
236 +#define ROMF_BASE_EASIL1 0
237 +#define TML_BASE_EASIL1 0
238 +#define TM_BASE_EASIL1 0
239 +
240 +#endif /* __EASIBASE_H */
241 diff --git a/drivers/dsp/bridge/hw/EasiGlobal.h b/drivers/dsp/bridge/hw/EasiGlobal.h
242 new file mode 100644
243 index 0000000..b6045fd
244 --- /dev/null
245 +++ b/drivers/dsp/bridge/hw/EasiGlobal.h
246 @@ -0,0 +1,42 @@
247 +/*
248 + * linux/drivers/dsp/bridge/hw/omap3/inc/EasiGlobal.h
249 + *
250 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
251 + *
252 + * Copyright (C) 2007 Texas Instruments, Inc.
253 + *
254 + * This package is free software; you can redistribute it and/or modify
255 + * it under the terms of the GNU General Public License version 2 as
256 + * published by the Free Software Foundation.
257 + *
258 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
259 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
260 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
261 + */
262 +
263 +#ifndef __EASIGLOBAL_H
264 +#define __EASIGLOBAL_H
265 +#include <linux/types.h>
266 +
267 +/*
268 + * DEFINE: READ_ONLY, WRITE_ONLY & READ_WRITE
269 + *
270 + * DESCRIPTION: Defines used to describe register types for EASI-checker tests.
271 + */
272 +
273 +#define READ_ONLY 1
274 +#define WRITE_ONLY 2
275 +#define READ_WRITE 3
276 +
277 +/*
278 + * MACRO: _DEBUG_LEVEL_1_EASI
279 + *
280 + * DESCRIPTION: A MACRO which can be used to indicate that a particular beach
281 + * register access function was called.
282 + *
283 + * NOTE: We currently dont use this functionality.
284 + */
285 +#define _DEBUG_LEVEL_1_EASI(easiNum) ((void)0)
286 +
287 +#endif /* __EASIGLOBAL_H */
288 +
289 diff --git a/drivers/dsp/bridge/hw/GlobalTypes.h b/drivers/dsp/bridge/hw/GlobalTypes.h
290 new file mode 100644
291 index 0000000..ac410f5
292 --- /dev/null
293 +++ b/drivers/dsp/bridge/hw/GlobalTypes.h
294 @@ -0,0 +1,328 @@
295 +/*
296 + * linux/drivers/dsp/bridge/hw/omap3/inc/GlobalTypes.h
297 + *
298 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
299 + *
300 + * Copyright (C) 2007 Texas Instruments, Inc.
301 + *
302 + * This package is free software; you can redistribute it and/or modify
303 + * it under the terms of the GNU General Public License version 2 as
304 + * published by the Free Software Foundation.
305 + *
306 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
307 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
308 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
309 + */
310 +
311 +
312 +/*
313 + * ======== GlobalTypes.h ========
314 + * Description:
315 + * Global HW definitions
316 + *
317 + *! Revision History:
318 + *! ================
319 + *! 16 Feb 2003 sb: Initial version
320 + */
321 +#ifndef __GLOBALTYPES_H
322 +#define __GLOBALTYPES_H
323 +
324 +/*
325 + * Definition: TRUE, FALSE
326 + *
327 + * DESCRIPTION: Boolean Definitions
328 + */
329 +#ifndef TRUE
330 +#define FALSE 0
331 +#define TRUE (!(FALSE))
332 +#endif
333 +
334 +/*
335 + * Definition: NULL
336 + *
337 + * DESCRIPTION: Invalid pointer
338 + */
339 +#ifndef NULL
340 +#define NULL (void *)0
341 +#endif
342 +
343 +/*
344 + * Definition: RET_CODE_BASE
345 + *
346 + * DESCRIPTION: Base value for return code offsets
347 + */
348 +#define RET_CODE_BASE 0
349 +
350 +/*
351 + * Definition: *BIT_OFFSET
352 + *
353 + * DESCRIPTION: offset in bytes from start of 32-bit word.
354 + */
355 +#define LOWER_16BIT_OFFSET 0
356 +#define UPPER_16BIT_OFFSET 2
357 +
358 +#define LOWER_8BIT_OFFSET 0
359 +#define LOWER_MIDDLE_8BIT_OFFSET 1
360 +#define UPPER_MIDDLE_8BIT_OFFSET 2
361 +#define UPPER_8BIT_OFFSET 3
362 +
363 +#define LOWER_8BIT_OF16_OFFSET 0
364 +#define UPPER_8BIT_OF16_OFFSET 1
365 +
366 +/*
367 + * Definition: *BIT_SHIFT
368 + *
369 + * DESCRIPTION: offset in bits from start of 32-bit word.
370 + */
371 +#define LOWER_16BIT_SHIFT 0
372 +#define UPPER_16BIT_SHIFT 16
373 +
374 +#define LOWER_8BIT_SHIFT 0
375 +#define LOWER_MIDDLE_8BIT_SHIFT 8
376 +#define UPPER_MIDDLE_8BIT_SHIFT 16
377 +#define UPPER_8BIT_SHIFT 24
378 +
379 +#define LOWER_8BIT_OF16_SHIFT 0
380 +#define UPPER_8BIT_OF16_SHIFT 8
381 +
382 +
383 +/*
384 + * Definition: LOWER_16BIT_MASK
385 + *
386 + * DESCRIPTION: 16 bit mask used for inclusion of lower 16 bits i.e. mask out
387 + * the upper 16 bits
388 + */
389 +#define LOWER_16BIT_MASK 0x0000FFFF
390 +
391 +
392 +/*
393 + * Definition: LOWER_8BIT_MASK
394 + *
395 + * DESCRIPTION: 8 bit masks used for inclusion of 8 bits i.e. mask out
396 + * the upper 16 bits
397 + */
398 +#define LOWER_8BIT_MASK 0x000000FF
399 +
400 +/*
401 + * Definition: RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits, upper16Bits)
402 + *
403 + * DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16
404 + * bit upper value
405 + */
406 +#define RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits,upper16Bits)\
407 + (((((u32)lower16Bits) & LOWER_16BIT_MASK)) | \
408 + (((((u32)upper16Bits) & LOWER_16BIT_MASK) << UPPER_16BIT_SHIFT)))
409 +
410 +/*
411 + * Definition: RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower16Bits, upper16Bits)
412 + *
413 + * DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8
414 + * bit upper value
415 + */
416 +#define RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower8Bits,upper8Bits)\
417 + (((((u32)lower8Bits) & LOWER_8BIT_MASK)) | \
418 + (((((u32)upper8Bits) & LOWER_8BIT_MASK) << UPPER_8BIT_OF16_SHIFT)))
419 +
420 +/*
421 + * Definition: RETURN_32BITS_FROM_4_8BIT_VALUES(lower8Bits, lowerMiddle8Bits,
422 + * lowerUpper8Bits, upper8Bits)
423 + *
424 + * DESCRIPTION: Returns a 32 bit value given four 8 bit values
425 + */
426 +#define RETURN_32BITS_FROM_4_8BIT_VALUES(lower8Bits, lowerMiddle8Bits,\
427 + lowerUpper8Bits, upper8Bits)\
428 + (((((u32)lower8Bits) & LOWER_8BIT_MASK)) | \
429 + (((((u32)lowerMiddle8Bits) & LOWER_8BIT_MASK) <<\
430 + LOWER_MIDDLE_8BIT_SHIFT)) | \
431 + (((((u32)lowerUpper8Bits) & LOWER_8BIT_MASK) <<\
432 + UPPER_MIDDLE_8BIT_SHIFT)) | \
433 + (((((u32)upper8Bits) & LOWER_8BIT_MASK) <<\
434 + UPPER_8BIT_SHIFT)))
435 +
436 +/*
437 + * Definition: READ_LOWER_16BITS_OF_32(value32bits)
438 + *
439 + * DESCRIPTION: Returns a 16 lower bits of 32bit value
440 + */
441 +#define READ_LOWER_16BITS_OF_32(value32bits)\
442 + ((u16)((u32)(value32bits) & LOWER_16BIT_MASK))
443 +
444 +/*
445 + * Definition: READ_UPPER_16BITS_OF_32(value32bits)
446 + *
447 + * DESCRIPTION: Returns a 16 lower bits of 32bit value
448 + */
449 +#define READ_UPPER_16BITS_OF_32(value32bits)\
450 + (((u16)((u32)(value32bits) >> UPPER_16BIT_SHIFT)) &\
451 + LOWER_16BIT_MASK)
452 +
453 +
454 +/*
455 + * Definition: READ_LOWER_8BITS_OF_32(value32bits)
456 + *
457 + * DESCRIPTION: Returns a 8 lower bits of 32bit value
458 + */
459 +#define READ_LOWER_8BITS_OF_32(value32bits)\
460 + ((u8)((u32)(value32bits) & LOWER_8BIT_MASK))
461 +
462 +/*
463 + * Definition: READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)
464 + *
465 + * DESCRIPTION: Returns a 8 lower middle bits of 32bit value
466 + */
467 +#define READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)\
468 + (((u8)((u32)(value32bits) >> LOWER_MIDDLE_8BIT_SHIFT)) &\
469 + LOWER_8BIT_MASK)
470 +
471 +/*
472 + * Definition: READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)
473 + *
474 + * DESCRIPTION: Returns a 8 lower middle bits of 32bit value
475 + */
476 +#define READ_UPPER_MIDDLE_8BITS_OF_32(value32bits)\
477 + (((u8)((u32)(value32bits) >> LOWER_MIDDLE_8BIT_SHIFT)) &\
478 + LOWER_8BIT_MASK)
479 +
480 +/*
481 + * Definition: READ_UPPER_8BITS_OF_32(value32bits)
482 + *
483 + * DESCRIPTION: Returns a 8 upper bits of 32bit value
484 + */
485 +#define READ_UPPER_8BITS_OF_32(value32bits)\
486 + (((u8)((u32)(value32bits) >> UPPER_8BIT_SHIFT)) & LOWER_8BIT_MASK)
487 +
488 +
489 +/*
490 + * Definition: READ_LOWER_8BITS_OF_16(value16bits)
491 + *
492 + * DESCRIPTION: Returns a 8 lower bits of 16bit value
493 + */
494 +#define READ_LOWER_8BITS_OF_16(value16bits)\
495 + ((u8)((u16)(value16bits) & LOWER_8BIT_MASK))
496 +
497 +/*
498 + * Definition: READ_UPPER_8BITS_OF_16(value32bits)
499 + *
500 + * DESCRIPTION: Returns a 8 upper bits of 16bit value
501 + */
502 +#define READ_UPPER_8BITS_OF_16(value16bits)\
503 + (((u8)((u32)(value16bits) >> UPPER_8BIT_SHIFT)) & LOWER_8BIT_MASK)
504 +
505 +/* 8 bit tpyes */
506 +typedef signed char WORD8;
507 +
508 +/* UWORD16: 16 bit tpyes */
509 +
510 +
511 +/* REG_UWORD8, REG_WORD8: 8 bit register types */
512 +typedef volatile unsigned char REG_UWORD8;
513 +typedef volatile signed char REG_WORD8;
514 +
515 +/* REG_UWORD16, REG_WORD16: 16 bit register types */
516 +#ifndef OMAPBRIDGE_TYPES
517 +typedef volatile unsigned short REG_UWORD16;
518 +#endif
519 +typedef volatile short REG_WORD16;
520 +
521 +/* REG_UWORD32, REG_WORD32: 32 bit register types */
522 +typedef volatile unsigned long REG_UWORD32;
523 +
524 +/* FLOAT
525 + *
526 + * Type to be used for floating point calculation. Note that floating point
527 + * calculation is very CPU expensive, and you should only use if you
528 + * absolutely need this. */
529 +#ifndef OMAPBRIDGE_TYPES
530 +typedef float FLOAT;
531 +#endif
532 +
533 +/* boolean_t: Boolean Type True, False */
534 +/* ReturnCode_t: Return codes to be returned by all library functions */
535 +typedef enum ReturnCode_label {
536 + RET_OK = 0,
537 + RET_FAIL = -1,
538 + RET_BAD_NULL_PARAM = -2,
539 + RET_PARAM_OUT_OF_RANGE = -3,
540 + RET_INVALID_ID = -4,
541 + RET_EMPTY = -5,
542 + RET_FULL = -6,
543 + RET_TIMEOUT = -7,
544 + RET_INVALID_OPERATION = -8,
545 +
546 + /* Add new error codes at end of above list */
547 +
548 + RET_NUM_RET_CODES /* this should ALWAYS be LAST entry */
549 +} ReturnCode_t, *pReturnCode_t;
550 +
551 +/* MACRO: RD_MEM_8, WR_MEM_8
552 + *
553 + * DESCRIPTION: 32 bit memory access macros
554 + */
555 +#define RD_MEM_8(addr) ((u8)(*((u8 *)(addr))))
556 +#define WR_MEM_8(addr, data) (*((u8 *)(addr)) = (u8)(data))
557 +
558 +/* MACRO: RD_MEM_8_VOLATILE, WR_MEM_8_VOLATILE
559 + *
560 + * DESCRIPTION: 8 bit register access macros
561 + */
562 +#define RD_MEM_8_VOLATILE(addr) ((u8)(*((REG_UWORD8 *)(addr))))
563 +#define WR_MEM_8_VOLATILE(addr, data) (*((REG_UWORD8 *)(addr)) = (u8)(data))
564 +
565 +
566 +/*
567 + * MACRO: RD_MEM_16, WR_MEM_16
568 + *
569 + * DESCRIPTION: 16 bit memory access macros
570 + */
571 +#define RD_MEM_16(addr) ((u16)(*((u16 *)(addr))))
572 +#define WR_MEM_16(addr, data) (*((u16 *)(addr)) = (u16)(data))
573 +
574 +/*
575 + * MACRO: RD_MEM_16_VOLATILE, WR_MEM_16_VOLATILE
576 + *
577 + * DESCRIPTION: 16 bit register access macros
578 + */
579 +#define RD_MEM_16_VOLATILE(addr) ((u16)(*((REG_UWORD16 *)(addr))))
580 +#define WR_MEM_16_VOLATILE(addr, data) (*((REG_UWORD16 *)(addr)) =\
581 + (u16)(data))
582 +
583 +/*
584 + * MACRO: RD_MEM_32, WR_MEM_32
585 + *
586 + * DESCRIPTION: 32 bit memory access macros
587 + */
588 +#define RD_MEM_32(addr) ((u32)(*((u32 *)(addr))))
589 +#define WR_MEM_32(addr, data) (*((u32 *)(addr)) = (u32)(data))
590 +
591 +/*
592 + * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE
593 + *
594 + * DESCRIPTION: 32 bit register access macros
595 + */
596 +#define RD_MEM_32_VOLATILE(addr) ((u32)(*((REG_UWORD32 *)(addr))))
597 +#define WR_MEM_32_VOLATILE(addr, data) (*((REG_UWORD32 *)(addr)) =\
598 + (u32)(data))
599 +
600 +/* Not sure if this all belongs here */
601 +
602 +#define CHECK_RETURN_VALUE(actualValue, expectedValue, returnCodeIfMismatch,\
603 + spyCodeIfMisMatch)
604 +#define CHECK_RETURN_VALUE_RET(actualValue, expectedValue, returnCodeIfMismatch)
605 +#define CHECK_RETURN_VALUE_RES(actualValue, expectedValue, spyCodeIfMisMatch)
606 +#define CHECK_RETURN_VALUE_RET_VOID(actualValue, expectedValue,\
607 + spyCodeIfMisMatch)
608 +
609 +#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\
610 + spyCodeIfMisMatch)
611 +#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue,\
612 + returnCodeIfMismatch)
613 +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue,\
614 + returnCodeIfMismatch, spyCodeIfMisMatch)
615 +#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue, maxValidValue,\
616 + returnCodeIfMismatch)
617 +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue,\
618 + returnCodeIfMismatch, spyCodeIfMisMatch)
619 +#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, maxValidValue,\
620 + returnCodeIfMismatch)
621 +
622 +#endif /* __GLOBALTYPES_H */
623 diff --git a/drivers/dsp/bridge/hw/IPIAccInt.h b/drivers/dsp/bridge/hw/IPIAccInt.h
624 new file mode 100644
625 index 0000000..e1dcca1
626 --- /dev/null
627 +++ b/drivers/dsp/bridge/hw/IPIAccInt.h
628 @@ -0,0 +1,41 @@
629 +/*
630 + * linux/drivers/dsp/bridge/hw/omap3/inc/IPIAccInt.h
631 + *
632 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
633 + *
634 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
635 + *
636 + * This package is free software; you can redistribute it and/or modify
637 + * it under the terms of the GNU General Public License version 2 as
638 + * published by the Free Software Foundation.
639 + *
640 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
641 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
642 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
643 + */
644 +
645 +#ifndef _IPI_ACC_INT_H
646 +#define _IPI_ACC_INT_H
647 +
648 +/* Bitfield mask and offset declarations */
649 +#define SYSC_IVA2BOOTMOD_OFFSET 0x404
650 +#define SYSC_IVA2BOOTADDR_OFFSET 0x400
651 +#define SYSC_IVA2BOOTADDR_MASK 0xfffffc00
652 +
653 +
654 +/* The following represent the enumerated values for each bitfield */
655 +
656 +enum IPIIPI_SYSCONFIGAutoIdleE {
657 + IPIIPI_SYSCONFIGAutoIdleclkfree = 0x0000,
658 + IPIIPI_SYSCONFIGAutoIdleautoclkgate = 0x0001
659 +} ;
660 +
661 +enum IPIIPI_ENTRYElemSizeValueE {
662 + IPIIPI_ENTRYElemSizeValueElemSz8b = 0x0000,
663 + IPIIPI_ENTRYElemSizeValueElemSz16b = 0x0001,
664 + IPIIPI_ENTRYElemSizeValueElemSz32b = 0x0002,
665 + IPIIPI_ENTRYElemSizeValueReserved = 0x0003
666 +} ;
667 +
668 +#endif /* _IPI_ACC_INT_H */
669 +/* EOF */
670 diff --git a/drivers/dsp/bridge/hw/IVA2RegAcM.h b/drivers/dsp/bridge/hw/IVA2RegAcM.h
671 new file mode 100644
672 index 0000000..2d7034d
673 --- /dev/null
674 +++ b/drivers/dsp/bridge/hw/IVA2RegAcM.h
675 @@ -0,0 +1,28 @@
676 +/*
677 + * linux/drivers/dsp/bridge/hw/omap3/dspss/IVA1RegAcM.h
678 + *
679 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
680 + *
681 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
682 + *
683 + * This package is free software; you can redistribute it and/or modify
684 + * it under the terms of the GNU General Public License version 2 as
685 + * published by the Free Software Foundation.
686 + *
687 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
688 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
689 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
690 + */
691 +
692 +
693 +
694 +#ifndef _IVA2_REG_ACM_H
695 +#define _IVA2_REG_ACM_H
696 +
697 +#include <GlobalTypes.h>
698 +#include <EasiGlobal.h>
699 +
700 +#define SYSC_IVA2BOOTMOD_OFFSET 0x404
701 +#define SYSC_IVA2BOOTADDR_OFFSET 0x400
702 +
703 +#endif
704 diff --git a/drivers/dsp/bridge/hw/MLBAccInt.h b/drivers/dsp/bridge/hw/MLBAccInt.h
705 new file mode 100644
706 index 0000000..e8a7fef
707 --- /dev/null
708 +++ b/drivers/dsp/bridge/hw/MLBAccInt.h
709 @@ -0,0 +1,132 @@
710 +/*
711 + * linux/drivers/dsp/bridge/hw/omap3/mbox/MLBAccInt.h
712 + *
713 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
714 + *
715 + * Copyright (C) 2007 Texas Instruments, Inc.
716 + *
717 + * This package is free software; you can redistribute it and/or modify
718 + * it under the terms of the GNU General Public License version 2 as
719 + * published by the Free Software Foundation.
720 + *
721 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
722 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
723 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
724 + */
725 +
726 +
727 +#ifndef _MLB_ACC_INT_H
728 +#define _MLB_ACC_INT_H
729 +
730 +/* Mappings of level 1 EASI function numbers to function names */
731 +
732 +#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32 (MLB_BASE_EASIL1 + 3)
733 +#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32 (MLB_BASE_EASIL1 + 4)
734 +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32 (MLB_BASE_EASIL1 + 7)
735 +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32 (MLB_BASE_EASIL1 + 17)
736 +#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29)
737 +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \
738 + (MLB_BASE_EASIL1 + 33)
739 +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32 (MLB_BASE_EASIL1 + 39)
740 +#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32 (MLB_BASE_EASIL1 + 44)
741 +#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \
742 + (MLB_BASE_EASIL1 + 50)
743 +#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32 \
744 + (MLB_BASE_EASIL1 + 51)
745 +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32 \
746 + (MLB_BASE_EASIL1 + 56)
747 +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \
748 + (MLB_BASE_EASIL1 + 57)
749 +#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32 \
750 + (MLB_BASE_EASIL1 + 60)
751 +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32 \
752 + (MLB_BASE_EASIL1 + 62)
753 +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \
754 + (MLB_BASE_EASIL1 + 63)
755 +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32 \
756 + (MLB_BASE_EASIL1 + 192)
757 +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32 \
758 + (MLB_BASE_EASIL1 + 193)
759 +
760 +/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address
761 + * increment and number of banks */
762 +
763 +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (u32)(0x0040)
764 +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (u32)(0x0004)
765 +
766 +/* Register offset address definitions relative to register set
767 + * MAILBOX_MESSAGE___REGSET_0_15 */
768 +
769 +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (u32)(0x0)
770 +
771 +
772 +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address
773 + * increment and number of banks */
774 +
775 +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (u32)(0x0080)
776 +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (u32)(0x0004)
777 +
778 +/* Register offset address definitions relative to register set
779 + * MAILBOX_FIFOSTATUS___REGSET_0_15 */
780 +
781 +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (u32)(0x0)
782 +
783 +
784 +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address
785 + * increment and number of banks */
786 +
787 +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (u32)(0x00c0)
788 +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (u32)(0x0004)
789 +
790 +/* Register offset address definitions relative to register set
791 + * MAILBOX_MSGSTATUS___REGSET_0_15 */
792 +
793 +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (u32)(0x0)
794 +
795 +
796 +/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address
797 + * increment and number of banks */
798 +
799 +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (u32)(0x0100)
800 +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (u32)(0x0008)
801 +
802 +/* Register offset address definitions relative to register set
803 + * MAILBOX_IRQSTATUS___REGSET_0_3 */
804 +
805 +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (u32)(0x0)
806 +
807 +
808 +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address
809 + * increment and number of banks */
810 +
811 +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (u32)(0x0104)
812 +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (u32)(0x0008)
813 +
814 +/* Register offset address definitions relative to register set
815 + * MAILBOX_IRQENABLE___REGSET_0_3 */
816 +
817 +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (u32)(0x0)
818 +
819 +
820 +/* Register offset address definitions */
821 +
822 +#define MLB_MAILBOX_SYSCONFIG_OFFSET (u32)(0x10)
823 +#define MLB_MAILBOX_SYSSTATUS_OFFSET (u32)(0x14)
824 +
825 +
826 +/* Bitfield mask and offset declarations */
827 +
828 +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (u32)(0x18)
829 +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (u32)(3)
830 +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (u32)(0x2)
831 +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (u32)(1)
832 +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (u32)(0x1)
833 +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (u32)(0)
834 +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (u32)(0x1)
835 +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (u32)(0)
836 +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (u32)(0x1)
837 +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (u32)(0)
838 +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (u32)(0x7f)
839 +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (u32)(0)
840 +
841 +#endif /* _MLB_ACC_INT_H */
842 diff --git a/drivers/dsp/bridge/hw/MLBRegAcM.h b/drivers/dsp/bridge/hw/MLBRegAcM.h
843 new file mode 100644
844 index 0000000..f9108c2
845 --- /dev/null
846 +++ b/drivers/dsp/bridge/hw/MLBRegAcM.h
847 @@ -0,0 +1,200 @@
848 +/*
849 + * linux/drivers/dsp/bridge/hw/omap3/mbox/MLBRegAcM.h
850 + *
851 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
852 + *
853 + * Copyright (C) 2007 Texas Instruments, Inc.
854 + *
855 + * This package is free software; you can redistribute it and/or modify
856 + * it under the terms of the GNU General Public License version 2 as
857 + * published by the Free Software Foundation.
858 + *
859 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
860 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
861 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
862 + */
863 +
864 +#ifndef _MLB_REG_ACM_H
865 +#define _MLB_REG_ACM_H
866 +
867 +#include <GlobalTypes.h>
868 +#include <EasiGlobal.h>
869 +#include "MLBAccInt.h"
870 +
871 +#if defined(USE_LEVEL_1_MACROS)
872 +
873 +#define MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress)\
874 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\
875 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+ \
876 + MLB_MAILBOX_SYSCONFIG_OFFSET))
877 +
878 +
879 +#define MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, value)\
880 +{\
881 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
882 + register u32 newValue = ((u32)(value));\
883 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\
884 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
885 +}
886 +
887 +
888 +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(baseAddress)\
889 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\
890 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
891 + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
892 + MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
893 + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
894 +
895 +
896 +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(baseAddress, value)\
897 +{\
898 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
899 + register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress)) +\
900 + offset);\
901 + register u32 newValue = ((u32)(value));\
902 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\
903 + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
904 + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
905 + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
906 + newValue |= data;\
907 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
908 +}
909 +
910 +
911 +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(baseAddress, value)\
912 +{\
913 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
914 + register u32 data =\
915 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
916 + register u32 newValue = ((u32)(value));\
917 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\
918 + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
919 + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
920 + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
921 + newValue |= data;\
922 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
923 +}
924 +
925 +
926 +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(baseAddress)\
927 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\
928 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
929 + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
930 + MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
931 + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
932 +
933 +
934 +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(baseAddress, value)\
935 +{\
936 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
937 + register u32 data =\
938 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
939 + register u32 newValue = ((u32)(value));\
940 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\
941 + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
942 + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
943 + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
944 + newValue |= data;\
945 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
946 +}
947 +
948 +
949 +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(baseAddress)\
950 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\
951 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
952 + (MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
953 + MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
954 + MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
955 +
956 +
957 +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress, bank)\
958 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\
959 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
960 + (MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
961 + MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\
962 + (bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
963 +
964 +
965 +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, bank, value)\
966 +{\
967 + const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
968 + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
969 + ((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
970 + register u32 newValue = ((u32)(value));\
971 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\
972 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
973 +}
974 +
975 +
976 +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(baseAddress, bank)\
977 + (_DEBUG_LEVEL_1_EASI(\
978 + EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\
979 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
980 + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
981 + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
982 + ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
983 +
984 +
985 +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress, bank)\
986 + (_DEBUG_LEVEL_1_EASI(\
987 + EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\
988 + (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
989 + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
990 + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
991 + ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
992 + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\
993 + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
994 +
995 +
996 +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress, bank)\
997 + (_DEBUG_LEVEL_1_EASI(\
998 + EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\
999 + (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
1000 + (MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
1001 + MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\
1002 + ((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
1003 + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\
1004 + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
1005 +
1006 +
1007 +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, bank)\
1008 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\
1009 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
1010 + (MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
1011 + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
1012 + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
1013 +
1014 +
1015 +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, bank, value)\
1016 +{\
1017 + const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
1018 + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
1019 + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
1020 + register u32 newValue = ((u32)(value));\
1021 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\
1022 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1023 +}
1024 +
1025 +
1026 +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress, bank)\
1027 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\
1028 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
1029 + (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
1030 + MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
1031 + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
1032 +
1033 +
1034 +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, bank, value)\
1035 +{\
1036 + const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
1037 + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
1038 + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
1039 + register u32 newValue = ((u32)(value));\
1040 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\
1041 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1042 +}
1043 +
1044 +
1045 +#endif /* USE_LEVEL_1_MACROS */
1046 +
1047 +#endif /* _MLB_REG_ACM_H */
1048 diff --git a/drivers/dsp/bridge/hw/MMUAccInt.h b/drivers/dsp/bridge/hw/MMUAccInt.h
1049 new file mode 100644
1050 index 0000000..6be9d75
1051 --- /dev/null
1052 +++ b/drivers/dsp/bridge/hw/MMUAccInt.h
1053 @@ -0,0 +1,79 @@
1054 +/*
1055 + * linux/drivers/dsp/bridge/hw/omap3/mmu/MMUAccInt.h
1056 + *
1057 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1058 + *
1059 + * Copyright (C) 2007 Texas Instruments, Inc.
1060 + *
1061 + * This package is free software; you can redistribute it and/or modify
1062 + * it under the terms of the GNU General Public License version 2 as
1063 + * published by the Free Software Foundation.
1064 + *
1065 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1066 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1067 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1068 + */
1069 +
1070 +#ifndef _MMU_ACC_INT_H
1071 +#define _MMU_ACC_INT_H
1072 +
1073 +/* Mappings of level 1 EASI function numbers to function names */
1074 +
1075 +#define EASIL1_MMUMMU_SYSCONFIGReadRegister32 (MMU_BASE_EASIL1 + 3)
1076 +#define EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32 (MMU_BASE_EASIL1 + 17)
1077 +#define EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32 (MMU_BASE_EASIL1 + 39)
1078 +#define EASIL1_MMUMMU_IRQSTATUSWriteRegister32 (MMU_BASE_EASIL1 + 51)
1079 +#define EASIL1_MMUMMU_IRQENABLEReadRegister32 (MMU_BASE_EASIL1 + 102)
1080 +#define EASIL1_MMUMMU_IRQENABLEWriteRegister32 (MMU_BASE_EASIL1 + 103)
1081 +#define EASIL1_MMUMMU_WALKING_STTWLRunningRead32 (MMU_BASE_EASIL1 + 156)
1082 +#define EASIL1_MMUMMU_CNTLTWLEnableRead32 (MMU_BASE_EASIL1 + 174)
1083 +#define EASIL1_MMUMMU_CNTLTWLEnableWrite32 (MMU_BASE_EASIL1 + 180)
1084 +#define EASIL1_MMUMMU_CNTLMMUEnableWrite32 (MMU_BASE_EASIL1 + 190)
1085 +#define EASIL1_MMUMMU_FAULT_ADReadRegister32 (MMU_BASE_EASIL1 + 194)
1086 +#define EASIL1_MMUMMU_TTBWriteRegister32 (MMU_BASE_EASIL1 + 198)
1087 +#define EASIL1_MMUMMU_LOCKReadRegister32 (MMU_BASE_EASIL1 + 203)
1088 +#define EASIL1_MMUMMU_LOCKWriteRegister32 (MMU_BASE_EASIL1 + 204)
1089 +#define EASIL1_MMUMMU_LOCKBaseValueRead32 (MMU_BASE_EASIL1 + 205)
1090 +#define EASIL1_MMUMMU_LOCKCurrentVictimRead32 (MMU_BASE_EASIL1 + 209)
1091 +#define EASIL1_MMUMMU_LOCKCurrentVictimWrite32 (MMU_BASE_EASIL1 + 211)
1092 +#define EASIL1_MMUMMU_LOCKCurrentVictimSet32 (MMU_BASE_EASIL1 + 212)
1093 +#define EASIL1_MMUMMU_LD_TLBReadRegister32 (MMU_BASE_EASIL1 + 213)
1094 +#define EASIL1_MMUMMU_LD_TLBWriteRegister32 (MMU_BASE_EASIL1 + 214)
1095 +#define EASIL1_MMUMMU_CAMWriteRegister32 (MMU_BASE_EASIL1 + 226)
1096 +#define EASIL1_MMUMMU_RAMWriteRegister32 (MMU_BASE_EASIL1 + 268)
1097 +#define EASIL1_MMUMMU_GFLUSHGlobalFlushWrite32 (MMU_BASE_EASIL1 + 317)
1098 +#define EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32 (MMU_BASE_EASIL1 + 322)
1099 +
1100 +/* Register offset address definitions */
1101 +#define MMU_MMU_SYSCONFIG_OFFSET 0x10
1102 +#define MMU_MMU_IRQSTATUS_OFFSET 0x18
1103 +#define MMU_MMU_IRQENABLE_OFFSET 0x1c
1104 +#define MMU_MMU_WALKING_ST_OFFSET 0x40
1105 +#define MMU_MMU_CNTL_OFFSET 0x44
1106 +#define MMU_MMU_FAULT_AD_OFFSET 0x48
1107 +#define MMU_MMU_TTB_OFFSET 0x4c
1108 +#define MMU_MMU_LOCK_OFFSET 0x50
1109 +#define MMU_MMU_LD_TLB_OFFSET 0x54
1110 +#define MMU_MMU_CAM_OFFSET 0x58
1111 +#define MMU_MMU_RAM_OFFSET 0x5c
1112 +#define MMU_MMU_GFLUSH_OFFSET 0x60
1113 +#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
1114 +/* Bitfield mask and offset declarations */
1115 +#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18
1116 +#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3
1117 +#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1
1118 +#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0
1119 +#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1
1120 +#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0
1121 +#define MMU_MMU_CNTL_TWLEnable_MASK 0x4
1122 +#define MMU_MMU_CNTL_TWLEnable_OFFSET 2
1123 +#define MMU_MMU_CNTL_MMUEnable_MASK 0x2
1124 +#define MMU_MMU_CNTL_MMUEnable_OFFSET 1
1125 +#define MMU_MMU_LOCK_BaseValue_MASK 0xfc00
1126 +#define MMU_MMU_LOCK_BaseValue_OFFSET 10
1127 +#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0
1128 +#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4
1129 +#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1
1130 +#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0
1131 +
1132 +#endif /* _MMU_ACC_INT_H */
1133 diff --git a/drivers/dsp/bridge/hw/MMURegAcM.h b/drivers/dsp/bridge/hw/MMURegAcM.h
1134 new file mode 100644
1135 index 0000000..fb3095c
1136 --- /dev/null
1137 +++ b/drivers/dsp/bridge/hw/MMURegAcM.h
1138 @@ -0,0 +1,267 @@
1139 +/*
1140 + * linux/drivers/dsp/bridge/hw/omap3/mmu/MMURegAcM.h
1141 + *
1142 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1143 + *
1144 + * Copyright (C) 2007 Texas Instruments, Inc.
1145 + *
1146 + * This package is free software; you can redistribute it and/or modify
1147 + * it under the terms of the GNU General Public License version 2 as
1148 + * published by the Free Software Foundation.
1149 + *
1150 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1151 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1152 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1153 + */
1154 +
1155 +
1156 +#ifndef _MMU_REG_ACM_H
1157 +#define _MMU_REG_ACM_H
1158 +
1159 +#include <GlobalTypes.h>
1160 +
1161 +#include <EasiGlobal.h>
1162 +
1163 +#include "MMUAccInt.h"
1164 +
1165 +#if defined(USE_LEVEL_1_MACROS)
1166 +
1167 +
1168 +#define MMUMMU_SYSCONFIGReadRegister32(baseAddress)\
1169 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGReadRegister32),\
1170 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET))
1171 +
1172 +
1173 +#define MMUMMU_SYSCONFIGIdleModeWrite32(baseAddress, value)\
1174 +{\
1175 + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
1176 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1177 + register u32 newValue = (value);\
1178 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32);\
1179 + data &= ~(MMU_MMU_SYSCONFIG_IdleMode_MASK);\
1180 + newValue <<= MMU_MMU_SYSCONFIG_IdleMode_OFFSET;\
1181 + newValue &= MMU_MMU_SYSCONFIG_IdleMode_MASK;\
1182 + newValue |= data;\
1183 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1184 +}
1185 +
1186 +
1187 +#define MMUMMU_SYSCONFIGAutoIdleWrite32(baseAddress, value)\
1188 +{\
1189 + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
1190 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1191 + register u32 newValue = (value);\
1192 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32);\
1193 + data &= ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK);\
1194 + newValue <<= MMU_MMU_SYSCONFIG_AutoIdle_OFFSET;\
1195 + newValue &= MMU_MMU_SYSCONFIG_AutoIdle_MASK;\
1196 + newValue |= data;\
1197 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1198 +}
1199 +
1200 +
1201 +#define MMUMMU_IRQSTATUSReadRegister32(baseAddress)\
1202 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\
1203 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET))
1204 +
1205 +
1206 +#define MMUMMU_IRQSTATUSWriteRegister32(baseAddress, value)\
1207 +{\
1208 + const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
1209 + register u32 newValue = (value);\
1210 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSWriteRegister32);\
1211 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1212 +}
1213 +
1214 +
1215 +#define MMUMMU_IRQENABLEReadRegister32(baseAddress)\
1216 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEReadRegister32),\
1217 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQENABLE_OFFSET))
1218 +
1219 +
1220 +#define MMUMMU_IRQENABLEWriteRegister32(baseAddress, value)\
1221 +{\
1222 + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
1223 + register u32 newValue = (value);\
1224 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEWriteRegister32);\
1225 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1226 +}
1227 +
1228 +
1229 +#define MMUMMU_WALKING_STTWLRunningRead32(baseAddress)\
1230 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_WALKING_STTWLRunningRead32),\
1231 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\
1232 + & MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\
1233 + MMU_MMU_WALKING_ST_TWLRunning_OFFSET))
1234 +
1235 +
1236 +#define MMUMMU_CNTLTWLEnableRead32(baseAddress)\
1237 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableRead32),\
1238 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\
1239 + MMU_MMU_CNTL_TWLEnable_MASK) >>\
1240 + MMU_MMU_CNTL_TWLEnable_OFFSET))
1241 +
1242 +
1243 +#define MMUMMU_CNTLTWLEnableWrite32(baseAddress, value)\
1244 +{\
1245 + const u32 offset = MMU_MMU_CNTL_OFFSET;\
1246 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1247 + register u32 newValue = (value);\
1248 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableWrite32);\
1249 + data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\
1250 + newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\
1251 + newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\
1252 + newValue |= data;\
1253 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1254 +}
1255 +
1256 +
1257 +#define MMUMMU_CNTLMMUEnableWrite32(baseAddress, value)\
1258 +{\
1259 + const u32 offset = MMU_MMU_CNTL_OFFSET;\
1260 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1261 + register u32 newValue = (value);\
1262 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLMMUEnableWrite32);\
1263 + data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\
1264 + newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\
1265 + newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\
1266 + newValue |= data;\
1267 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1268 +}
1269 +
1270 +
1271 +#define MMUMMU_FAULT_ADReadRegister32(baseAddress)\
1272 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FAULT_ADReadRegister32),\
1273 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_FAULT_AD_OFFSET))
1274 +
1275 +
1276 +#define MMUMMU_TTBWriteRegister32(baseAddress, value)\
1277 +{\
1278 + const u32 offset = MMU_MMU_TTB_OFFSET;\
1279 + register u32 newValue = (value);\
1280 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_TTBWriteRegister32);\
1281 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1282 +}
1283 +
1284 +
1285 +#define MMUMMU_LOCKReadRegister32(baseAddress)\
1286 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKReadRegister32),\
1287 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LOCK_OFFSET))
1288 +
1289 +
1290 +#define MMUMMU_LOCKWriteRegister32(baseAddress, value)\
1291 +{\
1292 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1293 + register u32 newValue = (value);\
1294 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKWriteRegister32);\
1295 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1296 +}
1297 +
1298 +
1299 +#define MMUMMU_LOCKBaseValueRead32(baseAddress)\
1300 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueRead32),\
1301 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
1302 + MMU_MMU_LOCK_BaseValue_MASK) >>\
1303 + MMU_MMU_LOCK_BaseValue_OFFSET))
1304 +
1305 +
1306 +#define MMUMMU_LOCKBaseValueWrite32(baseAddress, value)\
1307 +{\
1308 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1309 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1310 + register u32 newValue = (value);\
1311 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\
1312 + data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\
1313 + newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\
1314 + newValue &= MMU_MMU_LOCK_BaseValue_MASK;\
1315 + newValue |= data;\
1316 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1317 +}
1318 +
1319 +
1320 +#define MMUMMU_LOCKCurrentVictimRead32(baseAddress)\
1321 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimRead32),\
1322 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
1323 + MMU_MMU_LOCK_CurrentVictim_MASK) >>\
1324 + MMU_MMU_LOCK_CurrentVictim_OFFSET))
1325 +
1326 +
1327 +#define MMUMMU_LOCKCurrentVictimWrite32(baseAddress, value)\
1328 +{\
1329 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1330 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1331 + register u32 newValue = (value);\
1332 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimWrite32);\
1333 + data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\
1334 + newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\
1335 + newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\
1336 + newValue |= data;\
1337 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1338 +}
1339 +
1340 +
1341 +#define MMUMMU_LOCKCurrentVictimSet32(var, value)\
1342 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimSet32),\
1343 + (((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\
1344 + (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\
1345 + MMU_MMU_LOCK_CurrentVictim_MASK)))
1346 +
1347 +
1348 +#define MMUMMU_LD_TLBReadRegister32(baseAddress)\
1349 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBReadRegister32),\
1350 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LD_TLB_OFFSET))
1351 +
1352 +
1353 +#define MMUMMU_LD_TLBWriteRegister32(baseAddress, value)\
1354 +{\
1355 + const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
1356 + register u32 newValue = (value);\
1357 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBWriteRegister32);\
1358 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1359 +}
1360 +
1361 +
1362 +#define MMUMMU_CAMWriteRegister32(baseAddress, value)\
1363 +{\
1364 + const u32 offset = MMU_MMU_CAM_OFFSET;\
1365 + register u32 newValue = (value);\
1366 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CAMWriteRegister32);\
1367 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1368 +}
1369 +
1370 +
1371 +#define MMUMMU_RAMWriteRegister32(baseAddress, value)\
1372 +{\
1373 + const u32 offset = MMU_MMU_RAM_OFFSET;\
1374 + register u32 newValue = (value);\
1375 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_RAMWriteRegister32);\
1376 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1377 +}
1378 +
1379 +
1380 +#define MMUMMU_GFLUSHGlobalFlushWrite32(baseAddress, value)\
1381 +{\
1382 + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
1383 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1384 + register u32 newValue = (value);\
1385 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_GFLUSHGlobalFlushWrite32);\
1386 + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
1387 + newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
1388 + newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\
1389 + newValue |= data;\
1390 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1391 +}
1392 +
1393 +
1394 +#define MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, value)\
1395 +{\
1396 + const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
1397 + register u32 newValue = (value);\
1398 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32);\
1399 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1400 +}
1401 +
1402 +
1403 +#endif /* USE_LEVEL_1_MACROS */
1404 +
1405 +#endif /* _MMU_REG_ACM_H */
1406 diff --git a/drivers/dsp/bridge/hw/PRCMAccInt.h b/drivers/dsp/bridge/hw/PRCMAccInt.h
1407 new file mode 100644
1408 index 0000000..d315dff
1409 --- /dev/null
1410 +++ b/drivers/dsp/bridge/hw/PRCMAccInt.h
1411 @@ -0,0 +1,300 @@
1412 +/*
1413 + * linux/drivers/dsp/bridge/hw/omap3/prcm/PRCMAccInt.h
1414 + *
1415 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1416 + *
1417 + * Copyright (C) 2007 Texas Instruments, Inc.
1418 + *
1419 + * This package is free software; you can redistribute it and/or modify
1420 + * it under the terms of the GNU General Public License version 2 as
1421 + * published by the Free Software Foundation.
1422 + *
1423 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1424 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1425 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1426 + */
1427 +
1428 +#ifndef _PRCM_ACC_INT_H
1429 +#define _PRCM_ACC_INT_H
1430 +
1431 +/* Mappings of level 1 EASI function numbers to function names */
1432 +
1433 +#define EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32 \
1434 + (PRCM_BASE_EASIL1 + 349)
1435 +#define EASIL1_PRCMCM_FCLKEN1_COREReadRegister32 (PRCM_BASE_EASIL1 + 743)
1436 +#define EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32 (PRCM_BASE_EASIL1 + 951)
1437 +#define EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32 (PRCM_BASE_EASIL1 + 961)
1438 +#define EASIL1_PRCMCM_ICLKEN1_COREReadRegister32 \
1439 + (PRCM_BASE_EASIL1 + 1087)
1440 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32 \
1441 + (PRCM_BASE_EASIL1 + 1105)
1442 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32 \
1443 + (PRCM_BASE_EASIL1 + 1305)
1444 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32 \
1445 + (PRCM_BASE_EASIL1 + 1315)
1446 +#define EASIL1_PRCMCM_CLKSEL1_CORECLKSEL_L3ReadIssel132 \
1447 + (PRCM_BASE_EASIL1 + 2261)
1448 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32 \
1449 + (PRCM_BASE_EASIL1 + 2364)
1450 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32 \
1451 + (PRCM_BASE_EASIL1 + 2365)
1452 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32 \
1453 + (PRCM_BASE_EASIL1 + 2366)
1454 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32 \
1455 + (PRCM_BASE_EASIL1 + 2380)
1456 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32 \
1457 + (PRCM_BASE_EASIL1 + 2381)
1458 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32 \
1459 + (PRCM_BASE_EASIL1 + 2382)
1460 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32 \
1461 + (PRCM_BASE_EASIL1 + 2397)
1462 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32 \
1463 + (PRCM_BASE_EASIL1 + 2398)
1464 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32 \
1465 + (PRCM_BASE_EASIL1 + 2413)
1466 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32 \
1467 + (PRCM_BASE_EASIL1 + 2414)
1468 +#define EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32 \
1469 + (PRCM_BASE_EASIL1 + 3747)
1470 +#define EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32 (PRCM_BASE_EASIL1 + 3834)
1471 +#define EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32 \
1472 + (PRCM_BASE_EASIL1 + 3846)
1473 +#define EASIL1_PRCMCM_IDLEST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 3850)
1474 +#define EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32 (PRCM_BASE_EASIL1 + 3857)
1475 +#define EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32 (PRCM_BASE_EASIL1 + 3863)
1476 +#define EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32 \
1477 + (PRCM_BASE_EASIL1 + 3877)
1478 +#define EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32 (PRCM_BASE_EASIL1 + 3927)
1479 +#define EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32 \
1480 + (PRCM_BASE_EASIL1 + 3941)
1481 +#define EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32 \
1482 + (PRCM_BASE_EASIL1 + 3965)
1483 +#define EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32 \
1484 + (PRCM_BASE_EASIL1 + 3987)
1485 +#define EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32 \
1486 + (PRCM_BASE_EASIL1 + 3993)
1487 +#define EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32 (PRCM_BASE_EASIL1 + 3997)
1488 +#define EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32 \
1489 + (PRCM_BASE_EASIL1 + 4025)
1490 +#define EASIL1_PRCMRM_RSTST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 4029)
1491 +#define EASIL1_PRCMRM_RSTST_DSPWriteRegister32 (PRCM_BASE_EASIL1 + 4030)
1492 +#define EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32 \
1493 + (PRCM_BASE_EASIL1 + 4165)
1494 +#define EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32 \
1495 + (PRCM_BASE_EASIL1 + 4193)
1496 +#define EASIL1_PRCMPM_PWSTST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 4197)
1497 +#define EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32 \
1498 + (PRCM_BASE_EASIL1 + 4198)
1499 +#define EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32 \
1500 + (PRCM_BASE_EASIL1 + 4235)
1501 +#define EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32 \
1502 + (PRCM_BASE_EASIL1 + 4368)
1503 +#define EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32 \
1504 + (PRCM_BASE_EASIL1 + 4370)
1505 +#define EASIL1_CM_CLKSEL_PER_GPT5Write32k32 (PRCM_BASE_EASIL1 + 4372)
1506 +#define EASIL1_CM_CLKSEL_PER_GPT6Write32k32 (PRCM_BASE_EASIL1 + 4373)
1507 +#define EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32 \
1508 + (PRCM_BASE_EASIL1 + 4374)
1509 +#define EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32 \
1510 + (PRCM_BASE_EASIL1 + 4375)
1511 +#define EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32 \
1512 + (PRCM_BASE_EASIL1 + 4376)
1513 +#define EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32 \
1514 + (PRCM_BASE_EASIL1 + 4377)
1515 +#define EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32 \
1516 + (PRCM_BASE_EASIL1 + 4378)
1517 +#define EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32 (PRCM_BASE_EASIL1 + 4379)
1518 +
1519 +/* Register offset address definitions */
1520 +
1521 +#define PRCM_PRCM_CLKCFG_CTRL_OFFSET (u32)(0x80)
1522 +#define PRCM_CM_FCLKEN1_CORE_OFFSET (u32)(0x200)
1523 +#define PRCM_CM_ICLKEN1_CORE_OFFSET (u32)(0x210)
1524 +#define PRCM_CM_CLKSEL2_CORE_OFFSET (u32)(0x244)
1525 +#define PRCM_CM_CLKSEL1_PLL_OFFSET (u32)(0x540)
1526 +#define PRCM_CM_ICLKEN_DSP_OFFSET (u32)(0x810)
1527 +#define PRCM_CM_IDLEST_DSP_OFFSET (u32)(0x820)
1528 +#define PRCM_CM_AUTOIDLE_DSP_OFFSET (u32)(0x830)
1529 +#define PRCM_CM_CLKSEL_DSP_OFFSET (u32)(0x840)
1530 +#define PRCM_CM_CLKSTCTRL_DSP_OFFSET (u32)(0x848)
1531 +#define PRCM_RM_RSTCTRL_DSP_OFFSET (u32)(0x850)
1532 +#define PRCM_RM_RSTST_DSP_OFFSET (u32)(0x858)
1533 +#define PRCM_PM_PWSTCTRL_DSP_OFFSET (u32)(0x8e0)
1534 +#define PRCM_PM_PWSTST_DSP_OFFSET (u32)(0x8e4)
1535 +#define PRCM_PM_PWSTST_IVA2_OFFSET (u32)(0xE4)
1536 +#define PRCM_PM_PWSTCTRL_IVA2_OFFSET (u32)(0xE0)
1537 +#define PRCM_CM_CLKSTCTRL_IVA2_OFFSET (u32)(0x48)
1538 +#define CM_CLKSEL_PER_OFFSET (u32)(0x40)
1539 +
1540 +/* Bitfield mask and offset declarations */
1541 +
1542 +#define PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK (u32)(0x1)
1543 +#define PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET (u32)(0)
1544 +
1545 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK (u32)(0x400)
1546 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET (u32)(10)
1547 +
1548 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK (u32)(0x200)
1549 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET (u32)(9)
1550 +
1551 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK (u32)(0x400)
1552 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET (u32)(10)
1553 +
1554 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK (u32)(0x200)
1555 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET (u32)(9)
1556 +
1557 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK (u32)(0xc000)
1558 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET (u32)(14)
1559 +
1560 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK (u32)(0x3000)
1561 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET (u32)(12)
1562 +
1563 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK (u32)(0xc00)
1564 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET (u32)(10)
1565 +
1566 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK (u32)(0x300)
1567 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET (u32)(8)
1568 +
1569 +#define PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK (u32)(0x3800000)
1570 +#define PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET (u32)(23)
1571 +
1572 +#define PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK (u32)(0x2)
1573 +#define PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET (u32)(1)
1574 +
1575 +#define PRCM_CM_IDLEST_DSP_ST_IPI_MASK (u32)(0x2)
1576 +#define PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET (u32)(1)
1577 +
1578 +#define PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK (u32)(0x2)
1579 +#define PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET (u32)(1)
1580 +
1581 +#define PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK (u32)(0x80)
1582 +#define PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET (u32)(7)
1583 +
1584 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK (u32)(0x60)
1585 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET (u32)(5)
1586 +
1587 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK (u32)(0x1f)
1588 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET (u32)(0)
1589 +
1590 +#define PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK (u32)(0x1)
1591 +#define PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET (u32)(0)
1592 +
1593 +#define PRCM_PM_PWSTCTRL_DSP_ForceState_MASK (u32)(0x40000)
1594 +#define PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET (u32)(18)
1595 +
1596 +#define PRCM_PM_PWSTCTRL_DSP_PowerState_MASK (u32)(0x3)
1597 +#define PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET (u32)(0)
1598 +
1599 +#define PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK (u32)(0x3)
1600 +#define PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET (u32)(0)
1601 +
1602 +#define PRCM_PM_PWSTST_DSP_InTransition_MASK (u32)(0x100000)
1603 +#define PRCM_PM_PWSTST_DSP_InTransition_OFFSET (u32)(20)
1604 +
1605 +#define PRCM_PM_PWSTST_IVA2_InTransition_MASK (u32)(0x100000)
1606 +#define PRCM_PM_PWSTST_IVA2_InTransition_OFFSET (u32)(20)
1607 +
1608 +#define PRCM_PM_PWSTST_DSP_PowerStateSt_MASK (u32)(0x3)
1609 +#define PRCM_PM_PWSTST_DSP_PowerStateSt_OFFSET (u32)(0)
1610 +
1611 +#define PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK (u32)(0x3)
1612 +#define PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET (u32)(0)
1613 +
1614 +#define CM_FCLKEN_PER_OFFSET (u32)(0x0)
1615 +#define CM_FCLKEN_PER_GPT5_OFFSET (u32)(6)
1616 +#define CM_FCLKEN_PER_GPT5_MASK (u32)(0x40)
1617 +
1618 +#define CM_FCLKEN_PER_GPT6_OFFSET (u32)(7)
1619 +#define CM_FCLKEN_PER_GPT6_MASK (u32)(0x80)
1620 +
1621 +#define CM_ICLKEN_PER_OFFSET (u32)(0x10)
1622 +#define CM_ICLKEN_PER_GPT5_OFFSET (u32)(6)
1623 +#define CM_ICLKEN_PER_GPT5_MASK (u32)(0x40)
1624 +
1625 +#define CM_ICLKEN_PER_GPT6_OFFSET (u32)(7)
1626 +#define CM_ICLKEN_PER_GPT6_MASK (u32)(0x80)
1627 +
1628 +#define CM_CLKSEL_PER_GPT5_OFFSET (u32)(3)
1629 +#define CM_CLKSEL_PER_GPT5_MASK (u32)(0x8)
1630 +
1631 +#define CM_CLKSEL_PER_GPT6_OFFSET (u32)(4)
1632 +#define CM_CLKSEL_PER_GPT6_MASK (u32)(0x10)
1633 +
1634 +
1635 +#define CM_FCLKEN_IVA2_OFFSET (u32)(0x0)
1636 +#define CM_FCLKEN_IVA2_EN_MASK (u32)(0x1)
1637 +#define CM_FCLKEN_IVA2_EN_OFFSET (u32)(0x0)
1638 +
1639 +#define CM_IDLEST_IVA2_OFFSET (u32)(0x20)
1640 +#define CM_IDLEST_IVA2_ST_IVA2_MASK (u32) (0x01)
1641 +#define CM_IDLEST_IVA2_ST_IVA2_OFFSET (u32) (0x00)
1642 +
1643 +#define CM_FCLKEN1_CORE_OFFSET (u32)(0xA00)
1644 +
1645 +#define CM_ICLKEN1_CORE_OFFSET (u32)(0xA10)
1646 +#define CM_ICLKEN1_CORE_EN_MAILBOXES_MASK (u32)(0x00000080) /* bit 7 */
1647 +#define CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET (u32)(7)
1648 +
1649 +#define CM_CLKSTCTRL_IVA2_OFFSET (u32)(0x0)
1650 +#define CM_CLKSTCTRL_IVA2_MASK (u32)(0x3)
1651 +
1652 +
1653 +#define PRM_RSTCTRL_IVA2_OFFSET (u32)(0x50)
1654 +#define PRM_RSTCTRL_IVA2_RST1_MASK (u32)(0x1)
1655 +#define PRM_RSTCTRL_IVA2_RST1_OFFSET (u32)(0x0)
1656 +#define PRM_RSTCTRL_IVA2_RST2_MASK (u32)(0x2)
1657 +#define PRM_RSTCTRL_IVA2_RST2_OFFSET (u32)(0x1)
1658 +#define PRM_RSTCTRL_IVA2_RST3_MASK (u32)(0x4)
1659 +#define PRM_RSTCTRL_IVA2_RST3_OFFSET (u32)(0x2)
1660 +
1661 +
1662 +/* The following represent the enumerated values for each bitfield */
1663 +
1664 +enum PRCMPRCM_CLKCFG_CTRLValid_configE {
1665 + PRCMPRCM_CLKCFG_CTRLValid_configUpdated = 0x0000,
1666 + PRCMPRCM_CLKCFG_CTRLValid_configClk_valid = 0x0001
1667 +} ;
1668 +
1669 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT8E {
1670 + PRCMCM_CLKSEL2_CORECLKSEL_GPT832k = 0x0000,
1671 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys = 0x0001,
1672 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext = 0x0002,
1673 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Reserved = 0x0003
1674 +} ;
1675 +
1676 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT7E {
1677 + PRCMCM_CLKSEL2_CORECLKSEL_GPT732k = 0x0000,
1678 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys = 0x0001,
1679 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext = 0x0002,
1680 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Reserved = 0x0003
1681 +} ;
1682 +
1683 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT6E {
1684 + PRCMCM_CLKSEL2_CORECLKSEL_GPT632k = 0x0000,
1685 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys = 0x0001,
1686 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext = 0x0002,
1687 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Reserved = 0x0003
1688 +} ;
1689 +
1690 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT5E {
1691 + PRCMCM_CLKSEL2_CORECLKSEL_GPT532k = 0x0000,
1692 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys = 0x0001,
1693 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext = 0x0002,
1694 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Reserved = 0x0003
1695 +} ;
1696 +
1697 +enum PRCMPM_PWSTCTRL_DSPPowerStateE {
1698 + PRCMPM_PWSTCTRL_DSPPowerStateON = 0x0000,
1699 + PRCMPM_PWSTCTRL_DSPPowerStateRET = 0x0001,
1700 + PRCMPM_PWSTCTRL_DSPPowerStateReserved = 0x0002,
1701 + PRCMPM_PWSTCTRL_DSPPowerStateOFF = 0x0003
1702 +} ;
1703 +
1704 +enum PRCMPM_PWSTCTRL_IVA2PowerStateE {
1705 + PRCMPM_PWSTCTRL_IVA2PowerStateON = 0x0003,
1706 + PRCMPM_PWSTCTRL_IVA2PowerStateRET = 0x0001,
1707 + PRCMPM_PWSTCTRL_IVA2PowerStateReserved = 0x0002,
1708 + PRCMPM_PWSTCTRL_IVA2PowerStateOFF = 0x0000
1709 +} ;
1710 +
1711 +#endif /* _PRCM_ACC_INT_H */
1712 diff --git a/drivers/dsp/bridge/hw/PRCMRegAcM.h b/drivers/dsp/bridge/hw/PRCMRegAcM.h
1713 new file mode 100644
1714 index 0000000..99c2f07
1715 --- /dev/null
1716 +++ b/drivers/dsp/bridge/hw/PRCMRegAcM.h
1717 @@ -0,0 +1,669 @@
1718 +/*
1719 + * linux/drivers/dsp/bridge/hw/omap3/prcm/PRCMRegAcM.h
1720 + *
1721 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1722 + *
1723 + * Copyright (C) 2007 Texas Instruments, Inc.
1724 + *
1725 + * This package is free software; you can redistribute it and/or modify
1726 + * it under the terms of the GNU General Public License version 2 as
1727 + * published by the Free Software Foundation.
1728 + *
1729 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1730 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1731 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1732 + */
1733 +
1734 +#ifndef _PRCM_REG_ACM_H
1735 +#define _PRCM_REG_ACM_H
1736 +
1737 +#include <GlobalTypes.h>
1738 +
1739 +#include <EasiGlobal.h>
1740 +
1741 +#include "PRCMAccInt.h"
1742 +
1743 +#if defined(USE_LEVEL_1_MACROS)
1744 +
1745 +#define PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32(baseAddress)\
1746 +{\
1747 + const u32 offset = PRCM_PRCM_CLKCFG_CTRL_OFFSET;\
1748 + const u32 newValue = \
1749 + (u32)PRCMPRCM_CLKCFG_CTRLValid_configClk_valid <<\
1750 + PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET;\
1751 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1752 + _DEBUG_LEVEL_1_EASI(\
1753 + EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32);\
1754 + data &= ~(PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK);\
1755 + data |= newValue;\
1756 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1757 +}
1758 +
1759 +
1760 +#define CM_FCLKEN_PERReadRegister32(baseAddress)\
1761 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1762 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN_PER_OFFSET))
1763 +
1764 +
1765 +#define CM_ICLKEN_PERReadRegister32(baseAddress)\
1766 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1767 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET))
1768 +
1769 +
1770 +#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress,value)\
1771 +{\
1772 + const u32 offset = CM_FCLKEN_PER_OFFSET;\
1773 + register u32 data = \
1774 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1775 + register u32 newValue = ((u32)(value));\
1776 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
1777 + data &= ~(CM_FCLKEN_PER_GPT5_MASK);\
1778 + newValue <<= CM_FCLKEN_PER_GPT5_OFFSET;\
1779 + newValue &= CM_FCLKEN_PER_GPT5_MASK;\
1780 + newValue |= data;\
1781 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1782 +}
1783 +
1784 +
1785 +#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress,value)\
1786 +{\
1787 + const u32 offset = CM_FCLKEN_PER_OFFSET;\
1788 + register u32 data =\
1789 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1790 + register u32 newValue = ((u32)(value));\
1791 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
1792 + data &= ~(CM_FCLKEN_PER_GPT6_MASK);\
1793 + newValue <<= CM_FCLKEN_PER_GPT6_OFFSET;\
1794 + newValue &= CM_FCLKEN_PER_GPT6_MASK;\
1795 + newValue |= data;\
1796 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1797 +}
1798 +
1799 +
1800 +#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress,value)\
1801 +{\
1802 + const u32 offset = CM_ICLKEN_PER_OFFSET;\
1803 + register u32 data = \
1804 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1805 + register u32 newValue = ((u32)(value));\
1806 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
1807 + data &= ~(CM_ICLKEN_PER_GPT5_MASK);\
1808 + newValue <<= CM_ICLKEN_PER_GPT5_OFFSET;\
1809 + newValue &= CM_ICLKEN_PER_GPT5_MASK;\
1810 + newValue |= data;\
1811 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1812 +}
1813 +
1814 +
1815 +#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress,value)\
1816 +{\
1817 + const u32 offset = CM_ICLKEN_PER_OFFSET;\
1818 + register u32 data = \
1819 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1820 + register u32 newValue = ((u32)(value));\
1821 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
1822 + data &= ~(CM_ICLKEN_PER_GPT6_MASK);\
1823 + newValue <<= CM_ICLKEN_PER_GPT6_OFFSET;\
1824 + newValue &= CM_ICLKEN_PER_GPT6_MASK;\
1825 + newValue |= data;\
1826 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1827 +}
1828 +
1829 +
1830 +#define CM_FCLKEN1_COREReadRegister32(baseAddress)\
1831 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1832 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET))
1833 +
1834 +
1835 +#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress,value)\
1836 +{\
1837 + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
1838 + register u32 data = \
1839 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1840 + register u32 newValue = ((u32)(value));\
1841 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32);\
1842 + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK);\
1843 + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET;\
1844 + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK;\
1845 + newValue |= data;\
1846 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1847 +}
1848 +
1849 +
1850 +#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress,value)\
1851 +{\
1852 + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
1853 + register u32 data = \
1854 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1855 + register u32 newValue = ((u32)(value));\
1856 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32);\
1857 + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK);\
1858 + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET;\
1859 + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK;\
1860 + newValue |= data;\
1861 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1862 +}
1863 +
1864 +
1865 +#define CM_ICLKEN1_COREReadRegister32(baseAddress)\
1866 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREReadRegister32),\
1867 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN1_CORE_OFFSET))
1868 +
1869 +
1870 +#define CM_ICLKEN1_COREEN_MAILBOXESWrite32(baseAddress, value)\
1871 +{\
1872 + const u32 offset = CM_ICLKEN1_CORE_OFFSET;\
1873 + register u32 data = \
1874 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1875 + register u32 newValue = ((u32)(value));\
1876 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32);\
1877 + data &= ~(CM_ICLKEN1_CORE_EN_MAILBOXES_MASK);\
1878 + newValue <<= CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET;\
1879 + newValue &= CM_ICLKEN1_CORE_EN_MAILBOXES_MASK;\
1880 + newValue |= data;\
1881 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1882 +}
1883 +
1884 +
1885 +#define PRCMCM_ICLKEN1_COREEN_GPT8Write32(baseAddress, value)\
1886 +{\
1887 + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
1888 + register u32 data = \
1889 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1890 + register u32 newValue = ((u32)(value));\
1891 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32);\
1892 + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK);\
1893 + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET;\
1894 + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK;\
1895 + newValue |= data;\
1896 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1897 +}
1898 +
1899 +
1900 +#define PRCMCM_ICLKEN1_COREEN_GPT7Write32(baseAddress, value)\
1901 +{\
1902 + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
1903 + register u32 data =\
1904 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1905 + register u32 newValue = ((u32)(value));\
1906 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32);\
1907 + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK);\
1908 + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET;\
1909 + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK;\
1910 + newValue |= data;\
1911 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1912 +}
1913 +
1914 +
1915 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32(baseAddress)\
1916 +{\
1917 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1918 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT832k <<\
1919 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1920 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1921 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32);\
1922 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1923 + data |= newValue;\
1924 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1925 +}
1926 +
1927 +
1928 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32(baseAddress)\
1929 +{\
1930 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1931 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys <<\
1932 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1933 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1934 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32);\
1935 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1936 + data |= newValue;\
1937 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1938 +}
1939 +
1940 +
1941 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32(baseAddress)\
1942 +{\
1943 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1944 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext <<\
1945 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1946 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1947 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32);\
1948 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1949 + data |= newValue;\
1950 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1951 +}
1952 +
1953 +
1954 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32(baseAddress)\
1955 +{\
1956 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1957 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT732k <<\
1958 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1959 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1960 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32);\
1961 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1962 + data |= newValue;\
1963 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1964 +}
1965 +
1966 +
1967 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32(baseAddress)\
1968 +{\
1969 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1970 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys <<\
1971 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1972 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1973 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32);\
1974 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1975 + data |= newValue;\
1976 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1977 +}
1978 +
1979 +
1980 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32(baseAddress)\
1981 +{\
1982 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1983 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext <<\
1984 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1985 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1986 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32);\
1987 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1988 + data |= newValue;\
1989 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1990 +}
1991 +
1992 +
1993 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32(baseAddress)\
1994 +{\
1995 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1996 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys <<\
1997 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
1998 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1999 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32);\
2000 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
2001 + data |= newValue;\
2002 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2003 +}
2004 +
2005 +
2006 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32(baseAddress)\
2007 +{\
2008 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
2009 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext <<\
2010 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
2011 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2012 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32);\
2013 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
2014 + data |= newValue;\
2015 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2016 +}
2017 +
2018 +
2019 +#define CM_CLKSEL_PER_GPT5Write32k32(baseAddress)\
2020 +{\
2021 + const u32 offset = CM_CLKSEL_PER_OFFSET;\
2022 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
2023 + CM_CLKSEL_PER_GPT5_OFFSET;\
2024 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2025 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT5Write32k32);\
2026 + data &= ~(CM_CLKSEL_PER_GPT5_MASK);\
2027 + data |= newValue;\
2028 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2029 +}
2030 +
2031 +
2032 +#define CM_CLKSEL_PER_GPT6Write32k32(baseAddress)\
2033 +{\
2034 + const u32 offset = CM_CLKSEL_PER_OFFSET;\
2035 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
2036 + CM_CLKSEL_PER_GPT6_OFFSET;\
2037 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2038 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT6Write32k32);\
2039 + data &= ~(CM_CLKSEL_PER_GPT6_MASK);\
2040 + data |= newValue;\
2041 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2042 +}
2043 +
2044 +
2045 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32(baseAddress)\
2046 +{\
2047 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
2048 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys <<\
2049 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
2050 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2051 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32);\
2052 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
2053 + data |= newValue;\
2054 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2055 +}
2056 +
2057 +
2058 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32(baseAddress)\
2059 +{\
2060 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
2061 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext <<\
2062 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
2063 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2064 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32);\
2065 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
2066 + data |= newValue;\
2067 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2068 +}
2069 +
2070 +
2071 +#define PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32(baseAddress)\
2072 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32),\
2073 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2074 + (PRCM_CM_CLKSEL1_PLL_OFFSET)))) &\
2075 + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK) >>\
2076 + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET))
2077 +
2078 +
2079 +#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress,value)\
2080 +{\
2081 + const u32 offset = CM_FCLKEN_IVA2_OFFSET;\
2082 + register u32 data = \
2083 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2084 + register u32 newValue = ((u32)(value));\
2085 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32);\
2086 + data &= ~(CM_FCLKEN_IVA2_EN_MASK);\
2087 + newValue <<= CM_FCLKEN_IVA2_EN_OFFSET;\
2088 + newValue &= CM_FCLKEN_IVA2_EN_MASK;\
2089 + newValue |= data;\
2090 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2091 +}
2092 +
2093 +
2094 +#define PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32(baseAddress, value)\
2095 +{\
2096 + const u32 offset = PRCM_CM_ICLKEN_DSP_OFFSET;\
2097 + register u32 data = \
2098 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2099 + register u32 newValue = ((u32)(value));\
2100 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32);\
2101 + data &= ~(PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK);\
2102 + newValue <<= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET;\
2103 + newValue &= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK;\
2104 + newValue |= data;\
2105 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2106 +}
2107 +
2108 +
2109 +#define PRCMCM_IDLEST_DSPReadRegister32(baseAddress)\
2110 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPReadRegister32),\
2111 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_CM_IDLEST_DSP_OFFSET))
2112 +
2113 +
2114 +#define PRCMCM_IDLEST_DSPST_IPIRead32(baseAddress)\
2115 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32),\
2116 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2117 + (PRCM_CM_IDLEST_DSP_OFFSET)))) &\
2118 + PRCM_CM_IDLEST_DSP_ST_IPI_MASK) >>\
2119 + PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET))
2120 +
2121 +
2122 +#define PRM_IDLEST_IVA2ST_IVA2Read32(baseAddress)\
2123 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32),\
2124 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2125 + (CM_IDLEST_IVA2_OFFSET)))) &\
2126 + CM_IDLEST_IVA2_ST_IVA2_MASK) >>\
2127 + CM_IDLEST_IVA2_ST_IVA2_OFFSET))
2128 +
2129 +
2130 +#define PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32(baseAddress, value)\
2131 +{\
2132 + const u32 offset = PRCM_CM_AUTOIDLE_DSP_OFFSET;\
2133 + register u32 data =\
2134 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2135 + register u32 newValue = ((u32)(value));\
2136 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32);\
2137 + data &= ~(PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK);\
2138 + newValue <<= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET;\
2139 + newValue &= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK;\
2140 + newValue |= data;\
2141 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2142 +}
2143 +
2144 +
2145 +#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress,value)\
2146 +{\
2147 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2148 + register u32 data = \
2149 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2150 + register u32 newValue = ((u32)(value));\
2151 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32);\
2152 + data &= ~(PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK);\
2153 + newValue <<= PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET;\
2154 + newValue &= PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK;\
2155 + newValue |= data;\
2156 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2157 +}
2158 +
2159 +
2160 +#define PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32(baseAddress, value)\
2161 +{\
2162 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2163 + register u32 data = \
2164 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2165 + register u32 newValue = ((u32)(value));\
2166 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32);\
2167 + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK);\
2168 + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET;\
2169 + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK;\
2170 + newValue |= data;\
2171 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2172 +}
2173 +
2174 +
2175 +#define PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32(baseAddress, value)\
2176 +{\
2177 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2178 + register u32 data = \
2179 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2180 + register u32 newValue = ((u32)(value));\
2181 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32);\
2182 + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK);\
2183 + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET;\
2184 + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK;\
2185 + newValue |= data;\
2186 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2187 +}
2188 +
2189 +
2190 +#define PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, value)\
2191 +{\
2192 + const u32 offset = PRCM_CM_CLKSTCTRL_IVA2_OFFSET;\
2193 + register u32 data = \
2194 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2195 + register u32 newValue = ((u32)(value));\
2196 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32);\
2197 + data &= ~(CM_CLKSTCTRL_IVA2_MASK);\
2198 + newValue <<= CM_CLKSTCTRL_IVA2_OFFSET;\
2199 + newValue &= CM_CLKSTCTRL_IVA2_MASK;\
2200 + newValue |= data;\
2201 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2202 +}
2203 +
2204 +
2205 +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32(baseAddress)\
2206 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32),\
2207 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2208 + (PRCM_CM_CLKSTCTRL_DSP_OFFSET)))) &\
2209 + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK) >>\
2210 + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET))
2211 +
2212 +
2213 +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32(baseAddress, value)\
2214 +{\
2215 + const u32 offset = PRCM_CM_CLKSTCTRL_DSP_OFFSET;\
2216 + register u32 data = \
2217 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2218 + register u32 newValue = ((u32)(value));\
2219 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32);\
2220 + data &= ~(PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK);\
2221 + newValue <<= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET;\
2222 + newValue &= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK;\
2223 + newValue |= data;\
2224 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2225 +}
2226 +
2227 +
2228 +#define PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress)\
2229 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32),\
2230 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET))
2231 +
2232 +
2233 +#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress,value)\
2234 +{\
2235 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2236 + register u32 data =\
2237 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2238 + register u32 newValue = ((u32)(value));\
2239 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2240 + data &= ~(PRM_RSTCTRL_IVA2_RST1_MASK);\
2241 + newValue <<= PRM_RSTCTRL_IVA2_RST1_OFFSET;\
2242 + newValue &= PRM_RSTCTRL_IVA2_RST1_MASK;\
2243 + newValue |= data;\
2244 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2245 +}
2246 +
2247 +
2248 +#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress,value)\
2249 +{\
2250 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2251 + register u32 data =\
2252 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2253 + register u32 newValue = ((u32)(value));\
2254 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2255 + data &= ~(PRM_RSTCTRL_IVA2_RST2_MASK);\
2256 + newValue <<= PRM_RSTCTRL_IVA2_RST2_OFFSET;\
2257 + newValue &= PRM_RSTCTRL_IVA2_RST2_MASK;\
2258 + newValue |= data;\
2259 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2260 +}
2261 +
2262 +
2263 +#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress,value)\
2264 +{\
2265 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2266 + register u32 data =\
2267 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2268 + register u32 newValue = ((u32)(value));\
2269 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2270 + data &= ~(PRM_RSTCTRL_IVA2_RST3_MASK);\
2271 + newValue <<= PRM_RSTCTRL_IVA2_RST3_OFFSET;\
2272 + newValue &= PRM_RSTCTRL_IVA2_RST3_MASK;\
2273 + newValue |= data;\
2274 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2275 +}
2276 +
2277 +
2278 +#define PRCMRM_RSTST_DSPReadRegister32(baseAddress)\
2279 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPReadRegister32),\
2280 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTST_DSP_OFFSET))
2281 +
2282 +
2283 +#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress,value)\
2284 +{\
2285 + const u32 offset = PRCM_RM_RSTST_DSP_OFFSET;\
2286 + register u32 newValue = ((u32)(value));\
2287 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPWriteRegister32);\
2288 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
2289 +}
2290 +
2291 +
2292 +#define PRCMPM_PWSTCTRL_DSPForceStateWrite32(baseAddress, value)\
2293 +{\
2294 + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
2295 + register u32 data = \
2296 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2297 + register u32 newValue = ((u32)(value));\
2298 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32);\
2299 + data &= ~(PRCM_PM_PWSTCTRL_DSP_ForceState_MASK);\
2300 + newValue <<= PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET;\
2301 + newValue &= PRCM_PM_PWSTCTRL_DSP_ForceState_MASK;\
2302 + newValue |= data;\
2303 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2304 +}
2305 +
2306 +
2307 +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress)\
2308 +{\
2309 + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
2310 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateON <<\
2311 + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
2312 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2313 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32);\
2314 + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
2315 + data |= newValue;\
2316 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2317 +}
2318 +
2319 +
2320 +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress)\
2321 +{\
2322 + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
2323 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateOFF <<\
2324 + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
2325 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2326 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32);\
2327 + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
2328 + data |= newValue;\
2329 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2330 +}
2331 +
2332 +
2333 +#define PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress)\
2334 +{\
2335 + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
2336 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_DSPPowerStateRET <<\
2337 + PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET;\
2338 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2339 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32);\
2340 + data &= ~(PRCM_PM_PWSTCTRL_DSP_PowerState_MASK);\
2341 + data |= newValue;\
2342 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2343 +}
2344 +
2345 +
2346 +#define PRCMPM_PWSTST_DSPReadRegister32(baseAddress)\
2347 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPReadRegister32),\
2348 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_DSP_OFFSET))
2349 +
2350 +
2351 +#define PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress)\
2352 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32),\
2353 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_IVA2_OFFSET))
2354 +
2355 +
2356 +#define PRCMPM_PWSTST_DSPInTransitionRead32(baseAddress)\
2357 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32),\
2358 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2359 + (PRCM_PM_PWSTST_DSP_OFFSET)))) &\
2360 + PRCM_PM_PWSTST_DSP_InTransition_MASK) >>\
2361 + PRCM_PM_PWSTST_DSP_InTransition_OFFSET))
2362 +
2363 +
2364 +#define PRCMPM_PWSTST_IVA2InTransitionRead32(baseAddress)\
2365 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32),\
2366 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2367 + (PRCM_PM_PWSTST_IVA2_OFFSET)))) &\
2368 + PRCM_PM_PWSTST_IVA2_InTransition_MASK) >>\
2369 + PRCM_PM_PWSTST_IVA2_InTransition_OFFSET))
2370 +
2371 +
2372 +#define PRCMPM_PWSTST_DSPPowerStateStGet32(var)\
2373 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32),\
2374 + (u32)((((u32)(var)) & PRCM_PM_PWSTST_DSP_PowerStateSt_MASK) >>\
2375 + PRCM_PM_PWSTST_DSP_PowerStateSt_OFFSET))
2376 +
2377 +
2378 +#define PRCMPM_PWSTST_IVA2PowerStateStGet32(var)\
2379 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32),\
2380 + (u32)((((u32)(var)) & PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK) >>\
2381 + PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET))
2382 +
2383 +
2384 +#endif /* USE_LEVEL_1_MACROS */
2385 +
2386 +#endif /* _PRCM_REG_ACM_H */
2387 diff --git a/drivers/dsp/bridge/hw/hw_defs.h b/drivers/dsp/bridge/hw/hw_defs.h
2388 new file mode 100644
2389 index 0000000..69a27b3
2390 --- /dev/null
2391 +++ b/drivers/dsp/bridge/hw/hw_defs.h
2392 @@ -0,0 +1,73 @@
2393 +/*
2394 + * linux/drivers/dsp/bridge/hw/common/inc/hw_defs.h
2395 + *
2396 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2397 + *
2398 + * Copyright (C) 2007 Texas Instruments, Inc.
2399 + *
2400 + * This package is free software; you can redistribute it and/or modify
2401 + * it under the terms of the GNU General Public License version 2 as
2402 + * published by the Free Software Foundation.
2403 + *
2404 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2405 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2406 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2407 + */
2408 +
2409 +
2410 +/*
2411 + * ======== hw_defs.h ========
2412 + * Description:
2413 + * Global HW definitions
2414 + *
2415 + *! Revision History:
2416 + *! ================
2417 + *! 19 Apr 2004 sb: Added generic page size, endianness and element size defns
2418 + *! 16 Feb 2003 sb: Initial version
2419 + */
2420 +#ifndef __HW_DEFS_H
2421 +#define __HW_DEFS_H
2422 +
2423 +#include <GlobalTypes.h>
2424 +
2425 +/* Page size */
2426 +#define HW_PAGE_SIZE_4KB 0x1000
2427 +#define HW_PAGE_SIZE_64KB 0x10000
2428 +#define HW_PAGE_SIZE_1MB 0x100000
2429 +#define HW_PAGE_SIZE_16MB 0x1000000
2430 +
2431 +/* HW_STATUS: return type for HW API */
2432 +typedef long HW_STATUS;
2433 +
2434 +/* HW_SetClear_t: Enumerated Type used to set and clear any bit */
2435 +enum HW_SetClear_t {
2436 + HW_CLEAR,
2437 + HW_SET
2438 +} ;
2439 +
2440 +/* HW_Endianism_t: Enumerated Type used to specify the endianism
2441 + * Do NOT change these values. They are used as bit fields. */
2442 +enum HW_Endianism_t {
2443 + HW_LITTLE_ENDIAN,
2444 + HW_BIG_ENDIAN
2445 +
2446 +} ;
2447 +
2448 +/* HW_ElementSize_t: Enumerated Type used to specify the element size
2449 + * Do NOT change these values. They are used as bit fields. */
2450 +enum HW_ElementSize_t {
2451 + HW_ELEM_SIZE_8BIT,
2452 + HW_ELEM_SIZE_16BIT,
2453 + HW_ELEM_SIZE_32BIT,
2454 + HW_ELEM_SIZE_64BIT
2455 +
2456 +} ;
2457 +
2458 +/* HW_IdleMode_t: Enumerated Type used to specify Idle modes */
2459 + enum HW_IdleMode_t {
2460 + HW_FORCE_IDLE,
2461 + HW_NO_IDLE,
2462 + HW_SMART_IDLE
2463 + } ;
2464 +
2465 +#endif /* __HW_DEFS_H */
2466 diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.c b/drivers/dsp/bridge/hw/hw_dspssC64P.c
2467 new file mode 100644
2468 index 0000000..2411b51
2469 --- /dev/null
2470 +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.c
2471 @@ -0,0 +1,55 @@
2472 +/*
2473 + * linux/drivers/dsp/bridge/hw/omap3/dspss/hw_dspss64P.c
2474 + *
2475 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2476 + *
2477 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
2478 + *
2479 + * This package is free software; you can redistribute it and/or modify
2480 + * it under the terms of the GNU General Public License version 2 as
2481 + * published by the Free Software Foundation.
2482 + *
2483 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2484 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2485 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2486 + */
2487 +
2488 +/*
2489 + * ======== hw_dspss64P.c ========
2490 + * Description:
2491 + * API definitions to configure DSP Subsystem modules like IPI
2492 + *
2493 + *! Revision History:
2494 + *! ================
2495 + *! 19 Apr 2004 sb: Implemented HW_DSPSS_IPIEndianismSet
2496 + *! 16 Feb 2003 sb: Initial version
2497 + */
2498 +
2499 +/* PROJECT SPECIFIC INCLUDE FILES */
2500 +#include <GlobalTypes.h>
2501 +#include <hw_defs.h>
2502 +#include <hw_dspssC64P.h>
2503 +#include <IVA2RegAcM.h>
2504 +#include <IPIAccInt.h>
2505 +
2506 +/* HW FUNCTIONS */
2507 +HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
2508 + enum HW_DSPSYSC_BootMode_t bootMode,
2509 + const u32 bootAddress)
2510 +{
2511 + HW_STATUS status = RET_OK;
2512 + u32 offset = SYSC_IVA2BOOTMOD_OFFSET;
2513 + u32 alignedBootAddr;
2514 +
2515 + /* if Boot mode it DIRECT BOOT, check that the bootAddress is
2516 + * aligned to atleast 1K :: TODO */
2517 + WR_MEM_32_VOLATILE((baseAddress) + offset, bootMode);
2518 +
2519 + offset = SYSC_IVA2BOOTADDR_OFFSET;
2520 +
2521 + alignedBootAddr = bootAddress & SYSC_IVA2BOOTADDR_MASK;
2522 +
2523 + WR_MEM_32_VOLATILE((baseAddress) + offset, alignedBootAddr);
2524 +
2525 + return status;
2526 +}
2527 diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.h b/drivers/dsp/bridge/hw/hw_dspssC64P.h
2528 new file mode 100644
2529 index 0000000..3a5f820
2530 --- /dev/null
2531 +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.h
2532 @@ -0,0 +1,48 @@
2533 +/*
2534 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_dspssC64P.h
2535 + *
2536 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2537 + *
2538 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
2539 + *
2540 + * This package is free software; you can redistribute it and/or modify
2541 + * it under the terms of the GNU General Public License version 2 as
2542 + * published by the Free Software Foundation.
2543 + *
2544 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2545 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2546 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2547 + */
2548 +
2549 +
2550 +/*
2551 + * ======== hw_dspss.h ========
2552 + * Description:
2553 + * DSP Subsystem API declarations
2554 + *
2555 + *! Revision History:
2556 + *! ================
2557 + *! 19-Apr-2004 sb: Removed redundant argument from HW_DSPSS_IPIEndianismSet
2558 + *! Moved endianness and element size to generic hw_defs.h
2559 + *! 16 Feb 2003 sb: Initial version
2560 + */
2561 +
2562 +#ifndef __HW_DSPSS_H
2563 +#define __HW_DSPSS_H
2564 +#include <linux/types.h>
2565 +
2566 + enum HW_DSPSYSC_BootMode_t {
2567 + HW_DSPSYSC_DIRECTBOOT = 0x0,
2568 + HW_DSPSYSC_IDLEBOOT = 0x1,
2569 + HW_DSPSYSC_SELFLOOPBOOT = 0x2,
2570 + HW_DSPSYSC_USRBOOTSTRAP = 0x3,
2571 + HW_DSPSYSC_DEFAULTRESTORE = 0x4
2572 + } ;
2573 +
2574 +#define HW_DSP_IDLEBOOT_ADDR 0x007E0000
2575 +
2576 + extern HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
2577 + enum HW_DSPSYSC_BootMode_t bootMode,
2578 + const u32 bootAddress);
2579 +
2580 +#endif /* __HW_DSPSS_H */
2581 diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c
2582 new file mode 100644
2583 index 0000000..ec1fc04
2584 --- /dev/null
2585 +++ b/drivers/dsp/bridge/hw/hw_mbox.c
2586 @@ -0,0 +1,255 @@
2587 +/*
2588 + * linux/drivers/dsp/bridge/hw/omap3/mbox/hw_mbox.c
2589 + *
2590 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2591 + *
2592 + * Copyright (C) 2007 Texas Instruments, Inc.
2593 + *
2594 + * This package is free software; you can redistribute it and/or modify
2595 + * it under the terms of the GNU General Public License version 2 as
2596 + * published by the Free Software Foundation.
2597 + *
2598 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2599 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2600 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2601 + */
2602 +
2603 +
2604 +/*
2605 + * ======== hw_mbox.c ========
2606 + * Description:
2607 + * Mailbox messaging & configuration API definitions
2608 + *
2609 + *! Revision History:
2610 + *! ================
2611 + *! 16 Feb 2003 sb: Initial version
2612 + */
2613 +
2614 +#include <GlobalTypes.h>
2615 +#include "MLBRegAcM.h"
2616 +#include <hw_defs.h>
2617 +#include <hw_mbox.h>
2618 +
2619 +/* width in bits of MBOX Id */
2620 +#define HW_MBOX_ID_WIDTH 2
2621 +
2622 +struct MAILBOX_CONTEXT mboxsetting = {0, 0, 0};
2623 +
2624 +/* Saves the mailbox context */
2625 +HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
2626 +{
2627 + HW_STATUS status = RET_OK;
2628 +
2629 + mboxsetting.sysconfig = MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress);
2630 + /* Get current enable status */
2631 + mboxsetting.irqEnable0 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2632 + (baseAddress, HW_MBOX_U0_ARM);
2633 + mboxsetting.irqEnable1 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2634 + (baseAddress, HW_MBOX_U1_DSP1);
2635 + return status;
2636 +}
2637 +
2638 +/* Restores the mailbox context */
2639 +HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
2640 +{
2641 + HW_STATUS status = RET_OK;
2642 + /* Restor IRQ enable status */
2643 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, HW_MBOX_U0_ARM,
2644 + mboxsetting.irqEnable0);
2645 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, HW_MBOX_U1_DSP1,
2646 + mboxsetting.irqEnable1);
2647 + /* Restore Sysconfig register */
2648 + MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, mboxsetting.sysconfig);
2649 + return status;
2650 +}
2651 +
2652 +/* Reads a u32 from the sub module message box Specified. if there are no
2653 + * messages in the mailbox then and error is returned. */
2654 +HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2655 + u32 *const pReadValue)
2656 +{
2657 + HW_STATUS status = RET_OK;
2658 +
2659 + /* Check input parameters */
2660 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2661 + RES_INVALID_INPUT_PARAM);
2662 + CHECK_INPUT_PARAM(pReadValue, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2663 + RES_INVALID_INPUT_PARAM);
2664 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2665 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2666 +
2667 + /* Read 32-bit message in mail box */
2668 + *pReadValue = MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress,
2669 + (u32)mailBoxId);
2670 +
2671 + return status;
2672 +}
2673 +
2674 +/* Writes a u32 from the sub module message box Specified. */
2675 +HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2676 + const u32 writeValue)
2677 +{
2678 + HW_STATUS status = RET_OK;
2679 +
2680 + /* Check input parameters */
2681 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2682 + RES_INVALID_INPUT_PARAM);
2683 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2684 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2685 +
2686 + /* Write 32-bit value to mailbox */
2687 + MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, (u32)mailBoxId,
2688 + (u32)writeValue);
2689 +
2690 + return status;
2691 +}
2692 +
2693 +/* Reads the full status register for mailbox. */
2694 +HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2695 + u32 *const pIsFull)
2696 +{
2697 + HW_STATUS status = RET_OK;
2698 + u32 fullStatus;
2699 +
2700 + /* Check input parameters */
2701 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2702 + RES_INVALID_INPUT_PARAM);
2703 + CHECK_INPUT_PARAM(pIsFull, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2704 + RES_INVALID_INPUT_PARAM);
2705 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2706 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2707 +
2708 + /* read the is full status parameter for Mailbox */
2709 + fullStatus = MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress,
2710 + (u32)mailBoxId);
2711 +
2712 + /* fill in return parameter */
2713 + *pIsFull = (fullStatus & 0xFF);
2714 +
2715 + return status;
2716 +}
2717 +
2718 +/* Gets number of messages in a specified mailbox. */
2719 +HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2720 + u32 *const pNumMsg)
2721 +{
2722 + HW_STATUS status = RET_OK;
2723 +
2724 + /* Check input parameters */
2725 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2726 + RES_INVALID_INPUT_PARAM);
2727 + CHECK_INPUT_PARAM(pNumMsg, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2728 + RES_INVALID_INPUT_PARAM);
2729 +
2730 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2731 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2732 +
2733 + /* Get number of messages available for MailBox */
2734 + *pNumMsg = MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress,
2735 + (u32)mailBoxId);
2736 +
2737 + return status;
2738 +}
2739 +
2740 +/* Enables the specified IRQ. */
2741 +HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
2742 + const HW_MBOX_Id_t mailBoxId,
2743 + const HW_MBOX_UserId_t userId,
2744 + const u32 events)
2745 +{
2746 + HW_STATUS status = RET_OK;
2747 + u32 irqEnableReg;
2748 +
2749 + /* Check input parameters */
2750 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2751 + RES_INVALID_INPUT_PARAM);
2752 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2753 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2754 + CHECK_INPUT_RANGE_MIN0(enableIrq, HW_MBOX_INT_MAX, RET_INVALID_ID,
2755 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2756 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2757 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2758 +
2759 + /* Get current enable status */
2760 + irqEnableReg = MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress,
2761 + (u32)userId);
2762 +
2763 + /* update enable value */
2764 + irqEnableReg |= ((u32)(events)) << (((u32)(mailBoxId)) *
2765 + HW_MBOX_ID_WIDTH);
2766 +
2767 + /* write new enable status */
2768 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, (u32)userId,
2769 + (u32)irqEnableReg);
2770 +
2771 + mboxsetting.sysconfig = MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress);
2772 + /* Get current enable status */
2773 + mboxsetting.irqEnable0 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2774 + (baseAddress, HW_MBOX_U0_ARM);
2775 + mboxsetting.irqEnable1 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2776 + (baseAddress, HW_MBOX_U1_DSP1);
2777 + return status;
2778 +}
2779 +
2780 +/* Disables the specified IRQ. */
2781 +HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
2782 + const HW_MBOX_Id_t mailBoxId,
2783 + const HW_MBOX_UserId_t userId,
2784 + const u32 events)
2785 +{
2786 + HW_STATUS status = RET_OK;
2787 + u32 irqDisableReg;
2788 +
2789 + /* Check input parameters */
2790 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2791 + RES_INVALID_INPUT_PARAM);
2792 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2793 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2794 + CHECK_INPUT_RANGE_MIN0(disableIrq, HW_MBOX_INT_MAX, RET_INVALID_ID,
2795 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2796 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2797 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2798 +
2799 + /* Get current enable status */
2800 + irqDisableReg = MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress,
2801 + (u32)userId);
2802 +
2803 + /* update enable value */
2804 + irqDisableReg &= ~((u32)(events)) << (((u32)(mailBoxId)) *
2805 + HW_MBOX_ID_WIDTH);
2806 +
2807 + /* write new enable status */
2808 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, (u32)userId,
2809 + (u32)irqDisableReg);
2810 +
2811 + return status;
2812 +}
2813 +
2814 +/* Sets the status of the specified IRQ. */
2815 +HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2816 + const HW_MBOX_UserId_t userId, const u32 event)
2817 +{
2818 + HW_STATUS status = RET_OK;
2819 + u32 irqStatusReg;
2820 +
2821 + /* Check input parameters */
2822 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2823 + RES_INVALID_INPUT_PARAM);
2824 +
2825 + CHECK_INPUT_RANGE_MIN0(irqStatus, HW_MBOX_INT_MAX, RET_INVALID_ID,
2826 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2827 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2828 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2829 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2830 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2831 +
2832 + /* calculate status to write */
2833 + irqStatusReg = ((u32)event) << (((u32)(mailBoxId)) *
2834 + HW_MBOX_ID_WIDTH);
2835 +
2836 + /* clear Irq Status for specified mailbox/User Id */
2837 + MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, (u32)userId,
2838 + (u32)irqStatusReg);
2839 +
2840 + return status;
2841 +}
2842 diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h
2843 new file mode 100644
2844 index 0000000..7579378
2845 --- /dev/null
2846 +++ b/drivers/dsp/bridge/hw/hw_mbox.h
2847 @@ -0,0 +1,358 @@
2848 +/*
2849 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_mbox.h
2850 + *
2851 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2852 + *
2853 + * Copyright (C) 2007 Texas Instruments, Inc.
2854 + *
2855 + * This package is free software; you can redistribute it and/or modify
2856 + * it under the terms of the GNU General Public License version 2 as
2857 + * published by the Free Software Foundation.
2858 + *
2859 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2860 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2861 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2862 + */
2863 +
2864 +/*
2865 + * ======== hw_mbox.h ========
2866 + * Description:
2867 + * HW Mailbox API and types definitions
2868 + *
2869 + *! Revision History:
2870 + *! ================
2871 + *! 16 Feb 2003 sb: Initial version
2872 + */
2873 +#ifndef __MBOX_H
2874 +#define __MBOX_H
2875 +
2876 +/* Bitmasks for Mailbox interrupt sources */
2877 +#define HW_MBOX_INT_NEW_MSG 0x1
2878 +#define HW_MBOX_INT_NOT_FULL 0x2
2879 +#define HW_MBOX_INT_ALL 0x3
2880 +
2881 +/* Maximum number of messages that mailbox can hald at a time. */
2882 +#define HW_MBOX_MAX_NUM_MESSAGES 4
2883 +
2884 +/* HW_MBOX_Id_t: Enumerated Type used to specify Mailbox Sub Module Id Number */
2885 +typedef enum HW_MBOX_Id_label {
2886 + HW_MBOX_ID_0,
2887 + HW_MBOX_ID_1,
2888 + HW_MBOX_ID_2,
2889 + HW_MBOX_ID_3,
2890 + HW_MBOX_ID_4,
2891 + HW_MBOX_ID_5
2892 +
2893 +} HW_MBOX_Id_t, *pHW_MBOX_Id_t;
2894 +
2895 +/* HW_MBOX_UserId_t: Enumerated Type used to specify Mail box User Id */
2896 +typedef enum HW_MBOX_UserId_label {
2897 + HW_MBOX_U0_ARM,
2898 + HW_MBOX_U1_DSP1,
2899 + HW_MBOX_U2_DSP2,
2900 + HW_MBOX_U3_ARM
2901 +
2902 +} HW_MBOX_UserId_t, *pHW_MBOX_UserId_t;
2903 +
2904 +/* Mailbox context settings */
2905 +struct MAILBOX_CONTEXT {
2906 + u32 sysconfig;
2907 + u32 irqEnable0;
2908 + u32 irqEnable1;
2909 +};
2910 +
2911 +/*
2912 +* FUNCTION : HW_MBOX_MsgRead
2913 +*
2914 +* INPUTS:
2915 +*
2916 +* Identifier : baseAddress
2917 +* Type : const u32
2918 +* Description : Base Address of instance of Mailbox module
2919 +*
2920 +* Identifier : mailBoxId
2921 +* Type : const HW_MBOX_Id_t
2922 +* Description : Mail Box Sub module Id to read
2923 +*
2924 +* OUTPUTS:
2925 +*
2926 +* Identifier : pReadValue
2927 +* Type : u32 *const
2928 +* Description : Value read from MailBox
2929 +*
2930 +* RETURNS:
2931 +*
2932 +* Type : ReturnCode_t
2933 +* Description : RET_OK No errors occured
2934 +* RET_BAD_NULL_PARAM Address/ptr Paramater was set to 0/NULL
2935 +* RET_INVALID_ID Invalid Id used
2936 +* RET_EMPTY Mailbox empty
2937 +*
2938 +* PURPOSE: : this function reads a u32 from the sub module message
2939 +* box Specified. if there are no messages in the mailbox
2940 +* then and error is returned.
2941 +*/
2942 +extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
2943 + const HW_MBOX_Id_t mailBoxId,
2944 + u32 *const pReadValue);
2945 +
2946 +/*
2947 +* FUNCTION : HW_MBOX_MsgWrite
2948 +*
2949 +* INPUTS:
2950 +*
2951 +* Identifier : baseAddress
2952 +* Type : const u32
2953 +* Description : Base Address of instance of Mailbox module
2954 +*
2955 +* Identifier : mailBoxId
2956 +* Type : const HW_MBOX_Id_t
2957 +* Description : Mail Box Sub module Id to write
2958 +*
2959 +* Identifier : writeValue
2960 +* Type : const u32
2961 +* Description : Value to write to MailBox
2962 +*
2963 +* RETURNS:
2964 +*
2965 +* Type : ReturnCode_t
2966 +* Description : RET_OK No errors occured
2967 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
2968 +* RET_INVALID_ID Invalid Id used
2969 +*
2970 +* PURPOSE: : this function writes a u32 from the sub module message
2971 +* box Specified.
2972 +*/
2973 +extern HW_STATUS HW_MBOX_MsgWrite(
2974 + const u32 baseAddress,
2975 + const HW_MBOX_Id_t mailBoxId,
2976 + const u32 writeValue
2977 + );
2978 +
2979 +/*
2980 +* FUNCTION : HW_MBOX_IsFull
2981 +*
2982 +* INPUTS:
2983 +*
2984 +* Identifier : baseAddress
2985 +* Type : const u32
2986 +* Description : Base Address of instance of Mailbox module
2987 +*
2988 +* Identifier : mailBoxId
2989 +* Type : const HW_MBOX_Id_t
2990 +* Description : Mail Box Sub module Id to check
2991 +*
2992 +* OUTPUTS:
2993 +*
2994 +* Identifier : pIsFull
2995 +* Type : u32 *const
2996 +* Description : false means mail box not Full
2997 +* true means mailbox full.
2998 +*
2999 +* RETURNS:
3000 +*
3001 +* Type : ReturnCode_t
3002 +* Description : RET_OK No errors occured
3003 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3004 +* RET_INVALID_ID Invalid Id used
3005 +*
3006 +* PURPOSE: : this function reads the full status register for mailbox.
3007 +*/
3008 +extern HW_STATUS HW_MBOX_IsFull(
3009 + const u32 baseAddress,
3010 + const HW_MBOX_Id_t mailBoxId,
3011 + u32 *const pIsFull
3012 + );
3013 +
3014 +/*
3015 +* FUNCTION : HW_MBOX_NumMsgGet
3016 +*
3017 +* INPUTS:
3018 +*
3019 +* Identifier : baseAddress
3020 +* Type : const u32
3021 +* Description : Base Address of instance of Mailbox module
3022 +*
3023 +* Identifier : mailBoxId
3024 +* Type : const HW_MBOX_Id_t
3025 +* Description : Mail Box Sub module Id to get num messages
3026 +*
3027 +* OUTPUTS:
3028 +*
3029 +* Identifier : pNumMsg
3030 +* Type : u32 *const
3031 +* Description : Number of messages in mailbox
3032 +*
3033 +* RETURNS:
3034 +*
3035 +* Type : ReturnCode_t
3036 +* Description : RET_OK No errors occured
3037 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3038 +* RET_INVALID_ID Inavlid ID input at parameter
3039 +*
3040 +* PURPOSE: : this function gets number of messages in a specified mailbox.
3041 +*/
3042 +extern HW_STATUS HW_MBOX_NumMsgGet(
3043 + const u32 baseAddress,
3044 + const HW_MBOX_Id_t mailBoxId,
3045 + u32 *const pNumMsg
3046 + );
3047 +
3048 +/*
3049 +* FUNCTION : HW_MBOX_EventEnable
3050 +*
3051 +* INPUTS:
3052 +*
3053 +* Identifier : baseAddress
3054 +* Type : const u32
3055 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3056 +*
3057 +* Identifier : mailBoxId
3058 +* Type : const HW_MBOX_Id_t
3059 +* Description : Mail Box Sub module Id to enable
3060 +*
3061 +* Identifier : userId
3062 +* Type : const HW_MBOX_UserId_t
3063 +* Description : Mail box User Id to enable
3064 +*
3065 +* Identifier : enableIrq
3066 +* Type : const u32
3067 +* Description : Irq value to enable
3068 +*
3069 +* RETURNS:
3070 +*
3071 +* Type : ReturnCode_t
3072 +* Description : RET_OK No errors occured
3073 +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL
3074 +* RET_INVALID_ID Invalid Id used
3075 +*
3076 +* PURPOSE: : this function enables the specified IRQ.
3077 +*/
3078 +extern HW_STATUS HW_MBOX_EventEnable(
3079 + const u32 baseAddress,
3080 + const HW_MBOX_Id_t mailBoxId,
3081 + const HW_MBOX_UserId_t userId,
3082 + const u32 events
3083 + );
3084 +
3085 +/*
3086 +* FUNCTION : HW_MBOX_EventDisable
3087 +*
3088 +* INPUTS:
3089 +*
3090 +* Identifier : baseAddress
3091 +* Type : const u32
3092 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3093 +*
3094 +* Identifier : mailBoxId
3095 +* Type : const HW_MBOX_Id_t
3096 +* Description : Mail Box Sub module Id to disable
3097 +*
3098 +* Identifier : userId
3099 +* Type : const HW_MBOX_UserId_t
3100 +* Description : Mail box User Id to disable
3101 +*
3102 +* Identifier : enableIrq
3103 +* Type : const u32
3104 +* Description : Irq value to disable
3105 +*
3106 +* RETURNS:
3107 +*
3108 +* Type : ReturnCode_t
3109 +* Description : RET_OK No errors occured
3110 +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL
3111 +* RET_INVALID_ID Invalid Id used
3112 +*
3113 +* PURPOSE: : this function disables the specified IRQ.
3114 +*/
3115 +extern HW_STATUS HW_MBOX_EventDisable(
3116 + const u32 baseAddress,
3117 + const HW_MBOX_Id_t mailBoxId,
3118 + const HW_MBOX_UserId_t userId,
3119 + const u32 events
3120 + );
3121 +
3122 +/*
3123 +* FUNCTION : HW_MBOX_EventAck
3124 +*
3125 +* INPUTS:
3126 +*
3127 +* Identifier : baseAddress
3128 +* Type : const u32
3129 +* Description : Base Address of instance of Mailbox module
3130 +*
3131 +* Identifier : mailBoxId
3132 +* Type : const HW_MBOX_Id_t
3133 +* Description : Mail Box Sub module Id to set
3134 +*
3135 +* Identifier : userId
3136 +* Type : const HW_MBOX_UserId_t
3137 +* Description : Mail box User Id to set
3138 +*
3139 +* Identifier : irqStatus
3140 +* Type : const u32
3141 +* Description : The value to write IRQ status
3142 +*
3143 +* OUTPUTS:
3144 +*
3145 +* RETURNS:
3146 +*
3147 +* Type : ReturnCode_t
3148 +* Description : RET_OK No errors occured
3149 +* RET_BAD_NULL_PARAM Address Paramater was set to 0
3150 +* RET_INVALID_ID Invalid Id used
3151 +*
3152 +* PURPOSE: : this function sets the status of the specified IRQ.
3153 +*/
3154 +extern HW_STATUS HW_MBOX_EventAck(
3155 + const u32 baseAddress,
3156 + const HW_MBOX_Id_t mailBoxId,
3157 + const HW_MBOX_UserId_t userId,
3158 + const u32 event
3159 + );
3160 +
3161 +/*
3162 +* FUNCTION : HW_MBOX_saveSettings
3163 +*
3164 +* INPUTS:
3165 +*
3166 +* Identifier : baseAddress
3167 +* Type : const u32
3168 +* Description : Base Address of instance of Mailbox module
3169 +*
3170 +*
3171 +* RETURNS:
3172 +*
3173 +* Type : ReturnCode_t
3174 +* Description : RET_OK No errors occured
3175 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3176 +* RET_INVALID_ID Invalid Id used
3177 +* RET_EMPTY Mailbox empty
3178 +*
3179 +* PURPOSE: : this function saves the context of mailbox
3180 +*/
3181 +extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
3182 +
3183 +/*
3184 +* FUNCTION : HW_MBOX_restoreSettings
3185 +*
3186 +* INPUTS:
3187 +*
3188 +* Identifier : baseAddress
3189 +* Type : const u32
3190 +* Description : Base Address of instance of Mailbox module
3191 +*
3192 +*
3193 +* RETURNS:
3194 +*
3195 +* Type : ReturnCode_t
3196 +* Description : RET_OK No errors occured
3197 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3198 +* RET_INVALID_ID Invalid Id used
3199 +* RET_EMPTY Mailbox empty
3200 +*
3201 +* PURPOSE: : this function restores the context of mailbox
3202 +*/
3203 +extern HW_STATUS HW_MBOX_restoreSettings(u32 baseAddres);
3204 +
3205 +#endif /* __MBOX_H */
3206 diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c
3207 new file mode 100644
3208 index 0000000..e79728a
3209 --- /dev/null
3210 +++ b/drivers/dsp/bridge/hw/hw_mmu.c
3211 @@ -0,0 +1,607 @@
3212 +/*
3213 + * linux/drivers/dsp/bridge/hw/omap3/mmu/hw_mmu.c
3214 + *
3215 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
3216 + *
3217 + * Copyright (C) 2007 Texas Instruments, Inc.
3218 + *
3219 + * This package is free software; you can redistribute it and/or modify
3220 + * it under the terms of the GNU General Public License version 2 as
3221 + * published by the Free Software Foundation.
3222 + *
3223 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
3224 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
3225 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
3226 + */
3227 +
3228 +/*
3229 + * ======== hw_mmu.c ========
3230 + * Description:
3231 + * API definitions to setup MMU TLB and PTE
3232 + *
3233 + *! Revision History:
3234 + *! ================
3235 + *! 19-Apr-2004 sb TLBAdd and TLBFlush input the page size in bytes instead
3236 + of an enum. TLBAdd inputs mapping attributes struct instead
3237 + of individual arguments.
3238 + Removed MMU.h and other cosmetic updates.
3239 + *! 08-Mar-2004 sb Added the Page Table Management APIs
3240 + *! 16 Feb 2003 sb: Initial version
3241 + */
3242 +
3243 +#include <GlobalTypes.h>
3244 +#include "MMURegAcM.h"
3245 +#include <hw_defs.h>
3246 +#include <hw_mmu.h>
3247 +#include <linux/types.h>
3248 +
3249 +#define MMU_BASE_VAL_MASK 0xFC00
3250 +#define MMU_PAGE_MAX 3
3251 +#define MMU_ELEMENTSIZE_MAX 3
3252 +#define MMU_ADDR_MASK 0xFFFFF000
3253 +#define MMU_TTB_MASK 0xFFFFC000
3254 +#define MMU_SECTION_ADDR_MASK 0xFFF00000
3255 +#define MMU_SSECTION_ADDR_MASK 0xFF000000
3256 +#define MMU_PAGE_TABLE_MASK 0xFFFFFC00
3257 +#define MMU_LARGE_PAGE_MASK 0xFFFF0000
3258 +#define MMU_SMALL_PAGE_MASK 0xFFFFF000
3259 +
3260 +#define MMU_LOAD_TLB 0x00000001
3261 +
3262 +/* HW_MMUPageSize_t: Enumerated Type used to specify the MMU Page Size(SLSS) */
3263 +enum HW_MMUPageSize_t {
3264 + HW_MMU_SECTION,
3265 + HW_MMU_LARGE_PAGE,
3266 + HW_MMU_SMALL_PAGE,
3267 + HW_MMU_SUPERSECTION
3268 +} ;
3269 +
3270 +/*
3271 +* FUNCTION : MMU_FlushEntry
3272 +*
3273 +* INPUTS:
3274 +*
3275 +* Identifier : baseAddress
3276 +* Type : const u32
3277 +* Description : Base Address of instance of MMU module
3278 +*
3279 +* RETURNS:
3280 +*
3281 +* Type : HW_STATUS
3282 +* Description : RET_OK -- No errors occured
3283 +* RET_BAD_NULL_PARAM -- A Pointer
3284 +* Paramater was set to NULL
3285 +*
3286 +* PURPOSE: : Flush the TLB entry pointed by the
3287 +* lock counter register
3288 +* even if this entry is set protected
3289 +*
3290 +* METHOD: : Check the Input parameter and Flush a
3291 +* single entry in the TLB.
3292 +*/
3293 +static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
3294 +
3295 +/*
3296 +* FUNCTION : MMU_SetCAMEntry
3297 +*
3298 +* INPUTS:
3299 +*
3300 +* Identifier : baseAddress
3301 +* TypE : const u32
3302 +* Description : Base Address of instance of MMU module
3303 +*
3304 +* Identifier : pageSize
3305 +* TypE : const u32
3306 +* Description : It indicates the page size
3307 +*
3308 +* Identifier : preservedBit
3309 +* Type : const u32
3310 +* Description : It indicates the TLB entry is preserved entry
3311 +* or not
3312 +*
3313 +* Identifier : validBit
3314 +* Type : const u32
3315 +* Description : It indicates the TLB entry is valid entry or not
3316 +*
3317 +*
3318 +* Identifier : virtualAddrTag
3319 +* Type : const u32
3320 +* Description : virtual Address
3321 +*
3322 +* RETURNS:
3323 +*
3324 +* Type : HW_STATUS
3325 +* Description : RET_OK -- No errors occured
3326 +* RET_BAD_NULL_PARAM -- A Pointer Paramater
3327 +* was set to NULL
3328 +* RET_PARAM_OUT_OF_RANGE -- Input Parameter out
3329 +* of Range
3330 +*
3331 +* PURPOSE: : Set MMU_CAM reg
3332 +*
3333 +* METHOD: : Check the Input parameters and set the CAM entry.
3334 +*/
3335 +static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
3336 + const u32 pageSize,
3337 + const u32 preservedBit,
3338 + const u32 validBit,
3339 + const u32 virtualAddrTag);
3340 +
3341 +/*
3342 +* FUNCTION : MMU_SetRAMEntry
3343 +*
3344 +* INPUTS:
3345 +*
3346 +* Identifier : baseAddress
3347 +* Type : const u32
3348 +* Description : Base Address of instance of MMU module
3349 +*
3350 +* Identifier : physicalAddr
3351 +* Type : const u32
3352 +* Description : Physical Address to which the corresponding
3353 +* virtual Address shouldpoint
3354 +*
3355 +* Identifier : endianism
3356 +* Type : HW_Endianism_t
3357 +* Description : endianism for the given page
3358 +*
3359 +* Identifier : elementSize
3360 +* Type : HW_ElementSize_t
3361 +* Description : The element size ( 8,16, 32 or 64 bit)
3362 +*
3363 +* Identifier : mixedSize
3364 +* Type : HW_MMUMixedSize_t
3365 +* Description : Element Size to follow CPU or TLB
3366 +*
3367 +* RETURNS:
3368 +*
3369 +* Type : HW_STATUS
3370 +* Description : RET_OK -- No errors occured
3371 +* RET_BAD_NULL_PARAM -- A Pointer Paramater
3372 +* was set to NULL
3373 +* RET_PARAM_OUT_OF_RANGE -- Input Parameter
3374 +* out of Range
3375 +*
3376 +* PURPOSE: : Set MMU_CAM reg
3377 +*
3378 +* METHOD: : Check the Input parameters and set the RAM entry.
3379 +*/
3380 +static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
3381 + const u32 physicalAddr,
3382 + enum HW_Endianism_t endianism,
3383 + enum HW_ElementSize_t elementSize,
3384 + enum HW_MMUMixedSize_t mixedSize);
3385 +
3386 +/* HW FUNCTIONS */
3387 +
3388 +HW_STATUS HW_MMU_Enable(const u32 baseAddress)
3389 +{
3390 + HW_STATUS status = RET_OK;
3391 +
3392 + MMUMMU_CNTLMMUEnableWrite32(baseAddress, HW_SET);
3393 +
3394 + return status;
3395 +}
3396 +
3397 +HW_STATUS HW_MMU_Disable(const u32 baseAddress)
3398 +{
3399 + HW_STATUS status = RET_OK;
3400 +
3401 + MMUMMU_CNTLMMUEnableWrite32(baseAddress, HW_CLEAR);
3402 +
3403 + return status;
3404 +}
3405 +
3406 +HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
3407 + u32 numLockedEntries)
3408 +{
3409 + HW_STATUS status = RET_OK;
3410 +
3411 + MMUMMU_LOCKBaseValueWrite32(baseAddress, numLockedEntries);
3412 +
3413 + return status;
3414 +}
3415 +
3416 +HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
3417 + u32 victimEntryNum)
3418 +{
3419 + HW_STATUS status = RET_OK;
3420 +
3421 + MMUMMU_LOCKCurrentVictimWrite32(baseAddress, victimEntryNum);
3422 +
3423 + return status;
3424 +}
3425 +
3426 +HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
3427 +{
3428 + HW_STATUS status = RET_OK;
3429 +
3430 + MMUMMU_GFLUSHGlobalFlushWrite32(baseAddress, HW_SET);
3431 +
3432 + return status;
3433 +}
3434 +
3435 +HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
3436 +{
3437 + HW_STATUS status = RET_OK;
3438 +
3439 + MMUMMU_IRQSTATUSWriteRegister32(baseAddress, irqMask);
3440 +
3441 + return status;
3442 +}
3443 +
3444 +HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
3445 + u32 irqMask)
3446 +{
3447 + HW_STATUS status = RET_OK;
3448 + u32 irqReg;
3449 +
3450 + irqReg = MMUMMU_IRQENABLEReadRegister32(baseAddress);
3451 +
3452 + MMUMMU_IRQENABLEWriteRegister32(baseAddress, irqReg & ~irqMask);
3453 +
3454 + return status;
3455 +}
3456 +
3457 +HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
3458 +{
3459 + HW_STATUS status = RET_OK;
3460 + u32 irqReg;
3461 +
3462 + irqReg = MMUMMU_IRQENABLEReadRegister32(baseAddress);
3463 +
3464 + MMUMMU_IRQENABLEWriteRegister32(baseAddress, irqReg | irqMask);
3465 +
3466 + return status;
3467 +}
3468 +
3469 +
3470 +HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
3471 +{
3472 + HW_STATUS status = RET_OK;
3473 +
3474 + *irqMask = MMUMMU_IRQSTATUSReadRegister32(baseAddress);
3475 +
3476 + return status;
3477 +}
3478 +
3479 +
3480 +HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
3481 +{
3482 + HW_STATUS status = RET_OK;
3483 +
3484 + /*Check the input Parameters*/
3485 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3486 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3487 +
3488 + /* read values from register */
3489 + *addr = MMUMMU_FAULT_ADReadRegister32(baseAddress);
3490 +
3491 + return status;
3492 +}
3493 +
3494 +HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
3495 +{
3496 + HW_STATUS status = RET_OK;
3497 + u32 loadTTB;
3498 +
3499 + /*Check the input Parameters*/
3500 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3501 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3502 +
3503 + loadTTB = TTBPhysAddr & ~0x7FUL;
3504 + /* write values to register */
3505 + MMUMMU_TTBWriteRegister32(baseAddress, loadTTB);
3506 +
3507 + return status;
3508 +}
3509 +
3510 +HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
3511 +{
3512 + HW_STATUS status = RET_OK;
3513 +
3514 + MMUMMU_CNTLTWLEnableWrite32(baseAddress, HW_SET);
3515 +
3516 + return status;
3517 +}
3518 +
3519 +HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
3520 +{
3521 + HW_STATUS status = RET_OK;
3522 +
3523 + MMUMMU_CNTLTWLEnableWrite32(baseAddress, HW_CLEAR);
3524 +
3525 + return status;
3526 +}
3527 +
3528 +HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
3529 + u32 pageSize)
3530 +{
3531 + HW_STATUS status = RET_OK;
3532 + u32 virtualAddrTag;
3533 + enum HW_MMUPageSize_t pgSizeBits;
3534 +
3535 + switch (pageSize) {
3536 + case HW_PAGE_SIZE_4KB:
3537 + pgSizeBits = HW_MMU_SMALL_PAGE;
3538 + break;
3539 +
3540 + case HW_PAGE_SIZE_64KB:
3541 + pgSizeBits = HW_MMU_LARGE_PAGE;
3542 + break;
3543 +
3544 + case HW_PAGE_SIZE_1MB:
3545 + pgSizeBits = HW_MMU_SECTION;
3546 + break;
3547 +
3548 + case HW_PAGE_SIZE_16MB:
3549 + pgSizeBits = HW_MMU_SUPERSECTION;
3550 + break;
3551 +
3552 + default:
3553 + return RET_FAIL;
3554 + }
3555 +
3556 + /* Generate the 20-bit tag from virtual address */
3557 + virtualAddrTag = ((virtualAddr & MMU_ADDR_MASK) >> 12);
3558 +
3559 + MMU_SetCAMEntry(baseAddress, pgSizeBits, 0, 0, virtualAddrTag);
3560 +
3561 + MMU_FlushEntry(baseAddress);
3562 +
3563 + return status;
3564 +}
3565 +
3566 +HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
3567 + u32 physicalAddr,
3568 + u32 virtualAddr,
3569 + u32 pageSize,
3570 + u32 entryNum,
3571 + struct HW_MMUMapAttrs_t *mapAttrs,
3572 + enum HW_SetClear_t preservedBit,
3573 + enum HW_SetClear_t validBit)
3574 +{
3575 + HW_STATUS status = RET_OK;
3576 + u32 lockReg;
3577 + u32 virtualAddrTag;
3578 + enum HW_MMUPageSize_t mmuPgSize;
3579 +
3580 + /*Check the input Parameters*/
3581 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3582 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3583 + CHECK_INPUT_RANGE_MIN0(pageSize, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,
3584 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3585 + CHECK_INPUT_RANGE_MIN0(mapAttrs->elementSize, MMU_ELEMENTSIZE_MAX,
3586 + RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
3587 + RES_INVALID_INPUT_PARAM);
3588 +
3589 + switch (pageSize) {
3590 + case HW_PAGE_SIZE_4KB:
3591 + mmuPgSize = HW_MMU_SMALL_PAGE;
3592 + break;
3593 +
3594 + case HW_PAGE_SIZE_64KB:
3595 + mmuPgSize = HW_MMU_LARGE_PAGE;
3596 + break;
3597 +
3598 + case HW_PAGE_SIZE_1MB:
3599 + mmuPgSize = HW_MMU_SECTION;
3600 + break;
3601 +
3602 + case HW_PAGE_SIZE_16MB:
3603 + mmuPgSize = HW_MMU_SUPERSECTION;
3604 + break;
3605 +
3606 + default:
3607 + return RET_FAIL;
3608 + }
3609 +
3610 + lockReg = MMUMMU_LOCKReadRegister32(baseAddress);
3611 +
3612 + /* Generate the 20-bit tag from virtual address */
3613 + virtualAddrTag = ((virtualAddr & MMU_ADDR_MASK) >> 12);
3614 +
3615 + /* Write the fields in the CAM Entry Register */
3616 + MMU_SetCAMEntry(baseAddress, mmuPgSize, preservedBit, validBit,
3617 + virtualAddrTag);
3618 +
3619 + /* Write the different fields of the RAM Entry Register */
3620 + /* endianism of the page,Element Size of the page (8, 16, 32, 64 bit)*/
3621 + MMU_SetRAMEntry(baseAddress, physicalAddr, mapAttrs->endianism,
3622 + mapAttrs->elementSize, mapAttrs->mixedSize);
3623 +
3624 + /* Update the MMU Lock Register */
3625 + /* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1)*/
3626 + MMUMMU_LOCKCurrentVictimWrite32(baseAddress, entryNum);
3627 +
3628 + /* Enable loading of an entry in TLB by writing 1
3629 + into LD_TLB_REG register */
3630 + MMUMMU_LD_TLBWriteRegister32(baseAddress, MMU_LOAD_TLB);
3631 +
3632 +
3633 + MMUMMU_LOCKWriteRegister32(baseAddress, lockReg);
3634 +
3635 + return status;
3636 +}
3637 +
3638 +HW_STATUS HW_MMU_PteSet(const u32 pgTblVa,
3639 + u32 physicalAddr,
3640 + u32 virtualAddr,
3641 + u32 pageSize,
3642 + struct HW_MMUMapAttrs_t *mapAttrs)
3643 +{
3644 + HW_STATUS status = RET_OK;
3645 + u32 pteAddr, pteVal;
3646 + s32 numEntries = 1;
3647 +
3648 + switch (pageSize) {
3649 + case HW_PAGE_SIZE_4KB:
3650 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3651 + virtualAddr & MMU_SMALL_PAGE_MASK);
3652 + pteVal = ((physicalAddr & MMU_SMALL_PAGE_MASK) |
3653 + (mapAttrs->endianism << 9) |
3654 + (mapAttrs->elementSize << 4) |
3655 + (mapAttrs->mixedSize << 11) | 2
3656 + );
3657 + break;
3658 +
3659 + case HW_PAGE_SIZE_64KB:
3660 + numEntries = 16;
3661 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3662 + virtualAddr & MMU_LARGE_PAGE_MASK);
3663 + pteVal = ((physicalAddr & MMU_LARGE_PAGE_MASK) |
3664 + (mapAttrs->endianism << 9) |
3665 + (mapAttrs->elementSize << 4) |
3666 + (mapAttrs->mixedSize << 11) | 1
3667 + );
3668 + break;
3669 +
3670 + case HW_PAGE_SIZE_1MB:
3671 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3672 + virtualAddr & MMU_SECTION_ADDR_MASK);
3673 + pteVal = ((((physicalAddr & MMU_SECTION_ADDR_MASK) |
3674 + (mapAttrs->endianism << 15) |
3675 + (mapAttrs->elementSize << 10) |
3676 + (mapAttrs->mixedSize << 17)) &
3677 + ~0x40000) | 0x2
3678 + );
3679 + break;
3680 +
3681 + case HW_PAGE_SIZE_16MB:
3682 + numEntries = 16;
3683 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3684 + virtualAddr & MMU_SSECTION_ADDR_MASK);
3685 + pteVal = (((physicalAddr & MMU_SSECTION_ADDR_MASK) |
3686 + (mapAttrs->endianism << 15) |
3687 + (mapAttrs->elementSize << 10) |
3688 + (mapAttrs->mixedSize << 17)
3689 + ) | 0x40000 | 0x2
3690 + );
3691 + break;
3692 +
3693 + case HW_MMU_COARSE_PAGE_SIZE:
3694 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3695 + virtualAddr & MMU_SECTION_ADDR_MASK);
3696 + pteVal = (physicalAddr & MMU_PAGE_TABLE_MASK) | 1;
3697 + break;
3698 +
3699 + default:
3700 + return RET_FAIL;
3701 + }
3702 +
3703 + while (--numEntries >= 0)
3704 + ((u32 *)pteAddr)[numEntries] = pteVal;
3705 +
3706 + return status;
3707 +}
3708 +
3709 +HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
3710 + u32 virtualAddr,
3711 + u32 pgSize)
3712 +{
3713 + HW_STATUS status = RET_OK;
3714 + u32 pteAddr;
3715 + s32 numEntries = 1;
3716 +
3717 + switch (pgSize) {
3718 + case HW_PAGE_SIZE_4KB:
3719 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3720 + virtualAddr & MMU_SMALL_PAGE_MASK);
3721 + break;
3722 +
3723 + case HW_PAGE_SIZE_64KB:
3724 + numEntries = 16;
3725 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3726 + virtualAddr & MMU_LARGE_PAGE_MASK);
3727 + break;
3728 +
3729 + case HW_PAGE_SIZE_1MB:
3730 + case HW_MMU_COARSE_PAGE_SIZE:
3731 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3732 + virtualAddr & MMU_SECTION_ADDR_MASK);
3733 + break;
3734 +
3735 + case HW_PAGE_SIZE_16MB:
3736 + numEntries = 16;
3737 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3738 + virtualAddr & MMU_SSECTION_ADDR_MASK);
3739 + break;
3740 +
3741 + default:
3742 + return RET_FAIL;
3743 + }
3744 +
3745 + while (--numEntries >= 0)
3746 + ((u32 *)pteAddr)[numEntries] = 0;
3747 +
3748 + return status;
3749 +}
3750 +
3751 +/* MMU_FlushEntry */
3752 +static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
3753 +{
3754 + HW_STATUS status = RET_OK;
3755 + u32 flushEntryData = 0x1;
3756 +
3757 + /*Check the input Parameters*/
3758 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3759 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3760 +
3761 + /* write values to register */
3762 + MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, flushEntryData);
3763 +
3764 + return status;
3765 +}
3766 +
3767 +/* MMU_SetCAMEntry */
3768 +static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
3769 + const u32 pageSize,
3770 + const u32 preservedBit,
3771 + const u32 validBit,
3772 + const u32 virtualAddrTag)
3773 +{
3774 + HW_STATUS status = RET_OK;
3775 + u32 mmuCamReg;
3776 +
3777 + /*Check the input Parameters*/
3778 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3779 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3780 +
3781 + mmuCamReg = (virtualAddrTag << 12);
3782 + mmuCamReg = (mmuCamReg) | (pageSize) | (validBit << 2) |
3783 + (preservedBit << 3) ;
3784 +
3785 + /* write values to register */
3786 + MMUMMU_CAMWriteRegister32(baseAddress, mmuCamReg);
3787 +
3788 + return status;
3789 +}
3790 +
3791 +/* MMU_SetRAMEntry */
3792 +static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
3793 + const u32 physicalAddr,
3794 + enum HW_Endianism_t endianism,
3795 + enum HW_ElementSize_t elementSize,
3796 + enum HW_MMUMixedSize_t mixedSize)
3797 +{
3798 + HW_STATUS status = RET_OK;
3799 + u32 mmuRamReg;
3800 +
3801 + /*Check the input Parameters*/
3802 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3803 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3804 + CHECK_INPUT_RANGE_MIN0(elementSize, MMU_ELEMENTSIZE_MAX,
3805 + RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
3806 + RES_INVALID_INPUT_PARAM);
3807 +
3808 +
3809 + mmuRamReg = (physicalAddr & MMU_ADDR_MASK);
3810 + mmuRamReg = (mmuRamReg) | ((endianism << 9) | (elementSize << 7) |
3811 + (mixedSize << 6));
3812 +
3813 + /* write values to register */
3814 + MMUMMU_RAMWriteRegister32(baseAddress, mmuRamReg);
3815 +
3816 + return status;
3817 +
3818 +}
3819 diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h
3820 new file mode 100644
3821 index 0000000..8784276
3822 --- /dev/null
3823 +++ b/drivers/dsp/bridge/hw/hw_mmu.h
3824 @@ -0,0 +1,178 @@
3825 +/*
3826 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_mmu.h
3827 + *
3828 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
3829 + *
3830 + * Copyright (C) 2007 Texas Instruments, Inc.
3831 + *
3832 + * This package is free software; you can redistribute it and/or modify
3833 + * it under the terms of the GNU General Public License version 2 as
3834 + * published by the Free Software Foundation.
3835 + *
3836 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
3837 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
3838 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
3839 + */
3840 +
3841 +
3842 +/*
3843 + * ======== hw_mmu.h ========
3844 + * Description:
3845 + * MMU types and API declarations
3846 + *
3847 + *! Revision History:
3848 + *! ================
3849 + *! 19-Apr-2004 sb Moved & renamed endianness, page size, element size
3850 + TLBAdd takes in MMUMapAttrs instead of separate arguments
3851 + *! 08-Mar-2004 sb Added the Page Table management APIs
3852 + *! 16 Feb 2003 sb: Initial version
3853 + */
3854 +#ifndef __HW_MMU_H
3855 +#define __HW_MMU_H
3856 +
3857 +#include <linux/types.h>
3858 +
3859 +/* Bitmasks for interrupt sources */
3860 +#define HW_MMU_TRANSLATION_FAULT 0x2
3861 +#define HW_MMU_ALL_INTERRUPTS 0x1F
3862 +
3863 +#define HW_MMU_COARSE_PAGE_SIZE 0x400
3864 +
3865 +/* HW_MMUMixedSize_t: Enumerated Type used to specify whether to follow
3866 + CPU/TLB Element size */
3867 +enum HW_MMUMixedSize_t {
3868 + HW_MMU_TLBES,
3869 + HW_MMU_CPUES
3870 +
3871 +} ;
3872 +
3873 +/* HW_MMUMapAttrs_t: Struct containing MMU mapping attributes */
3874 +struct HW_MMUMapAttrs_t {
3875 + enum HW_Endianism_t endianism;
3876 + enum HW_ElementSize_t elementSize;
3877 + enum HW_MMUMixedSize_t mixedSize;
3878 +} ;
3879 +
3880 +extern HW_STATUS HW_MMU_Enable(const u32 baseAddress);
3881 +
3882 +extern HW_STATUS HW_MMU_Disable(const u32 baseAddress);
3883 +
3884 +extern HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
3885 + u32 numLockedEntries);
3886 +
3887 +extern HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
3888 + u32 victimEntryNum);
3889 +
3890 +/* For MMU faults */
3891 +extern HW_STATUS HW_MMU_EventAck(const u32 baseAddress,
3892 + u32 irqMask);
3893 +
3894 +extern HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
3895 + u32 irqMask);
3896 +
3897 +extern HW_STATUS HW_MMU_EventEnable(const u32 baseAddress,
3898 + u32 irqMask);
3899 +
3900 +extern HW_STATUS HW_MMU_EventStatus(const u32 baseAddress,
3901 + u32 *irqMask);
3902 +
3903 +extern HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress,
3904 + u32 *addr);
3905 +
3906 +/* Set the TT base address */
3907 +extern HW_STATUS HW_MMU_TTBSet(const u32 baseAddress,
3908 + u32 TTBPhysAddr);
3909 +
3910 +extern HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress);
3911 +
3912 +extern HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress);
3913 +
3914 +extern HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress,
3915 + u32 virtualAddr,
3916 + u32 pageSize);
3917 +
3918 +extern HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress);
3919 +
3920 +extern HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
3921 + u32 physicalAddr,
3922 + u32 virtualAddr,
3923 + u32 pageSize,
3924 + u32 entryNum,
3925 + struct HW_MMUMapAttrs_t *mapAttrs,
3926 + enum HW_SetClear_t preservedBit,
3927 + enum HW_SetClear_t validBit);
3928 +
3929 +
3930 +/* For PTEs */
3931 +extern HW_STATUS HW_MMU_PteSet(const u32 pgTblVa,
3932 + u32 physicalAddr,
3933 + u32 virtualAddr,
3934 + u32 pageSize,
3935 + struct HW_MMUMapAttrs_t *mapAttrs);
3936 +
3937 +extern HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
3938 + u32 pgSize,
3939 + u32 virtualAddr);
3940 +
3941 +static inline u32 HW_MMU_PteAddrL1(u32 L1_base, u32 va)
3942 +{
3943 + u32 pteAddr;
3944 + u32 VA_31_to_20;
3945 +
3946 + VA_31_to_20 = va >> (20 - 2); /* Left-shift by 2 here itself */
3947 + VA_31_to_20 &= 0xFFFFFFFCUL;
3948 + pteAddr = L1_base + VA_31_to_20;
3949 +
3950 + return pteAddr;
3951 +}
3952 +
3953 +static inline u32 HW_MMU_PteAddrL2(u32 L2_base, u32 va)
3954 +{
3955 + u32 pteAddr;
3956 +
3957 + pteAddr = (L2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
3958 +
3959 + return pteAddr;
3960 +}
3961 +
3962 +static inline u32 HW_MMU_PteCoarseL1(u32 pteVal)
3963 +{
3964 + u32 pteCoarse;
3965 +
3966 + pteCoarse = pteVal & 0xFFFFFC00;
3967 +
3968 + return pteCoarse;
3969 +}
3970 +
3971 +static inline u32 HW_MMU_PteSizeL1(u32 pteVal)
3972 +{
3973 + u32 pteSize = 0;
3974 +
3975 + if ((pteVal & 0x3) == 0x1) {
3976 + /* Points to L2 PT */
3977 + pteSize = HW_MMU_COARSE_PAGE_SIZE;
3978 + }
3979 +
3980 + if ((pteVal & 0x3) == 0x2) {
3981 + if (pteVal & (1 << 18))
3982 + pteSize = HW_PAGE_SIZE_16MB;
3983 + else
3984 + pteSize = HW_PAGE_SIZE_1MB;
3985 + }
3986 +
3987 + return pteSize;
3988 +}
3989 +
3990 +static inline u32 HW_MMU_PteSizeL2(u32 pteVal)
3991 +{
3992 + u32 pteSize = 0;
3993 +
3994 + if (pteVal & 0x2)
3995 + pteSize = HW_PAGE_SIZE_4KB;
3996 + else if (pteVal & 0x1)
3997 + pteSize = HW_PAGE_SIZE_64KB;
3998 +
3999 + return pteSize;
4000 +}
4001 +
4002 +#endif /* __HW_MMU_H */
4003 diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
4004 new file mode 100644
4005 index 0000000..ed1f3c7
4006 --- /dev/null
4007 +++ b/drivers/dsp/bridge/hw/hw_prcm.c
4008 @@ -0,0 +1,167 @@
4009 +/*
4010 + * linux/drivers/dsp/bridge/hw/omap3/prcm/hw_prcm.c
4011 + *
4012 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
4013 + *
4014 + * Copyright (C) 2007 Texas Instruments, Inc.
4015 + *
4016 + * This package is free software; you can redistribute it and/or modify
4017 + * it under the terms of the GNU General Public License version 2 as
4018 + * published by the Free Software Foundation.
4019 + *
4020 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
4021 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
4022 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
4023 + */
4024 +
4025 +/*
4026 + * ======== hw_prcm.c ========
4027 + * Description:
4028 + * API definitions to configure PRCM (Power, Reset & Clocks Manager)
4029 + *
4030 + *! Revision History:
4031 + *! ================
4032 + *! 16 Feb 2003 sb: Initial version
4033 + */
4034 +
4035 +#include <GlobalTypes.h>
4036 +#include "PRCMRegAcM.h"
4037 +#include <hw_defs.h>
4038 +#include <hw_prcm.h>
4039 +
4040 +static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
4041 + enum HW_RstModule_t r,
4042 + enum HW_SetClear_t val);
4043 +
4044 +HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
4045 +{
4046 + return HW_RST_WriteVal(baseAddress, r, HW_SET);
4047 +}
4048 +
4049 +HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
4050 +{
4051 + return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
4052 +}
4053 +
4054 +static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
4055 + enum HW_RstModule_t r,
4056 + enum HW_SetClear_t val)
4057 +{
4058 + HW_STATUS status = RET_OK;
4059 +
4060 + switch (r) {
4061 + case HW_RST1_IVA2:
4062 + PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
4063 + break;
4064 + case HW_RST2_IVA2:
4065 + PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
4066 + break;
4067 + case HW_RST3_IVA2:
4068 + PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
4069 + break;
4070 + default:
4071 + status = RET_FAIL;
4072 + break;
4073 + }
4074 + return status;
4075 +}
4076 +
4077 +HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
4078 + enum HW_PwrState_t *value)
4079 +{
4080 + HW_STATUS status = RET_OK;
4081 + u32 temp;
4082 +
4083 + switch (p) {
4084 + case HW_PWR_DOMAIN_DSP:
4085 + /* wait until Transition is complete */
4086 + do {
4087 + /* mdelay(1); */
4088 + temp = PRCMPM_PWSTST_IVA2InTransitionRead32
4089 + (baseAddress);
4090 +
4091 + } while (temp);
4092 +
4093 + temp = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
4094 + *value = PRCMPM_PWSTST_IVA2PowerStateStGet32(temp);
4095 + break;
4096 +
4097 + default:
4098 + status = RET_FAIL;
4099 + break;
4100 + }
4101 + return status;
4102 +}
4103 +
4104 +HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
4105 +{
4106 + HW_STATUS status = RET_OK;
4107 +
4108 + *value = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
4109 +
4110 + return status;
4111 +}
4112 +
4113 +
4114 +HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
4115 + enum HW_PwrModule_t p,
4116 + enum HW_PwrState_t value)
4117 +{
4118 + HW_STATUS status = RET_OK;
4119 +
4120 + switch (p) {
4121 + case HW_PWR_DOMAIN_DSP:
4122 + switch (value) {
4123 + case HW_PWR_STATE_ON:
4124 + PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress);
4125 + break;
4126 + case HW_PWR_STATE_RET:
4127 + PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress);
4128 + break;
4129 + case HW_PWR_STATE_OFF:
4130 + PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress);
4131 + break;
4132 + default:
4133 + status = RET_FAIL;
4134 + break;
4135 + }
4136 + break;
4137 +
4138 + default:
4139 + status = RET_FAIL;
4140 + break;
4141 + }
4142 +
4143 + return status;
4144 +}
4145 +
4146 +HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
4147 + enum HW_TransitionState_t val)
4148 +{
4149 + HW_STATUS status = RET_OK;
4150 +
4151 + PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, val);
4152 +
4153 + return status;
4154 +
4155 +}
4156 +
4157 +HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
4158 + u32 *value)
4159 +{
4160 + HW_STATUS status = RET_OK;
4161 +
4162 + *value = PRCMRM_RSTST_DSPReadRegister32(baseAddress);
4163 +
4164 + return status;
4165 +}
4166 +
4167 +HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
4168 + u32 *value)
4169 +{
4170 + HW_STATUS status = RET_OK;
4171 +
4172 + *value = PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress);
4173 +
4174 + return status;
4175 +}
4176 diff --git a/drivers/dsp/bridge/hw/hw_prcm.h b/drivers/dsp/bridge/hw/hw_prcm.h
4177 new file mode 100644
4178 index 0000000..d3aa199
4179 --- /dev/null
4180 +++ b/drivers/dsp/bridge/hw/hw_prcm.h
4181 @@ -0,0 +1,168 @@
4182 +/*
4183 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_prcm.h
4184 + *
4185 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
4186 + *
4187 + * Copyright (C) 2007 Texas Instruments, Inc.
4188 + *
4189 + * This package is free software; you can redistribute it and/or modify
4190 + * it under the terms of the GNU General Public License version 2 as
4191 + * published by the Free Software Foundation.
4192 + *
4193 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
4194 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
4195 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
4196 + */
4197 +
4198 +/*
4199 + * ======== hw_prcm.h ========
4200 + * Description:
4201 + * PRCM types and API declarations
4202 + *
4203 + *! Revision History:
4204 + *! ================
4205 + *! 16 Feb 2003 sb: Initial version
4206 + */
4207 +
4208 +#ifndef __HW_PRCM_H
4209 +#define __HW_PRCM_H
4210 +
4211 +/* HW_ClkModule: Enumerated Type used to specify the clock domain */
4212 +
4213 +enum HW_ClkModule_t {
4214 +/* DSP Domain */
4215 + HW_CLK_DSP_CPU,
4216 + HW_CLK_DSP_IPI_MMU,
4217 + HW_CLK_IVA_ARM,
4218 + HW_CLK_IVA_COP, /* IVA Coprocessor */
4219 +
4220 +/* Core Domain */
4221 + HW_CLK_FN_WDT4, /* Functional Clock */
4222 + HW_CLK_FN_WDT3,
4223 + HW_CLK_FN_UART2,
4224 + HW_CLK_FN_UART1,
4225 + HW_CLK_GPT5,
4226 + HW_CLK_GPT6,
4227 + HW_CLK_GPT7,
4228 + HW_CLK_GPT8,
4229 +
4230 + HW_CLK_IF_WDT4, /* Interface Clock */
4231 + HW_CLK_IF_WDT3,
4232 + HW_CLK_IF_UART2,
4233 + HW_CLK_IF_UART1,
4234 + HW_CLK_IF_MBOX
4235 +
4236 +} ;
4237 +
4238 +enum HW_ClkSubsys_t {
4239 + HW_CLK_DSPSS,
4240 + HW_CLK_IVASS
4241 +} ;
4242 +
4243 +/* HW_GPtimers: General purpose timers */
4244 +enum HW_GPtimer_t {
4245 + HW_GPT5 = 5,
4246 + HW_GPT6 = 6,
4247 + HW_GPT7 = 7,
4248 + HW_GPT8 = 8
4249 +} ;
4250 +
4251 +
4252 +/* GP timers Input clock type: General purpose timers */
4253 +enum HW_Clocktype_t {
4254 + HW_CLK_32KHz = 0,
4255 + HW_CLK_SYS = 1,
4256 + HW_CLK_EXT = 2
4257 +} ;
4258 +
4259 +/* HW_ClkDiv: Clock divisors */
4260 +enum HW_ClkDiv_t {
4261 + HW_CLK_DIV_1 = 0x1,
4262 + HW_CLK_DIV_2 = 0x2,
4263 + HW_CLK_DIV_3 = 0x3,
4264 + HW_CLK_DIV_4 = 0x4,
4265 + HW_CLK_DIV_6 = 0x6,
4266 + HW_CLK_DIV_8 = 0x8,
4267 + HW_CLK_DIV_12 = 0xC
4268 +} ;
4269 +
4270 +/* HW_RstModule: Enumerated Type used to specify the module to be reset */
4271 +enum HW_RstModule_t {
4272 + HW_RST1_IVA2, /* Reset the DSP */
4273 + HW_RST2_IVA2, /* Reset MMU and LEON HWa */
4274 + HW_RST3_IVA2 /* Reset LEON sequencer */
4275 +} ;
4276 +
4277 +/* HW_PwrModule: Enumerated Type used to specify the power domain */
4278 +enum HW_PwrModule_t {
4279 +/* Domains */
4280 + HW_PWR_DOMAIN_CORE,
4281 + HW_PWR_DOMAIN_MPU,
4282 + HW_PWR_DOMAIN_WAKEUP,
4283 + HW_PWR_DOMAIN_DSP,
4284 +
4285 +/* Sub-domains */
4286 + HW_PWR_DSP_IPI, /* IPI = Intrusive Port Interface */
4287 + HW_PWR_IVA_ISP /* ISP = Intrusive Slave Port */
4288 +} ;
4289 +
4290 +enum HW_PwrState_t {
4291 + HW_PWR_STATE_OFF,
4292 + HW_PWR_STATE_RET,
4293 + HW_PWR_STATE_INACT,
4294 + HW_PWR_STATE_ON = 3
4295 +} ;
4296 +
4297 +enum HW_ForceState_t {
4298 + HW_FORCE_OFF,
4299 + HW_FORCE_ON
4300 +} ;
4301 +
4302 +enum HW_IdleState_t {
4303 + HW_ACTIVE,
4304 + HW_STANDBY
4305 +
4306 +} ;
4307 +
4308 +enum HW_TransitionState_t {
4309 + HW_AUTOTRANS_DIS,
4310 + HW_SW_SUP_SLEEP,
4311 + HW_SW_SUP_WAKEUP,
4312 + HW_AUTOTRANS_EN
4313 +} ;
4314 +
4315 +
4316 +extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
4317 + enum HW_RstModule_t r);
4318 +
4319 +extern HW_STATUS HW_RST_UnReset(const u32 baseAddress,
4320 + enum HW_RstModule_t r);
4321 +
4322 +extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress,
4323 + enum HW_RstModule_t p,
4324 + u32 *value);
4325 +extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress,
4326 + enum HW_RstModule_t p, u32 *value);
4327 +
4328 +extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
4329 + enum HW_PwrModule_t p,
4330 + enum HW_PwrState_t value);
4331 +
4332 +extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
4333 + enum HW_GPtimer_t gpt,
4334 + enum HW_Clocktype_t c);
4335 +
4336 +extern HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress,
4337 + enum HW_PwrModule_t p,
4338 + enum HW_PwrState_t *value);
4339 +
4340 +extern HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value);
4341 +
4342 +extern HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
4343 + enum HW_PwrModule_t p,
4344 + enum HW_PwrState_t value);
4345 +
4346 +extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
4347 + enum HW_TransitionState_t val);
4348 +
4349 +#endif /* __HW_PRCM_H */
4350 --
4351 1.5.5.1.357.g1af8b