| blob | 4b77f577689f707aac8af505c52e02f320e2d2af |
1 Patch borrowed from OpenEmbedded, available at
2 /meta/recipes-extended/libaio/libaio/00_arches.patch in their source
3 tree. This patch has been modified to only add the MIPS definitions.
5 The patch adds MIPS specific definitions (syscall number and macros).
7 Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
9 Index: libaio-0.3.110/src/syscall.h
10 ===================================================================
11 --- libaio-0.3.110.orig/src/syscall.h
12 +++ libaio-0.3.110/src/syscall.h
13 @@ -28,6 +28,8 @@
14 #include "syscall-sparc.h"
15 #elif defined(__aarch64__)
16 #include "syscall-arm64.h"
17 +#elif defined(__mips__)
18 +#include "syscall-mips.h"
19 #else
20 #warning "using generic syscall method"
21 #include "syscall-generic.h"
22 Index: libaio-0.3.110/src/syscall-mips.h
23 ===================================================================
24 --- /dev/null
25 +++ libaio-0.3.110/src/syscall-mips.h
26 @@ -0,0 +1,223 @@
27 +/*
28 + * This file is subject to the terms and conditions of the GNU General Public
29 + * License. See the file "COPYING" in the main directory of this archive
30 + * for more details.
31 + *
32 + * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
33 + * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
34 + *
35 + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
36 + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
37 + */
38 +
39 +#ifndef _MIPS_SIM_ABI32
40 +#define _MIPS_SIM_ABI32 1
41 +#define _MIPS_SIM_NABI32 2
42 +#define _MIPS_SIM_ABI64 3
43 +#endif
44 +
45 +#if _MIPS_SIM == _MIPS_SIM_ABI32
46 +
47 +/*
48 + * Linux o32 style syscalls are in the range from 4000 to 4999.
49 + */
50 +#define __NR_Linux 4000
51 +#define __NR_io_setup (__NR_Linux + 241)
52 +#define __NR_io_destroy (__NR_Linux + 242)
53 +#define __NR_io_getevents (__NR_Linux + 243)
54 +#define __NR_io_submit (__NR_Linux + 244)
55 +#define __NR_io_cancel (__NR_Linux + 245)
56 +
57 +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
58 +
59 +#if _MIPS_SIM == _MIPS_SIM_ABI64
60 +
61 +/*
62 + * Linux 64-bit syscalls are in the range from 5000 to 5999.
63 + */
64 +#define __NR_Linux 5000
65 +#define __NR_io_setup (__NR_Linux + 200)
66 +#define __NR_io_destroy (__NR_Linux + 201)
67 +#define __NR_io_getevents (__NR_Linux + 202)
68 +#define __NR_io_submit (__NR_Linux + 203)
69 +#define __NR_io_cancel (__NR_Linux + 204)
70 +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
71 +
72 +#if _MIPS_SIM == _MIPS_SIM_NABI32
73 +
74 +/*
75 + * Linux N32 syscalls are in the range from 6000 to 6999.
76 + */
77 +#define __NR_Linux 6000
78 +#define __NR_io_setup (__NR_Linux + 200)
79 +#define __NR_io_destroy (__NR_Linux + 201)
80 +#define __NR_io_getevents (__NR_Linux + 202)
81 +#define __NR_io_submit (__NR_Linux + 203)
82 +#define __NR_io_cancel (__NR_Linux + 204)
83 +#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
84 +
85 +#define io_syscall1(type,fname,sname,atype,a) \
86 +type fname(atype a) \
87 +{ \
88 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
89 + register unsigned long __a3 asm("$7"); \
90 + unsigned long __v0; \
91 + \
92 + __asm__ volatile ( \
93 + ".set\tnoreorder\n\t" \
94 + "li\t$2, %3\t\t\t# " #fname "\n\t" \
95 + "syscall\n\t" \
96 + "move\t%0, $2\n\t" \
97 + ".set\treorder" \
98 + : "=&r" (__v0), "=r" (__a3) \
99 + : "r" (__a0), "i" (__NR_##sname) \
100 + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
101 + "memory"); \
102 + \
103 + if (__a3 == 0) \
104 + return (type) __v0; \
105 + return (type) -1; \
106 +}
107 +
108 +#define io_syscall2(type,fname,sname,atype,a,btype,b) \
109 +type fname(atype a, btype b) \
110 +{ \
111 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
112 + register unsigned long __a1 asm("$5") = (unsigned long) b; \
113 + register unsigned long __a3 asm("$7"); \
114 + unsigned long __v0; \
115 + \
116 + __asm__ volatile ( \
117 + ".set\tnoreorder\n\t" \
118 + "li\t$2, %4\t\t\t# " #fname "\n\t" \
119 + "syscall\n\t" \
120 + "move\t%0, $2\n\t" \
121 + ".set\treorder" \
122 + : "=&r" (__v0), "=r" (__a3) \
123 + : "r" (__a0), "r" (__a1), "i" (__NR_##sname) \
124 + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
125 + "memory"); \
126 + \
127 + if (__a3 == 0) \
128 + return (type) __v0; \
129 + return (type) -1; \
130 +}
131 +
132 +#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
133 +type fname(atype a, btype b, ctype c) \
134 +{ \
135 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
136 + register unsigned long __a1 asm("$5") = (unsigned long) b; \
137 + register unsigned long __a2 asm("$6") = (unsigned long) c; \
138 + register unsigned long __a3 asm("$7"); \
139 + unsigned long __v0; \
140 + \
141 + __asm__ volatile ( \
142 + ".set\tnoreorder\n\t" \
143 + "li\t$2, %5\t\t\t# " #fname "\n\t" \
144 + "syscall\n\t" \
145 + "move\t%0, $2\n\t" \
146 + ".set\treorder" \
147 + : "=&r" (__v0), "=r" (__a3) \
148 + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
149 + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
150 + "memory"); \
151 + \
152 + if (__a3 == 0) \
153 + return (type) __v0; \
154 + return (type) -1; \
155 +}
156 +
157 +#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
158 +type fname(atype a, btype b, ctype c, dtype d) \
159 +{ \
160 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
161 + register unsigned long __a1 asm("$5") = (unsigned long) b; \
162 + register unsigned long __a2 asm("$6") = (unsigned long) c; \
163 + register unsigned long __a3 asm("$7") = (unsigned long) d; \
164 + unsigned long __v0; \
165 + \
166 + __asm__ volatile ( \
167 + ".set\tnoreorder\n\t" \
168 + "li\t$2, %5\t\t\t# " #fname "\n\t" \
169 + "syscall\n\t" \
170 + "move\t%0, $2\n\t" \
171 + ".set\treorder" \
172 + : "=&r" (__v0), "+r" (__a3) \
173 + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
174 + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
175 + "memory"); \
176 + \
177 + if (__a3 == 0) \
178 + return (type) __v0; \
179 + return (type) -1; \
180 +}
181 +
182 +#if (_MIPS_SIM == _MIPS_SIM_ABI32)
183 +
184 +/*
185 + * Using those means your brain needs more than an oil change ;-)
186 + */
187 +
188 +#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
189 +type fname(atype a, btype b, ctype c, dtype d, etype e) \
190 +{ \
191 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
192 + register unsigned long __a1 asm("$5") = (unsigned long) b; \
193 + register unsigned long __a2 asm("$6") = (unsigned long) c; \
194 + register unsigned long __a3 asm("$7") = (unsigned long) d; \
195 + unsigned long __v0; \
196 + \
197 + __asm__ volatile ( \
198 + ".set\tnoreorder\n\t" \
199 + "lw\t$2, %6\n\t" \
200 + "subu\t$29, 32\n\t" \
201 + "sw\t$2, 16($29)\n\t" \
202 + "li\t$2, %5\t\t\t# " #fname "\n\t" \
203 + "syscall\n\t" \
204 + "move\t%0, $2\n\t" \
205 + "addiu\t$29, 32\n\t" \
206 + ".set\treorder" \
207 + : "=&r" (__v0), "+r" (__a3) \
208 + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname), \
209 + "m" ((unsigned long)e) \
210 + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
211 + "memory"); \
212 + \
213 + if (__a3 == 0) \
214 + return (type) __v0; \
215 + return (type) -1; \
216 +}
217 +
218 +#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
219 +
220 +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
221 +
222 +#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
223 +type fname (atype a,btype b,ctype c,dtype d,etype e) \
224 +{ \
225 + register unsigned long __a0 asm("$4") = (unsigned long) a; \
226 + register unsigned long __a1 asm("$5") = (unsigned long) b; \
227 + register unsigned long __a2 asm("$6") = (unsigned long) c; \
228 + register unsigned long __a3 asm("$7") = (unsigned long) d; \
229 + register unsigned long __a4 asm("$8") = (unsigned long) e; \
230 + unsigned long __v0; \
231 + \
232 + __asm__ volatile ( \
233 + ".set\tnoreorder\n\t" \
234 + "li\t$2, %6\t\t\t# " #fname "\n\t" \
235 + "syscall\n\t" \
236 + "move\t%0, $2\n\t" \
237 + ".set\treorder" \
238 + : "=&r" (__v0), "+r" (__a3) \
239 + : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##sname) \
240 + : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
241 + "memory"); \
242 + \
243 + if (__a3 == 0) \
244 + return (type) __v0; \
245 + return (type) -1; \
246 +}
247 +
248 +#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
249 +