| blob | 8ffedd9febc27d93648e14110fee7986498b696e |
1 /*
2 * Device Tree Generator version: 1.3
3 *
4 * (C) Copyright 2007-2008 Xilinx, Inc.
5 * (C) Copyright 2007-2009 Michal Simek
6 *
7 * Michal SIMEK <monstr@monstr.eu>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * CAUTION: This file is automatically generated by libgen.
25 * Version: Xilinx EDK 13.2 EDK_O.61xd
26 *
27 * XPS project directory: device-tree_bsp_230-orig
28 */
30 /dts-v1/;
31 / {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "xlnx,microblaze";
35 model = "testing";
36 MCB3_LPDDR: memory@80000000 {
37 device_type = "memory";
38 reg = < 0x80000000 0x4000000 >;
39 } ;
40 aliases {
41 ethernet0 = &Ethernet_MAC;
42 serial0 = &USB_Uart;
43 } ;
44 chosen {
45 bootargs = "console=ttyUL0";
46 linux,stdout-path = "/axi@0/serial@40600000";
47 } ;
48 cpus {
49 #address-cells = <1>;
50 #cpus = <0x1>;
51 #size-cells = <0>;
52 microblaze_0: cpu@0 {
53 clock-frequency = <66666667>;
54 compatible = "xlnx,microblaze-8.20.a";
55 d-cache-baseaddr = <0x80000000>;
56 d-cache-highaddr = <0x83ffffff>;
57 d-cache-line-size = <0x10>;
58 d-cache-size = <0x2000>;
59 device_type = "cpu";
60 i-cache-baseaddr = <0x80000000>;
61 i-cache-highaddr = <0x83ffffff>;
62 i-cache-line-size = <0x10>;
63 i-cache-size = <0x2000>;
64 model = "microblaze,8.20.a";
65 reg = <0>;
66 timebase-frequency = <66666667>;
67 xlnx,addr-tag-bits = <0xd>;
68 xlnx,allow-dcache-wr = <0x1>;
69 xlnx,allow-icache-wr = <0x1>;
70 xlnx,area-optimized = <0x0>;
71 xlnx,avoid-primitives = <0x0>;
72 xlnx,branch-target-cache-size = <0x0>;
73 xlnx,cache-byte-size = <0x2000>;
74 xlnx,d-axi = <0x1>;
75 xlnx,d-lmb = <0x1>;
76 xlnx,d-plb = <0x0>;
77 xlnx,data-size = <0x20>;
78 xlnx,dcache-addr-tag = <0xd>;
79 xlnx,dcache-always-used = <0x1>;
80 xlnx,dcache-byte-size = <0x2000>;
81 xlnx,dcache-data-width = <0x0>;
82 xlnx,dcache-force-tag-lutram = <0x0>;
83 xlnx,dcache-interface = <0x0>;
84 xlnx,dcache-line-len = <0x4>;
85 xlnx,dcache-use-fsl = <0x0>;
86 xlnx,dcache-use-writeback = <0x0>;
87 xlnx,dcache-victims = <0x0>;
88 xlnx,debug-enabled = <0x1>;
89 xlnx,div-zero-exception = <0x0>;
90 xlnx,dynamic-bus-sizing = <0x1>;
91 xlnx,ecc-use-ce-exception = <0x0>;
92 xlnx,edge-is-positive = <0x1>;
93 xlnx,endianness = <0x1>;
94 xlnx,family = "spartan6";
95 xlnx,fault-tolerant = <0x0>;
96 xlnx,fpu-exception = <0x0>;
97 xlnx,freq = <0x3f940ab>;
98 xlnx,fsl-data-size = <0x20>;
99 xlnx,fsl-exception = <0x0>;
100 xlnx,fsl-links = <0x0>;
101 xlnx,i-axi = <0x0>;
102 xlnx,i-lmb = <0x1>;
103 xlnx,i-plb = <0x0>;
104 xlnx,icache-always-used = <0x1>;
105 xlnx,icache-data-width = <0x0>;
106 xlnx,icache-force-tag-lutram = <0x0>;
107 xlnx,icache-interface = <0x0>;
108 xlnx,icache-line-len = <0x4>;
109 xlnx,icache-streams = <0x0>;
110 xlnx,icache-use-fsl = <0x0>;
111 xlnx,icache-victims = <0x0>;
112 xlnx,ill-opcode-exception = <0x0>;
113 xlnx,instance = "microblaze_0";
114 xlnx,interconnect = <0x2>;
115 xlnx,interconnect-m-axi-dc-aw-register = <0x0>;
116 xlnx,interconnect-m-axi-dc-read-issuing = <0x2>;
117 xlnx,interconnect-m-axi-dc-w-register = <0x0>;
118 xlnx,interconnect-m-axi-dc-write-issuing = <0x20>;
119 xlnx,interconnect-m-axi-dp-read-issuing = <0x1>;
120 xlnx,interconnect-m-axi-dp-write-issuing = <0x1>;
121 xlnx,interconnect-m-axi-ic-read-issuing = <0x2>;
122 xlnx,interconnect-m-axi-ip-read-issuing = <0x1>;
123 xlnx,interrupt-is-edge = <0x0>;
124 xlnx,lockstep-slave = <0x0>;
125 xlnx,mmu-dtlb-size = <0x1>;
126 xlnx,mmu-itlb-size = <0x1>;
127 xlnx,mmu-privileged-instr = <0x0>;
128 xlnx,mmu-tlb-access = <0x3>;
129 xlnx,mmu-zones = <0x2>;
130 xlnx,number-of-pc-brk = <0x1>;
131 xlnx,number-of-rd-addr-brk = <0x0>;
132 xlnx,number-of-wr-addr-brk = <0x0>;
133 xlnx,opcode-0x0-illegal = <0x0>;
134 xlnx,optimization = <0x0>;
135 xlnx,pvr = <0x0>;
136 xlnx,pvr-user1 = <0x0>;
137 xlnx,pvr-user2 = <0x0>;
138 xlnx,reset-msr = <0x0>;
139 xlnx,sco = <0x0>;
140 xlnx,stream-interconnect = <0x0>;
141 xlnx,unaligned-exceptions = <0x0>;
142 xlnx,use-barrel = <0x1>;
143 xlnx,use-branch-target-cache = <0x0>;
144 xlnx,use-dcache = <0x1>;
145 xlnx,use-div = <0x0>;
146 xlnx,use-ext-brk = <0x1>;
147 xlnx,use-ext-nm-brk = <0x1>;
148 xlnx,use-extended-fsl-instr = <0x0>;
149 xlnx,use-fpu = <0x0>;
150 xlnx,use-hw-mul = <0x1>;
151 xlnx,use-icache = <0x1>;
152 xlnx,use-interrupt = <0x1>;
153 xlnx,use-mmu = <0x3>;
154 xlnx,use-msr-instr = <0x1>;
155 xlnx,use-pcmp-instr = <0x0>;
156 xlnx,use-stack-protection = <0x0>;
157 } ;
158 } ;
159 axi4lite_0: axi@0 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "xlnx,axi-interconnect-1.03.a", "simple-bus";
163 ranges ;
164 Ethernet_MAC: ethernet@40e00000 {
165 compatible = "xlnx,axi-ethernetlite-1.00.a", "xlnx,xps-ethernetlite-1.00.a";
166 device_type = "network";
167 interrupt-parent = <µblaze_0_intc>;
168 interrupts = < 2 0 >;
169 local-mac-address = [ 00 0a 35 aa de 00 ];
170 // phy-handle = <&phy0>;
171 reg = < 0x40e00000 0x10000 >;
172 xlnx,duplex = <0x1>;
173 xlnx,family = "spartan6";
174 xlnx,include-global-buffers = <0x0>;
175 xlnx,include-internal-loopback = <0x0>;
176 xlnx,include-mdio = <0x1>;
177 xlnx,include-phy-constraints = <0x1>;
178 xlnx,interconnect-s-axi-read-acceptance = <0x1>;
179 xlnx,interconnect-s-axi-write-acceptance = <0x1>;
180 xlnx,rx-ping-pong = <0x0>;
181 xlnx,s-axi-aclk-period-ps = <0x3a98>;
182 xlnx,s-axi-id-width = <0x1>;
183 xlnx,s-axi-supports-narrow-burst = <0x0>;
184 xlnx,tx-ping-pong = <0x0>;
185 /*
186 mdio {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 phy0: phy@7 {
190 compatible = "marvell,88e1111";
191 device_type = "ethernet-phy";
192 reg = <7>;
193 } ;
194 } ;
195 */
196 } ;
197 SPI_FLASH: spi@40a00000 {
198 compatible = "xlnx,axi-spi-1.01.a", "xlnx,xps-spi-2.00.a";
199 interrupt-parent = <µblaze_0_intc>;
200 interrupts = < 1 2 >;
201 reg = < 0x40a00000 0x10000 >;
202 xlnx,family = "spartan6";
203 xlnx,fifo-exist = <0x1>;
204 xlnx,num-ss-bits = <0x1>;
205 xlnx,num-transfer-bits = <0x8>;
206 xlnx,sck-ratio = <0x4>;
207 } ;
208 USB_Uart: serial@40600000 {
209 clock-frequency = <66666667>;
210 compatible = "xlnx,axi-uartlite-1.02.a", "xlnx,xps-uartlite-1.00.a";
211 current-speed = <115200>;
212 device_type = "serial";
213 interrupt-parent = <µblaze_0_intc>;
214 interrupts = < 3 0 >;
215 port-number = <0>;
216 reg = < 0x40600000 0x10000 >;
217 xlnx,baudrate = <0x1c200>;
218 xlnx,data-bits = <0x8>;
219 xlnx,family = "spartan6";
220 xlnx,odd-parity = <0x1>;
221 xlnx,s-axi-aclk-freq-hz = <0x3f940ab>;
222 xlnx,use-parity = <0x0>;
223 } ;
224 microblaze_0_intc: interrupt-controller@41200000 {
225 #interrupt-cells = <0x2>;
226 compatible = "xlnx,axi-intc-1.01.a", "xlnx,xps-intc-1.00.a";
227 interrupt-controller ;
228 reg = < 0x41200000 0x10000 >;
229 xlnx,kind-of-intr = <0xc>;
230 xlnx,num-intr-inputs = <0x4>;
231 } ;
232 system_timer: timer@41c00000 {
233 clock-frequency = <66666667>;
234 compatible = "xlnx,axi-timer-1.02.a", "xlnx,xps-timer-1.00.a";
235 interrupt-parent = <µblaze_0_intc>;
236 interrupts = < 0 2 >;
237 reg = < 0x41c00000 0x10000 >;
238 xlnx,count-width = <0x20>;
239 xlnx,family = "spartan6";
240 xlnx,gen0-assert = <0x1>;
241 xlnx,gen1-assert = <0x1>;
242 xlnx,one-timer-only = <0x0>;
243 xlnx,trig0-assert = <0x1>;
244 xlnx,trig1-assert = <0x1>;
245 } ;
246 } ;
247 } ;