sysvinit: adjust help text
[buildroot-gz.git] / arch / Config.in.x86
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1 # i386/x86_64 cpu features
2 config BR2_X86_CPU_HAS_MMX
3 bool
4 config BR2_X86_CPU_HAS_SSE
5 bool
6 config BR2_X86_CPU_HAS_SSE2
7 bool
8 config BR2_X86_CPU_HAS_SSE3
9 bool
10 config BR2_X86_CPU_HAS_SSSE3
11 bool
12 config BR2_X86_CPU_HAS_SSE4
13 bool
14 config BR2_X86_CPU_HAS_SSE42
15 bool
16 config BR2_X86_CPU_HAS_AVX
17 bool
18 config BR2_X86_CPU_HAS_AVX2
19 bool
21 choice
22 prompt "Target Architecture Variant"
23 depends on BR2_i386 || BR2_x86_64
24 default BR2_x86_i586 if BR2_i386
25 help
26 Specific CPU variant to use
28 config BR2_x86_i486
29 bool "i486"
30 depends on !BR2_x86_64
31 config BR2_x86_i586
32 bool "i586"
33 depends on !BR2_x86_64
34 config BR2_x86_x1000
35 bool "x1000"
36 depends on !BR2_x86_64
37 help
38 The Intel X1000 is a Pentium class microprocessor in the
39 Quark (sub-Atom) Product Line. The X1000 has a bug on the
40 lock prefix requiring that prefix must be stripped at build
41 time.
43 See https://en.wikipedia.org/wiki/Intel_Quark
45 config BR2_x86_i686
46 bool "i686"
47 depends on !BR2_x86_64
48 config BR2_x86_pentiumpro
49 bool "pentium pro"
50 depends on !BR2_x86_64
51 config BR2_x86_pentium_mmx
52 bool "pentium MMX"
53 select BR2_X86_CPU_HAS_MMX
54 depends on !BR2_x86_64
55 config BR2_x86_pentium_m
56 bool "pentium mobile"
57 select BR2_X86_CPU_HAS_MMX
58 select BR2_X86_CPU_HAS_SSE
59 depends on !BR2_x86_64
60 config BR2_x86_pentium2
61 bool "pentium2"
62 select BR2_X86_CPU_HAS_MMX
63 depends on !BR2_x86_64
64 config BR2_x86_pentium3
65 bool "pentium3"
66 select BR2_X86_CPU_HAS_MMX
67 select BR2_X86_CPU_HAS_SSE
68 depends on !BR2_x86_64
69 config BR2_x86_pentium4
70 bool "pentium4"
71 select BR2_X86_CPU_HAS_MMX
72 select BR2_X86_CPU_HAS_SSE
73 select BR2_X86_CPU_HAS_SSE2
74 depends on !BR2_x86_64
75 config BR2_x86_prescott
76 bool "prescott"
77 select BR2_X86_CPU_HAS_MMX
78 select BR2_X86_CPU_HAS_SSE
79 select BR2_X86_CPU_HAS_SSE2
80 select BR2_X86_CPU_HAS_SSE3
81 depends on !BR2_x86_64
82 config BR2_x86_nocona
83 bool "nocona"
84 select BR2_X86_CPU_HAS_MMX
85 select BR2_X86_CPU_HAS_SSE
86 select BR2_X86_CPU_HAS_SSE2
87 select BR2_X86_CPU_HAS_SSE3
88 config BR2_x86_core2
89 bool "core2"
90 select BR2_X86_CPU_HAS_MMX
91 select BR2_X86_CPU_HAS_SSE
92 select BR2_X86_CPU_HAS_SSE2
93 select BR2_X86_CPU_HAS_SSE3
94 select BR2_X86_CPU_HAS_SSSE3
95 config BR2_x86_corei7
96 bool "corei7"
97 select BR2_X86_CPU_HAS_MMX
98 select BR2_X86_CPU_HAS_SSE
99 select BR2_X86_CPU_HAS_SSE2
100 select BR2_X86_CPU_HAS_SSE3
101 select BR2_X86_CPU_HAS_SSSE3
102 select BR2_X86_CPU_HAS_SSE4
103 select BR2_X86_CPU_HAS_SSE42
104 config BR2_x86_corei7_avx
105 bool "corei7-avx"
106 select BR2_X86_CPU_HAS_MMX
107 select BR2_X86_CPU_HAS_SSE
108 select BR2_X86_CPU_HAS_SSE2
109 select BR2_X86_CPU_HAS_SSE3
110 select BR2_X86_CPU_HAS_SSSE3
111 select BR2_X86_CPU_HAS_SSE4
112 select BR2_X86_CPU_HAS_SSE42
113 select BR2_X86_CPU_HAS_AVX
114 config BR2_x86_core_avx2
115 bool "core-avx2"
116 select BR2_X86_CPU_HAS_MMX
117 select BR2_X86_CPU_HAS_SSE
118 select BR2_X86_CPU_HAS_SSE2
119 select BR2_X86_CPU_HAS_SSE3
120 select BR2_X86_CPU_HAS_SSSE3
121 select BR2_X86_CPU_HAS_SSE4
122 select BR2_X86_CPU_HAS_SSE42
123 select BR2_X86_CPU_HAS_AVX
124 select BR2_X86_CPU_HAS_AVX2
125 config BR2_x86_atom
126 bool "atom"
127 select BR2_X86_CPU_HAS_MMX
128 select BR2_X86_CPU_HAS_SSE
129 select BR2_X86_CPU_HAS_SSE2
130 select BR2_X86_CPU_HAS_SSE3
131 select BR2_X86_CPU_HAS_SSSE3
132 config BR2_x86_k6
133 bool "k6"
134 select BR2_X86_CPU_HAS_MMX
135 depends on !BR2_x86_64
136 config BR2_x86_k6_2
137 bool "k6-2"
138 select BR2_X86_CPU_HAS_MMX
139 depends on !BR2_x86_64
140 config BR2_x86_athlon
141 bool "athlon"
142 select BR2_X86_CPU_HAS_MMX
143 depends on !BR2_x86_64
144 config BR2_x86_athlon_4
145 bool "athlon-4"
146 select BR2_X86_CPU_HAS_MMX
147 select BR2_X86_CPU_HAS_SSE
148 depends on !BR2_x86_64
149 config BR2_x86_opteron
150 bool "opteron"
151 select BR2_X86_CPU_HAS_MMX
152 select BR2_X86_CPU_HAS_SSE
153 select BR2_X86_CPU_HAS_SSE2
154 config BR2_x86_opteron_sse3
155 bool "opteron w/ SSE3"
156 select BR2_X86_CPU_HAS_MMX
157 select BR2_X86_CPU_HAS_SSE
158 select BR2_X86_CPU_HAS_SSE2
159 select BR2_X86_CPU_HAS_SSE3
160 config BR2_x86_barcelona
161 bool "barcelona"
162 select BR2_X86_CPU_HAS_MMX
163 select BR2_X86_CPU_HAS_SSE
164 select BR2_X86_CPU_HAS_SSE2
165 select BR2_X86_CPU_HAS_SSE3
166 config BR2_x86_jaguar
167 bool "jaguar"
168 select BR2_X86_CPU_HAS_MMX
169 select BR2_X86_CPU_HAS_SSE
170 select BR2_X86_CPU_HAS_SSE2
171 select BR2_X86_CPU_HAS_SSE3
172 select BR2_X86_CPU_HAS_SSSE3
173 select BR2_X86_CPU_HAS_SSE4
174 select BR2_X86_CPU_HAS_SSE42
175 config BR2_x86_steamroller
176 bool "steamroller"
177 select BR2_X86_CPU_HAS_MMX
178 select BR2_X86_CPU_HAS_SSE
179 select BR2_X86_CPU_HAS_SSE2
180 select BR2_X86_CPU_HAS_SSE3
181 select BR2_X86_CPU_HAS_SSSE3
182 select BR2_X86_CPU_HAS_SSE4
183 select BR2_X86_CPU_HAS_SSE42
184 config BR2_x86_geode
185 bool "geode"
186 # Don't include MMX support because there several variant of geode
187 # processor, some with MMX support, some without.
188 # See: http://en.wikipedia.org/wiki/Geode_%28processor%29
189 depends on !BR2_x86_64
190 config BR2_x86_c3
191 bool "Via/Cyrix C3 (Samuel/Ezra cores)"
192 select BR2_X86_CPU_HAS_MMX
193 depends on !BR2_x86_64
194 config BR2_x86_c32
195 bool "Via C3-2 (Nehemiah cores)"
196 select BR2_X86_CPU_HAS_MMX
197 select BR2_X86_CPU_HAS_SSE
198 depends on !BR2_x86_64
199 config BR2_x86_winchip_c6
200 bool "IDT Winchip C6"
201 select BR2_X86_CPU_HAS_MMX
202 depends on !BR2_x86_64
203 config BR2_x86_winchip2
204 bool "IDT Winchip 2"
205 select BR2_X86_CPU_HAS_MMX
206 depends on !BR2_x86_64
207 endchoice
209 config BR2_ARCH
210 default "i486" if BR2_x86_i486
211 default "i586" if BR2_x86_i586
212 default "i586" if BR2_x86_x1000
213 default "i586" if BR2_x86_pentium_mmx
214 default "i586" if BR2_x86_geode
215 default "i586" if BR2_x86_c3
216 default "i686" if BR2_x86_c32
217 default "i586" if BR2_x86_winchip_c6
218 default "i586" if BR2_x86_winchip2
219 default "i686" if BR2_x86_i686
220 default "i686" if BR2_x86_pentium2
221 default "i686" if BR2_x86_pentium3
222 default "i686" if BR2_x86_pentium4
223 default "i686" if BR2_x86_pentium_m
224 default "i686" if BR2_x86_pentiumpro
225 default "i686" if BR2_x86_prescott
226 default "i686" if BR2_x86_nocona && BR2_i386
227 default "i686" if BR2_x86_core2 && BR2_i386
228 default "i686" if BR2_x86_corei7 && BR2_i386
229 default "i686" if BR2_x86_corei7_avx && BR2_i386
230 default "i686" if BR2_x86_corei7_avx2 && BR2_i386
231 default "i686" if BR2_x86_atom && BR2_i386
232 default "i686" if BR2_x86_opteron && BR2_i386
233 default "i686" if BR2_x86_opteron_sse3 && BR2_i386
234 default "i686" if BR2_x86_barcelona && BR2_i386
235 default "i686" if BR2_x86_jaguar && BR2_i386
236 default "i686" if BR2_x86_steamroller && BR2_i386
237 default "i686" if BR2_x86_k6
238 default "i686" if BR2_x86_k6_2
239 default "i686" if BR2_x86_athlon
240 default "i686" if BR2_x86_athlon_4
241 default "x86_64" if BR2_x86_64
243 config BR2_ENDIAN
244 default "LITTLE"
246 config BR2_GCC_TARGET_ARCH
247 default "i486" if BR2_x86_i486
248 default "i586" if BR2_x86_i586
249 default "i586" if BR2_x86_x1000
250 default "pentium-mmx" if BR2_x86_pentium_mmx
251 default "i686" if BR2_x86_i686
252 default "pentiumpro" if BR2_x86_pentiumpro
253 default "pentium-m" if BR2_x86_pentium_m
254 default "pentium2" if BR2_x86_pentium2
255 default "pentium3" if BR2_x86_pentium3
256 default "pentium4" if BR2_x86_pentium4
257 default "prescott" if BR2_x86_prescott
258 default "nocona" if BR2_x86_nocona
259 default "core2" if BR2_x86_core2
260 default "corei7" if BR2_x86_corei7
261 default "corei7-avx" if BR2_x86_corei7_avx
262 default "core-avx2" if BR2_x86_core_avx2
263 default "atom" if BR2_x86_atom
264 default "k8" if BR2_x86_opteron
265 default "k8-sse3" if BR2_x86_opteron_sse3
266 default "barcelona" if BR2_x86_barcelona
267 default "btver2" if BR2_x86_jaguar
268 default "bdver3" if BR2_x86_steamroller
269 default "k6" if BR2_x86_k6
270 default "k6-2" if BR2_x86_k6_2
271 default "athlon" if BR2_x86_athlon
272 default "athlon-4" if BR2_x86_athlon_4
273 default "winchip-c6" if BR2_x86_winchip_c6
274 default "winchip2" if BR2_x86_winchip2
275 default "c3" if BR2_x86_c3
276 default "c3-2" if BR2_x86_c32
277 default "geode" if BR2_x86_geode