wireshark: fix inet_pton detection
[buildroot-gz.git] / arch / Config.in.arm
blobdb7b8f2cb4abdd994fa4bea2b0f7252fca0bf473
1 # arm cpu features
2 config BR2_ARM_CPU_HAS_NEON
3 bool
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
7 bool
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
11 bool
13 config BR2_ARM_CPU_HAS_VFPV2
14 bool
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
18 bool
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
22 bool
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
27 bool
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
31 bool
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
35 bool
37 config BR2_ARM_CPU_HAS_THUMB
38 bool
40 config BR2_ARM_CPU_HAS_THUMB2
41 bool
43 config BR2_ARM_CPU_ARMV4
44 bool
46 config BR2_ARM_CPU_ARMV5
47 bool
49 config BR2_ARM_CPU_ARMV6
50 bool
52 config BR2_ARM_CPU_ARMV7A
53 bool
55 choice
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
58 default BR2_arm926t
59 help
60 Specific CPU variant to use
62 config BR2_arm920t
63 bool "arm920t"
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
67 select BR2_ARCH_HAS_MMU_OPTIONAL
68 config BR2_arm922t
69 bool "arm922t"
70 select BR2_ARM_CPU_HAS_ARM
71 select BR2_ARM_CPU_HAS_THUMB
72 select BR2_ARM_CPU_ARMV4
73 select BR2_ARCH_HAS_MMU_OPTIONAL
74 config BR2_arm926t
75 bool "arm926t"
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
78 select BR2_ARM_CPU_HAS_THUMB
79 select BR2_ARM_CPU_ARMV5
80 select BR2_ARCH_HAS_MMU_OPTIONAL
81 config BR2_arm1136j_s
82 bool "arm1136j-s"
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_HAS_THUMB
85 select BR2_ARM_CPU_ARMV6
86 select BR2_ARCH_HAS_MMU_OPTIONAL
87 config BR2_arm1136jf_s
88 bool "arm1136jf-s"
89 select BR2_ARM_CPU_HAS_ARM
90 select BR2_ARM_CPU_HAS_VFPV2
91 select BR2_ARM_CPU_HAS_THUMB
92 select BR2_ARM_CPU_ARMV6
93 select BR2_ARCH_HAS_MMU_OPTIONAL
94 config BR2_arm1176jz_s
95 bool "arm1176jz-s"
96 select BR2_ARM_CPU_HAS_ARM
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 config BR2_arm1176jzf_s
101 bool "arm1176jzf-s"
102 select BR2_ARM_CPU_HAS_ARM
103 select BR2_ARM_CPU_HAS_VFPV2
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
107 config BR2_cortex_a5
108 bool "cortex-A5"
109 select BR2_ARM_CPU_HAS_ARM
110 select BR2_ARM_CPU_MAYBE_HAS_NEON
111 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
112 select BR2_ARM_CPU_HAS_THUMB2
113 select BR2_ARM_CPU_ARMV7A
114 select BR2_ARCH_HAS_MMU_OPTIONAL
115 config BR2_cortex_a7
116 bool "cortex-A7"
117 select BR2_ARM_CPU_HAS_ARM
118 select BR2_ARM_CPU_HAS_NEON
119 select BR2_ARM_CPU_HAS_VFPV4
120 select BR2_ARM_CPU_HAS_THUMB2
121 select BR2_ARM_CPU_ARMV7A
122 select BR2_ARCH_HAS_MMU_OPTIONAL
123 config BR2_cortex_a8
124 bool "cortex-A8"
125 select BR2_ARM_CPU_HAS_ARM
126 select BR2_ARM_CPU_HAS_NEON
127 select BR2_ARM_CPU_HAS_VFPV3
128 select BR2_ARM_CPU_HAS_THUMB2
129 select BR2_ARM_CPU_ARMV7A
130 select BR2_ARCH_HAS_MMU_OPTIONAL
131 config BR2_cortex_a9
132 bool "cortex-A9"
133 select BR2_ARM_CPU_HAS_ARM
134 select BR2_ARM_CPU_MAYBE_HAS_NEON
135 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
136 select BR2_ARM_CPU_HAS_THUMB2
137 select BR2_ARM_CPU_ARMV7A
138 select BR2_ARCH_HAS_MMU_OPTIONAL
139 config BR2_cortex_a12
140 bool "cortex-A12"
141 select BR2_ARM_CPU_HAS_ARM
142 select BR2_ARM_CPU_HAS_NEON
143 select BR2_ARM_CPU_HAS_VFPV4
144 select BR2_ARM_CPU_HAS_THUMB2
145 select BR2_ARM_CPU_ARMV7A
146 select BR2_ARCH_HAS_MMU_OPTIONAL
147 config BR2_cortex_a15
148 bool "cortex-A15"
149 select BR2_ARM_CPU_HAS_ARM
150 select BR2_ARM_CPU_HAS_NEON
151 select BR2_ARM_CPU_HAS_VFPV4
152 select BR2_ARM_CPU_HAS_THUMB2
153 select BR2_ARM_CPU_ARMV7A
154 select BR2_ARCH_HAS_MMU_OPTIONAL
155 config BR2_cortex_m3
156 bool "cortex-M3"
157 select BR2_ARM_CPU_HAS_THUMB
158 select BR2_ARM_CPU_HAS_THUMB2
159 config BR2_fa526
160 bool "fa526/626"
161 select BR2_ARM_CPU_HAS_ARM
162 select BR2_ARM_CPU_ARMV4
163 select BR2_ARCH_HAS_MMU_OPTIONAL
164 config BR2_pj4
165 bool "pj4"
166 select BR2_ARM_CPU_HAS_ARM
167 select BR2_ARM_CPU_HAS_VFPV3
168 select BR2_ARM_CPU_ARMV7A
169 select BR2_ARCH_HAS_MMU_OPTIONAL
170 config BR2_strongarm
171 bool "strongarm sa110/sa1100"
172 select BR2_ARM_CPU_HAS_ARM
173 select BR2_ARM_CPU_ARMV4
174 select BR2_ARCH_HAS_MMU_OPTIONAL
175 config BR2_xscale
176 bool "xscale"
177 select BR2_ARM_CPU_HAS_ARM
178 select BR2_ARM_CPU_HAS_THUMB
179 select BR2_ARM_CPU_ARMV5
180 select BR2_ARCH_HAS_MMU_OPTIONAL
181 config BR2_iwmmxt
182 bool "iwmmxt"
183 select BR2_ARM_CPU_HAS_ARM
184 select BR2_ARM_CPU_ARMV5
185 select BR2_ARCH_HAS_MMU_OPTIONAL
186 endchoice
188 choice
189 prompt "Target ABI"
190 depends on BR2_arm || BR2_armeb
191 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
192 default BR2_ARM_EABI
193 help
194 Application Binary Interface to use. The Application Binary
195 Interface describes the calling conventions (how arguments
196 are passed to functions, how the return value is passed, how
197 system calls are made, etc.).
199 config BR2_ARM_EABI
200 bool "EABI"
201 help
202 The EABI is currently the standard ARM ABI, which is used in
203 most projects. It supports both the 'soft' floating point
204 model (in which floating point instructions are emulated in
205 software) and the 'softfp' floating point model (in which
206 floating point instructions are executed using an hardware
207 floating point unit, but floating point arguments to
208 functions are passed in integer registers).
210 The 'softfp' floating point model is link-compatible with
211 the 'soft' floating point model, i.e you can link a library
212 built 'soft' with some other code built 'softfp'.
214 However, passing the floating point arguments in integer
215 registers is a bit inefficient, so if your ARM processor has
216 a floating point unit, and you don't have pre-compiled
217 'soft' or 'softfp' code, using the EABIhf ABI will provide
218 better floating point performances.
220 If your processor does not have a floating point unit, then
221 you must use this ABI.
223 config BR2_ARM_EABIHF
224 bool "EABIhf"
225 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 || BR2_ARM_CPU_HAS_VFPV2
226 help
227 The EABIhf is an extension of EABI which supports the 'hard'
228 floating point model. This model uses the floating point
229 unit to execute floating point instructions, and passes
230 floating point arguments in floating point registers.
232 It is more efficient than EABI for floating point related
233 workload. However, it does not allow to link against code
234 that has been pre-built for the 'soft' or 'softfp' floating
235 point models.
237 If your processor has a floating point unit, and you don't
238 depend on existing pre-compiled code, this option is most
239 likely the best choice.
241 endchoice
243 config BR2_ARM_ENABLE_NEON
244 bool "Enable NEON SIMD extension support"
245 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
246 select BR2_ARM_CPU_HAS_NEON
247 help
248 For some CPU cores, the NEON SIMD extension is optional.
249 Select this option if you are certain your particular
250 implementation has NEON support and you want to use it.
252 choice
253 prompt "Floating point strategy"
254 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
255 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
256 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
257 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
258 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
260 config BR2_ARM_SOFT_FLOAT
261 bool "Soft float"
262 depends on BR2_ARM_EABI
263 select BR2_SOFT_FLOAT
264 help
265 This option allows to use software emulated floating
266 point. It should be used for ARM cores that do not include a
267 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
268 example) or certain ARMv6 cores.
270 config BR2_ARM_FPU_VFPV2
271 bool "VFPv2"
272 depends on BR2_ARM_CPU_HAS_VFPV2 || BR2_ARM_CPU_MAYBE_HAS_VFPV2
273 help
274 This option allows to use the VFPv2 floating point unit, as
275 available in some ARMv5 processors (ARM926EJ-S) and some
276 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
277 MPCore).
279 Note that this option is also safe to use for newer cores
280 such as Cortex-A, because the VFPv3 and VFPv4 units are
281 backward compatible with VFPv2.
283 config BR2_ARM_FPU_VFPV3
284 bool "VFPv3"
285 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
286 help
287 This option allows to use the VFPv3 floating point unit, as
288 available in some ARMv7 processors (Cortex-A{8, 9}). This
289 option requires a VFPv3 unit that has 32 double-precision
290 registers, which is not necessarily the case in all SOCs
291 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
292 instead, which is guaranteed to work on all Cortex-A{8, 9}.
294 Note that this option is also safe to use for newer cores
295 that have a VFPv4 unit, because VFPv4 is backward compatible
296 with VFPv3. They must of course also have 32
297 double-precision registers.
299 config BR2_ARM_FPU_VFPV3D16
300 bool "VFPv3-D16"
301 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
302 help
303 This option allows to use the VFPv3 floating point unit, as
304 available in some ARMv7 processors (Cortex-A{8, 9}). This
305 option requires a VFPv3 unit that has 16 double-precision
306 registers, which is generally the case in all SOCs based on
307 Cortex-A{8, 9}, even though VFPv3 is technically optional on
308 Cortex-A9. This is the safest option for those cores.
310 Note that this option is also safe to use for newer cores
311 such that have a VFPv4 unit, because the VFPv4 is backward
312 compatible with VFPv3.
314 config BR2_ARM_FPU_VFPV4
315 bool "VFPv4"
316 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
317 help
318 This option allows to use the VFPv4 floating point unit, as
319 available in some ARMv7 processors (Cortex-A{5, 7, 12,
320 15}). This option requires a VFPv4 unit that has 32
321 double-precision registers, which is not necessarily the
322 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
323 unsure, you should probably use VFPv4-D16 instead.
325 Note that if you want binary code that works on all ARMv7
326 cores, including the earlier Cortex-A{8, 9}, you should
327 instead select VFPv3.
329 config BR2_ARM_FPU_VFPV4D16
330 bool "VFPv4-D16"
331 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
332 help
333 This option allows to use the VFPv4 floating point unit, as
334 available in some ARMv7 processors (Cortex-A{5, 7, 12,
335 15}). This option requires a VFPv4 unit that has 16
336 double-precision registers, which is always available on
337 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
338 Cortex-A7.
340 Note that if you want binary code that works on all ARMv7
341 cores, including the earlier Cortex-A{8, 9}, you should
342 instead select VFPv3-D16.
344 config BR2_ARM_FPU_NEON
345 bool "NEON"
346 depends on BR2_ARM_CPU_HAS_NEON
347 help
348 This option allows to use the NEON SIMD unit, as available
349 in some ARMv7 processors, as a floating-point unit. It
350 should however be noted that using NEON for floating point
351 operations doesn't provide a complete compatibility with the
352 IEEE 754.
354 config BR2_ARM_FPU_NEON_VFPV4
355 bool "NEON/VFPv4"
356 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
357 depends on BR2_ARM_CPU_HAS_NEON
358 help
359 This option allows to use both the VFPv4 and the NEON SIMD
360 units for floating point operations. Note that some ARMv7
361 cores do not necessarily have VFPv4 and/or NEON support, for
362 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
363 NEON is optional.
365 endchoice
367 choice
368 prompt "ARM instruction set"
370 config BR2_ARM_INSTRUCTIONS_ARM
371 bool "ARM"
372 depends on BR2_ARM_CPU_HAS_ARM
373 help
374 This option instructs the compiler to generate regular ARM
375 instructions, that are all 32 bits wide.
377 config BR2_ARM_INSTRUCTIONS_THUMB
378 bool "Thumb"
379 depends on BR2_ARM_CPU_HAS_THUMB
380 help
381 This option instructions the compiler to generate Thumb
382 instructions, which allows to mix 16 bits instructions and
383 32 bits instructions. This generally provides a much smaller
384 compiled binary size.
386 config BR2_ARM_INSTRUCTIONS_THUMB2
387 bool "Thumb2"
388 depends on BR2_ARM_CPU_HAS_THUMB2
389 help
390 This option instructions the compiler to generate Thumb2
391 instructions, which allows to mix 16 bits instructions and
392 32 bits instructions. This generally provides a much smaller
393 compiled binary size.
395 endchoice
397 config BR2_ARCH
398 default "arm" if BR2_arm
399 default "armeb" if BR2_armeb
401 config BR2_ENDIAN
402 default "LITTLE" if BR2_arm
403 default "BIG" if BR2_armeb
405 config BR2_ARCH_HAS_ATOMICS
406 default y
408 config BR2_GCC_TARGET_CPU
409 default "arm920t" if BR2_arm920t
410 default "arm922t" if BR2_arm922t
411 default "arm926ej-s" if BR2_arm926t
412 default "arm1136j-s" if BR2_arm1136j_s
413 default "arm1136jf-s" if BR2_arm1136jf_s
414 default "arm1176jz-s" if BR2_arm1176jz_s
415 default "arm1176jzf-s" if BR2_arm1176jzf_s
416 default "cortex-a5" if BR2_cortex_a5
417 default "cortex-a7" if BR2_cortex_a7
418 default "cortex-a8" if BR2_cortex_a8
419 default "cortex-a9" if BR2_cortex_a9
420 default "cortex-a12" if BR2_cortex_a12
421 default "cortex-a15" if BR2_cortex_a15
422 default "cortex-m3" if BR2_cortex_m3
423 default "fa526" if BR2_fa526
424 default "marvell-pj4" if BR2_pj4
425 default "strongarm" if BR2_strongarm
426 default "xscale" if BR2_xscale
427 default "iwmmxt" if BR2_iwmmxt
429 config BR2_GCC_TARGET_ABI
430 default "aapcs-linux"
432 config BR2_GCC_TARGET_FPU
433 default "vfp" if BR2_ARM_FPU_VFPV2
434 default "vfpv3" if BR2_ARM_FPU_VFPV3
435 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
436 default "vfpv4" if BR2_ARM_FPU_VFPV4
437 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
438 default "neon" if BR2_ARM_FPU_NEON
439 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
441 config BR2_GCC_TARGET_FLOAT_ABI
442 default "soft" if BR2_ARM_SOFT_FLOAT
443 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
444 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
446 config BR2_GCC_TARGET_MODE
447 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
448 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2