[buildroot-gz.git] / board / arcturus / ppc-ucp1020 / patches / linux / 0001-Arcturus-uCP1020-BSP-support.patch
| blob | 759712714ef68c299ea8991d3d0d94dd00a66000 |
1 From a243628639e12a4bd0a737eac78a12ed240cd137 Mon Sep 17 00:00:00 2001
2 From: Oleksandr G Zhadan <oleks@arcturusnetworks.com>
3 Date: Mon, 18 Jul 2016 10:40:16 -0400
4 Subject: [PATCH] Arcturus uCP1020 BSP support
6 The uCP1020 product family (ucp1020) is an Arcturus Networks Inc.
7 System on Modules product featuring a NXP QorIQ P1020 CPU,
8 optionally populated with 1 or 2 Gig-Ethernet PHYs,
9 DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
11 Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com>
12 Signed-off-by: Michael Durrant <arcsupport@arcturusnetworks.com>
13 ---
14 arch/powerpc/boot/dts/ucp1020.dts | 87 ++++++++++++
15 arch/powerpc/boot/dts/ucp1020.dtsi | 211 ++++++++++++++++++++++++++++++
16 arch/powerpc/platforms/85xx/Kconfig | 7 +
17 arch/powerpc/platforms/85xx/Makefile | 1 +
18 arch/powerpc/platforms/85xx/ucp1020_som.c | 92 +++++++++++++
19 5 files changed, 398 insertions(+)
20 create mode 100644 arch/powerpc/boot/dts/ucp1020.dts
21 create mode 100644 arch/powerpc/boot/dts/ucp1020.dtsi
22 create mode 100644 arch/powerpc/platforms/85xx/ucp1020_som.c
24 diff --git a/arch/powerpc/boot/dts/ucp1020.dts b/arch/powerpc/boot/dts/ucp1020.dts
25 new file mode 100644
26 index 0000000..291e70a
27 --- /dev/null
28 +++ b/arch/powerpc/boot/dts/ucp1020.dts
29 @@ -0,0 +1,87 @@
30 +/*
31 + * uCP1020 Tree Source (32-bit address map)
32 + *
33 + * Copyright 2013-2016 Arcturus Networks Inc.
34 + *
35 + * Redistribution and use in source and binary forms, with or without
36 + * modification, are permitted provided that the following conditions are met:
37 + * * Redistributions of source code must retain the above copyright
38 + * notice, this list of conditions and the following disclaimer.
39 + * * Redistributions in binary form must reproduce the above copyright
40 + * notice, this list of conditions and the following disclaimer in the
41 + * documentation and/or other materials provided with the distribution.
42 + * * Neither the name of Freescale Semiconductor nor the
43 + * names of its contributors may be used to endorse or promote products
44 + * derived from this software without specific prior written permission.
45 + *
46 + *
47 + * ALTERNATIVELY, this software may be distributed under the terms of the
48 + * GNU General Public License ("GPL") as published by the Free Software
49 + * Foundation, either version 2 of that License or (at your option) any
50 + * later version.
51 + *
52 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
53 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
56 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
59 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 + */
63 +
64 +/include/ "fsl/p1020si-pre.dtsi"
65 +/ {
66 + model = "arcturus,uCP1020";
67 + compatible = "arcturus,uCP1020";
68 +
69 + memory {
70 + device_type = "memory";
71 + };
72 +
73 + lbc: localbus@ffe05000 {
74 + reg = <0 0xffe05000 0 0x1000>;
75 +
76 + /* NOR Flash */
77 + ranges = <0x0 0x0 0x0 0xec000000 0x04000000>;
78 + };
79 +
80 + soc: soc@ffe00000 {
81 + ranges = <0x0 0x0 0xffe00000 0x100000>;
82 + };
83 +
84 + pci0: pcie@ffe09000 {
85 + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
86 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
87 + reg = <0 0xffe09000 0 0x1000>;
88 + pcie@0 {
89 + ranges = <0x2000000 0x0 0xa0000000
90 + 0x2000000 0x0 0xa0000000
91 + 0x0 0x20000000
92 +
93 + 0x1000000 0x0 0x0
94 + 0x1000000 0x0 0x0
95 + 0x0 0x100000>;
96 + };
97 + };
98 +
99 + pci1: pcie@ffe0a000 {
100 + reg = <0 0xffe0a000 0 0x1000>;
101 + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
102 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
103 + pcie@0 {
104 + ranges = <0x2000000 0x0 0x80000000
105 + 0x2000000 0x0 0x80000000
106 + 0x0 0x20000000
107 +
108 + 0x1000000 0x0 0x0
109 + 0x1000000 0x0 0x0
110 + 0x0 0x100000>;
111 + };
112 + };
113 +};
114 +
115 +/include/ "ucp1020.dtsi"
116 +/include/ "fsl/p1020si-post.dtsi"
117 diff --git a/arch/powerpc/boot/dts/ucp1020.dtsi b/arch/powerpc/boot/dts/ucp1020.dtsi
118 new file mode 100644
119 index 0000000..7cff949
120 --- /dev/null
121 +++ b/arch/powerpc/boot/dts/ucp1020.dtsi
122 @@ -0,0 +1,211 @@
123 +/*
124 + * uCP1020 Device Tree Source stub (no addresses or top-level ranges)
125 + *
126 + * Copyright 2013-2016 Arcturus Networks Inc.
127 + *
128 + * Redistribution and use in source and binary forms, with or without
129 + * modification, are permitted provided that the following conditions are met:
130 + * * Redistributions of source code must retain the above copyright
131 + * notice, this list of conditions and the following disclaimer.
132 + * * Redistributions in binary form must reproduce the above copyright
133 + * notice, this list of conditions and the following disclaimer in the
134 + * documentation and/or other materials provided with the distribution.
135 + * * Neither the name of Freescale Semiconductor nor the
136 + * names of its contributors may be used to endorse or promote products
137 + * derived from this software without specific prior written permission.
138 + *
139 + *
140 + * ALTERNATIVELY, this software may be distributed under the terms of the
141 + * GNU General Public License ("GPL") as published by the Free Software
142 + * Foundation, either version 2 of that License or (at your option) any
143 + * later version.
144 + *
145 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
146 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
147 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
148 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
149 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
150 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
151 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
152 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
153 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
154 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
155 + */
156 +
157 +&lbc {
158 + nor@0,0 {
159 + #address-cells = <1>;
160 + #size-cells = <1>;
161 + compatible = "cfi-flash";
162 + reg = <0x0 0x0 0x04000000>;
163 + bank-width = <2>;
164 + device-width = <1>;
165 +
166 + partition@100000 {
167 + /* 7MB - PART 0 */
168 + reg = <0x00100000 0x00700000>;
169 + label = "0";
170 + };
171 +
172 + partition@800000 {
173 + /* 32MB - PART 1 */
174 + reg = <0x0800000 0x02000000>;
175 + label = "1";
176 + };
177 +
178 + partition@2800000 {
179 + /* 8MB - PART 2 */
180 + reg = <0x02800000 0x00800000>;
181 + label = "2";
182 + };
183 +
184 + partition@3000000 {
185 + /* (16MB - 512K) - PART 3 JFFS 2 */
186 + reg = <0x03000000 0x00f80000>;
187 + label = "3";
188 + };
189 +
190 + partition@0 {
191 + /* 512KB - bootloader[u-boot, uCbootloader] */
192 + reg = <0x0 0x00080000>;
193 + label = "BOOT_SPI";
194 + };
195 +
196 + partition@3f80000 {
197 + /* 512KB - bootloade NOR r[u-boot, uCbootloader] */
198 + reg = <0x03f80000 0x00080000>;
199 + label = "B";
200 + };
201 +
202 + partition@80000 {
203 + /* 256KB - bootloaders environment (uCenv) */
204 + reg = <0x00080000 0x00040000>;
205 +
206 + label = "E";
207 + };
208 +
209 + partition@C0000 {
210 + /* 256KB - bootloaders environment (u-boot) */
211 + reg = <0x000C0000 0x00040000>;
212 + label = "UENV";
213 + };
214 + };
215 +};
216 +
217 +&soc {
218 + i2c@3000 {
219 + spoc@14 {
220 + compatible = "conexant,cx2070x";
221 + reg = <0x14>;
222 + };
223 + };
224 +
225 + i2c@3100 {
226 + dtt@4C {
227 + compatible = "national,lm90";
228 + reg = <0x4C>;
229 + };
230 + };
231 +
232 + spi@7000 {
233 + flash@0 {
234 + #address-cells = <1>;
235 + #size-cells = <1>;
236 + compatible = "winbond,w25q80bl";
237 + reg = <0>;
238 + spi-max-frequency = <40000000>; /* input clock */
239 +
240 + partition@0 {
241 + label = "SPI MBR";
242 + reg = <0x00000000 0x00002000>;
243 + read-only;
244 + };
245 + partition@2000 {
246 + label = "SPI ENV";
247 + reg = <0x00002000 0x00006000>;
248 + read-only;
249 + };
250 + partition@8000 {
251 + label = "SPI FS";
252 + reg = <0x00008000 0x000F8000>;
253 + };
254 + };
255 + flash@3 {
256 + #address-cells = <1>;
257 + #size-cells = <1>;
258 + compatible = "spansion,s25fl008k";
259 + reg = <3>;
260 + spi-max-frequency = <40000000>; /* input clock */
261 + partition@0 {
262 + label = "SPI USER";
263 + reg = <0x00000000 0x00100000>;
264 + };
265 + };
266 + };
267 +
268 + usb@22000 {
269 + phy_type = "ulpi";
270 + dr_mode = "host";
271 + };
272 +
273 + mdio@24000 {
274 + phy0: ethernet-phy@4 {
275 + interrupt-parent = <&mpic>;
276 + interrupts = <4 1>;
277 + reg = <0x04>;
278 + };
279 +
280 + phy1: ethernet-phy@6 {
281 + interrupt-parent = <&mpic>;
282 + interrupts = <8 1>;
283 + reg = <0x6>;
284 + };
285 + };
286 +
287 + enet0: ethernet@b0000 {
288 + phy-handle = <&phy0>;
289 + phy-connection-type = "rgmii-id";
290 + };
291 +
292 + enet1: ethernet@b1000 {
293 + status = "disabled";
294 + };
295 +
296 + enet2: ethernet@b2000 {
297 + phy-handle = <&phy1>;
298 + phy-connection-type = "rgmii-id";
299 + };
300 +
301 + gpio0: gpio@f000 {
302 + compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
303 + reg = <0xf000 0x1000>;
304 + interrupts = <47 2>;
305 + interrupt-parent = <&mpic>;
306 + #gpio-cells = <2>;
307 + gpio-controller;
308 + };
309 +
310 + gpio-leds {
311 + compatible = "gpio-leds";
312 + gpio5 {
313 + label = "led1"; /* LED15 */
314 + gpios = <&gpio0 5 0>;
315 + };
316 + gpio12 {
317 + label = "led2"; /* LED16 */
318 + gpios = <&gpio0 12 0>;
319 + };
320 + gpio13 {
321 + label = "led3"; /* LED17 */
322 + gpios = <&gpio0 13 0>;
323 + };
324 + gpio7 {
325 + label = "led4"; /* LED18 */
326 + gpios = <&gpio0 7 0>;
327 + };
328 + gpio6 {
329 + label = "led5"; /* LED19 */
330 + gpios = <&gpio0 6 0>;
331 + };
332 + };
333 +};
334 diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
335 index 2fb4b24..81a944f 100644
336 --- a/arch/powerpc/platforms/85xx/Kconfig
337 +++ b/arch/powerpc/platforms/85xx/Kconfig
338 @@ -241,6 +241,13 @@ config SGY_CTS1000
339 help
340 Enable this to support functionality in Servergy's CTS-1000 systems.
342 +config UCP1020_SOM
343 + bool "Arcturus uCP1020 Rev.1.3 System on Module"
344 + select DEFAULT_UIMAGE
345 + help
346 + This option enables support for the Arcturus Networks Inc.
347 + uCP1020 System on Module.
348 +
349 config MVME2500
350 bool "Artesyn MVME2500"
351 select DEFAULT_UIMAGE
352 diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
353 index 1fe7fb9..84f2b9a 100644
354 --- a/arch/powerpc/platforms/85xx/Makefile
355 +++ b/arch/powerpc/platforms/85xx/Makefile
356 @@ -31,4 +31,5 @@ obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
357 obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
358 obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
359 obj-$(CONFIG_SGY_CTS1000) += sgy_cts1000.o
360 +obj-$(CONFIG_UCP1020_SOM) += ucp1020_som.o
361 obj-$(CONFIG_MVME2500) += mvme2500.o
362 diff --git a/arch/powerpc/platforms/85xx/ucp1020_som.c b/arch/powerpc/platforms/85xx/ucp1020_som.c
363 new file mode 100644
364 index 0000000..777e8ad
365 --- /dev/null
366 +++ b/arch/powerpc/platforms/85xx/ucp1020_som.c
367 @@ -0,0 +1,92 @@
368 +/*
369 + * Arcturus Networks Inc. uCP1020 module Setup
370 + *
371 + * Copyright 2014-2016 Arcturus Networks Inc.
372 + *
373 + * by Oleksandr G Zhadan & Michael Durrant (www.ArcturusNetworks.com)
374 + *
375 + * This program is free software; you can redistribute it and/or modify it
376 + * under the terms of the GNU General Public License as published by the
377 + * Free Software Foundation; either version 2 of the License, or (at your
378 + * option) any later version.
379 + */
380 +
381 +#include <linux/stddef.h>
382 +#include <linux/kernel.h>
383 +#include <linux/pci.h>
384 +#include <linux/kdev_t.h>
385 +#include <linux/delay.h>
386 +#include <linux/seq_file.h>
387 +#include <linux/interrupt.h>
388 +#include <linux/of_platform.h>
389 +
390 +#include <asm/time.h>
391 +#include <asm/machdep.h>
392 +#include <asm/pci-bridge.h>
393 +#include <mm/mmu_decl.h>
394 +#include <asm/prom.h>
395 +#include <asm/udbg.h>
396 +#include <asm/mpic.h>
397 +#include <asm/fsl_guts.h>
398 +
399 +#include <sysdev/fsl_soc.h>
400 +#include <sysdev/fsl_pci.h>
401 +#include "smp.h"
402 +
403 +#include "mpc85xx.h"
404 +
405 +void __init ucp1020_som_pic_init(void)
406 +{
407 + struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
408 + MPIC_SINGLE_DEST_CPU,
409 + 0, 256, " OpenPIC ");
410 +
411 + BUG_ON(mpic == NULL);
412 +
413 + mpic_init(mpic);
414 +}
415 +
416 +/*
417 + * Setup the architecture
418 + */
419 +static void __init ucp1020_som_setup_arch(void)
420 +{
421 + if (ppc_md.progress)
422 + ppc_md.progress("uCP1020_SoM_setup_arch()", 0);
423 +
424 + mpc85xx_smp_init();
425 +
426 + fsl_pci_assign_primary();
427 + pr_info("\n\t%s (http://www.arcturusnetworks.com)\n", ppc_md.name);
428 +}
429 +
430 +machine_arch_initcall(ucp1020, mpc85xx_common_publish_devices);
431 +machine_arch_initcall(ucp1020, swiotlb_setup_bus_notifier);
432 +
433 +/*
434 + * Called very early, device-tree isn't unflattened
435 + */
436 +static int __init ucp1020_probe(void)
437 +{
438 + unsigned long root = of_get_flat_dt_root();
439 +
440 + if (of_flat_dt_is_compatible(root, "arcturus,uCP1020"))
441 + return 1;
442 + return 0;
443 +}
444 +
445 +define_machine(ucp1020) {
446 + .name = "uCP1020 SoM - Arcturus Networks Inc.",
447 + .probe = ucp1020_probe,
448 + .setup_arch = ucp1020_som_setup_arch,
449 + .init_IRQ = ucp1020_som_pic_init,
450 +#ifdef CONFIG_PCI
451 + .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
452 +#endif
453 + .get_irq = mpic_get_irq,
454 + .restart = fsl_rstcr_restart,
455 + .calibrate_decr = generic_calibrate_decr,
456 +#ifdef DEBUG
457 + .progress = udbg_progress,
458 +#endif
459 +};
460 --
461 2.1.4