prj/tech/libsrc/dev2d/vgareg.h

   1 /*
   2  * $RCSfile: vgareg.h $
   3  * $Revision: 1.1 $
   4  * $Author: KEVIN $
   5  * $Date: 1996/04/10 17:02:21 $
   6  *
   7  * Constants for vga registers.
   8  *
   9  * This file is part of the dev2d library.
  10  */
  11
  12 #ifndef __VGAREGS_H
  13 #define __VGAREGS_H
  14
  15 #ifdef __cplusplus
  16 extern "C" {
  17 #endif
  18
  19 /* VGA base video address */
  20 #define VGA_BASE   0xa0000
  21
  22 /* VGA miscellaneous registers */
  23 #define GEN_STAT0  0x3c2
  24 #define GEN_STAT1  0x3da
  25 #define GEN_MSCOUT_R    0x3cc
  26 #define GEN_MSCOUT_W    0x3c2
  27 #define GEN_FEAT_R      0x3ca
  28 #define GEN_FEAT_W      0x3da
  29 #define MR_STAT    0x3da                        /* vga status reg */
  30 #define MR_VSYNC   8                                    /* vertical retrace bit */
  31 #define MR_HSYNC   1             /* horizontal retrace bit */
  32
  33 /* VGA sequencer register stuff */
  34 #define SRX_ADR    0x3c4                        /* sequencer address port */
  35 #define SRX_DATA   0x3c5                        /* sequencer data port */
  36 #define SR_MAP     2                                    /* seq map mask reg */
  37 #define SR_MEMORY  4                                    /* seq memory mode reg */
  38 #define SR4_C4     8                                    /* chain4 bit */
  39 #define SR4_OE           4                                      /* odd/even bit */
  40
  41 /* VGA CRT controller registers */
  42 #define CRX_ADR    0x3d4                        /* crt controller address port */
  43 #define CRX_DATA   0x3d5                        /* crt controller data */
  44 #define CR_MAX     0x9           /* maximum scan line register. */
  45 #define CR_SAH     0xc                          /* screen source address high */
  46 #define CR_SAL     0xd                          /* low */
  47 #define CR_OFFSET  0x13                         /* crtc offset reg */
  48 #define CR_ULINE   0x14                         /* crtc underline register */
  49 #define CR14_DWORD 64                           /* dword mode bit */
  50 #define CR_MODE    0x17                         /* crtc mode register */
  51 #define CR17_BYTE  64                           /* byte mode bit */
  52
  53 /* VGA graphics controller registers */
  54 #define GRX_ADR    0x3ce                        /* graphics controller address port */
  55 #define GRX_DATA   0x3cf                        /* gc data port */
  56 #define GR_MAP     4                                    /* gc read map select */
  57 #define GR_MODE    5                                    /* gc mode register index */
  58 #define GR5_OE     16                           /* odd/even bit */
  59 #define GR_MISC    6                                    /* gc misc register index */
  60 #define GR6_CHAIN  2                                    /* chain bit */
  61 #define GR6_MODE   1             /* mode bit */
  62
  63 /* VGA attribute controller */
  64 #define ARX_ADR    0x3c0                        /* attibute controller address port */
  65 #define ARX_WRITE  0x3c0                        /* ar data port */
  66 #define ARX_READ         0x3c1
  67 #define AR_HPAN    0x13                         /* horizontal panning register */
  68 #define AR_PAS     0x20
  69
  70 /* VGA PEL registers. */
  71 #define PEL_RADR   0x3c7         /* PEL address for reads */
  72 #define PEL_WADR   0x3c8         /* PEL address for writes */
  73 #define PEL_DATA   0x3c9         /* PEL data read/write register */
  74
  75 #ifdef __cplusplus
  76 };
  77 #endif
  78 #endif /* !__VGAREGS_H */