Semi-decennial update. 50% code inflation.
[cbaos.git] / arch / arm-cortex-m0 / crt.c
blob422906c8fa738d87675baa96c9cec095e9d38a58
1 /* Author: Domen Puncer <domen@cba.si>. License: WTFPL, see file LICENSE */
2 #include "arch/crt.h"
4 extern void _ram_end;
6 void __naked reset_handler()
8 /* cortex-m3 trm 2.2.1 main stack and process stack */
9 asm volatile (
10 /* select PSP as current stack pointer */
11 "mrs r0, CONTROL\n"
12 "mov r1, #2\n"
13 "orr r0, r1\n"
14 "msr CONTROL, r0\n"
15 "isb\n"
17 /* hrm... this stack is ignored laters anyways, as the scheduler starts,
18 * so it could just be the same as for exceptions, yes? */
19 "ldr r0, =_ram_end-1024\n" /* 1k for main stack */
20 "mov sp, r0\n"
22 "bl init\n"
23 "bl main\n"
24 "b generic_exception_handler\n"
28 /* cortex-m3 trm, 5.5.1, mcu stacks xPSR, PC, LR, R12, R3, R2, R1, R0 */
29 void __naked generic_exception_handler()
31 asm volatile (
32 "mov r2, lr\n"
33 "mov r1, #0x4\n"
34 "tst r2, r1\n" /* process task, see EXC_RETURN */
36 "mrs r0, MSP\n"
37 "beq 1f\n"
38 "mrs r0, PSP\n"
39 "1:\n"
41 /* yeah, on cortex-m3 this is push {r4-r11, lr} :P */
42 "push {lr}\n"
43 "mov lr, r0\n" /* tmp for sp */
44 "mov r0, r8\n"
45 "mov r1, r9\n"
46 "mov r2, r10\n"
47 "mov r3, r11\n"
48 "push {r0-r3}\n" /* r8-r11 */
49 "push {r4-r7}\n"
50 "mov r0, lr\n" /* restore sp to r0 */
52 "mov r1, sp\n\t"
53 "mrs r2, IPSR\n\t"
54 "b generic_exception_handler_c\n\t"