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Now it works.
[cbs-scheduler.git] / sound / soc / s3c24xx / s3c2412-i2s.c
blobf3fc0aba0aaf78755d2e0170eeabcc82d575f31b
1 /* sound/soc/s3c24xx/s3c2412-i2s.c
2 *
3 * ALSA Soc Audio Layer - S3C2412 I2S driver
4 *
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
8 *
9 * Copyright (c) 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/kernel.h>
25
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
31 #include <mach/hardware.h>
32
33 #include <linux/io.h>
34 #include <asm/dma.h>
35
36 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
37
38 #include <mach/regs-gpio.h>
39 #include <mach/audio.h>
40 #include <mach/dma.h>
41
42 #include "s3c24xx-pcm.h"
43 #include "s3c2412-i2s.h"
44
45 #define S3C2412_I2S_DEBUG 0
46 #define S3C2412_I2S_DEBUG_CON 0
47
48 #if S3C2412_I2S_DEBUG
49 #define DBG(x...) printk(KERN_INFO x)
50 #else
51 #define DBG(x...) do { } while (0)
52 #endif
53
54 static struct s3c2410_dma_client s3c2412_dma_client_out = {
55 .name = "I2S PCM Stereo out"
56 };
57
58 static struct s3c2410_dma_client s3c2412_dma_client_in = {
59 .name = "I2S PCM Stereo in"
60 };
61
62 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_out = {
63 .client = &s3c2412_dma_client_out,
64 .channel = DMACH_I2S_OUT,
65 .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
66 .dma_size = 4,
67 };
68
69 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_in = {
70 .client = &s3c2412_dma_client_in,
71 .channel = DMACH_I2S_IN,
72 .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
73 .dma_size = 4,
74 };
75
76 struct s3c2412_i2s_info {
77 struct device *dev;
78 void __iomem *regs;
79 struct clk *iis_clk;
80 struct clk *iis_pclk;
81 struct clk *iis_cclk;
82
83 u32 suspend_iismod;
84 u32 suspend_iiscon;
85 u32 suspend_iispsr;
86 };
87
88 static struct s3c2412_i2s_info s3c2412_i2s;
89
90 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
91
92 #if S3C2412_I2S_DEBUG_CON
93 static void dbg_showcon(const char *fn, u32 con)
94 {
95 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
96 bit_set(con, S3C2412_IISCON_LRINDEX),
97 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
98 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
99 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
100 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
101
102 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
103 fn,
104 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
105 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
106 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
107 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
108 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
109 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
110 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
111 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
112 }
113 #else
114 static inline void dbg_showcon(const char *fn, u32 con)
115 {
116 }
117 #endif
118
119 /* Turn on or off the transmission path. */
120 static void s3c2412_snd_txctrl(int on)
121 {
122 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
123 void __iomem *regs = i2s->regs;
124 u32 fic, con, mod;
125
126 DBG("%s(%d)\n", __func__, on);
127
128 fic = readl(regs + S3C2412_IISFIC);
129 con = readl(regs + S3C2412_IISCON);
130 mod = readl(regs + S3C2412_IISMOD);
131
132 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
133
134 if (on) {
135 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
136 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
137 con &= ~S3C2412_IISCON_TXCH_PAUSE;
138
139 switch (mod & S3C2412_IISMOD_MODE_MASK) {
140 case S3C2412_IISMOD_MODE_TXONLY:
141 case S3C2412_IISMOD_MODE_TXRX:
142 /* do nothing, we are in the right mode */
143 break;
144
145 case S3C2412_IISMOD_MODE_RXONLY:
146 mod &= ~S3C2412_IISMOD_MODE_MASK;
147 mod |= S3C2412_IISMOD_MODE_TXRX;
148 break;
149
150 default:
151 dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n");
152 }
153
154 writel(con, regs + S3C2412_IISCON);
155 writel(mod, regs + S3C2412_IISMOD);
156 } else {
157 /* Note, we do not have any indication that the FIFO problems
158 * tha the S3C2410/2440 had apply here, so we should be able
159 * to disable the DMA and TX without resetting the FIFOS.
160 */
161
162 con |= S3C2412_IISCON_TXDMA_PAUSE;
163 con |= S3C2412_IISCON_TXCH_PAUSE;
164 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
165
166 switch (mod & S3C2412_IISMOD_MODE_MASK) {
167 case S3C2412_IISMOD_MODE_TXRX:
168 mod &= ~S3C2412_IISMOD_MODE_MASK;
169 mod |= S3C2412_IISMOD_MODE_RXONLY;
170 break;
171
172 case S3C2412_IISMOD_MODE_TXONLY:
173 mod &= ~S3C2412_IISMOD_MODE_MASK;
174 con &= ~S3C2412_IISCON_IIS_ACTIVE;
175 break;
176
177 default:
178 dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n");
179 }
180
181 writel(mod, regs + S3C2412_IISMOD);
182 writel(con, regs + S3C2412_IISCON);
183 }
184
185 fic = readl(regs + S3C2412_IISFIC);
186 dbg_showcon(__func__, con);
187 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
188 }
189
190 static void s3c2412_snd_rxctrl(int on)
191 {
192 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
193 void __iomem *regs = i2s->regs;
194 u32 fic, con, mod;
195
196 DBG("%s(%d)\n", __func__, on);
197
198 fic = readl(regs + S3C2412_IISFIC);
199 con = readl(regs + S3C2412_IISCON);
200 mod = readl(regs + S3C2412_IISMOD);
201
202 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
203
204 if (on) {
205 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
206 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
207 con &= ~S3C2412_IISCON_RXCH_PAUSE;
208
209 switch (mod & S3C2412_IISMOD_MODE_MASK) {
210 case S3C2412_IISMOD_MODE_TXRX:
211 case S3C2412_IISMOD_MODE_RXONLY:
212 /* do nothing, we are in the right mode */
213 break;
214
215 case S3C2412_IISMOD_MODE_TXONLY:
216 mod &= ~S3C2412_IISMOD_MODE_MASK;
217 mod |= S3C2412_IISMOD_MODE_TXRX;
218 break;
219
220 default:
221 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
222 }
223
224 writel(mod, regs + S3C2412_IISMOD);
225 writel(con, regs + S3C2412_IISCON);
226 } else {
227 /* See txctrl notes on FIFOs. */
228
229 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
230 con |= S3C2412_IISCON_RXDMA_PAUSE;
231 con |= S3C2412_IISCON_RXCH_PAUSE;
232
233 switch (mod & S3C2412_IISMOD_MODE_MASK) {
234 case S3C2412_IISMOD_MODE_RXONLY:
235 con &= ~S3C2412_IISCON_IIS_ACTIVE;
236 mod &= ~S3C2412_IISMOD_MODE_MASK;
237 break;
238
239 case S3C2412_IISMOD_MODE_TXRX:
240 mod &= ~S3C2412_IISMOD_MODE_MASK;
241 mod |= S3C2412_IISMOD_MODE_TXONLY;
242 break;
243
244 default:
245 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
246 }
247
248 writel(con, regs + S3C2412_IISCON);
249 writel(mod, regs + S3C2412_IISMOD);
250 }
251
252 fic = readl(regs + S3C2412_IISFIC);
253 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
254 }
255
256
257 /*
258 * Wait for the LR signal to allow synchronisation to the L/R clock
259 * from the codec. May only be needed for slave mode.
260 */
261 static int s3c2412_snd_lrsync(void)
262 {
263 u32 iiscon;
264 unsigned long timeout = jiffies + msecs_to_jiffies(5);
265
266 DBG("Entered %s\n", __func__);
267
268 while (1) {
269 iiscon = readl(s3c2412_i2s.regs + S3C2412_IISCON);
270 if (iiscon & S3C2412_IISCON_LRINDEX)
271 break;
272
273 if (timeout < jiffies) {
274 printk(KERN_ERR "%s: timeout\n", __func__);
275 return -ETIMEDOUT;
276 }
277 }
278
279 return 0;
280 }
281
282 /*
283 * Check whether CPU is the master or slave
284 */
285 static inline int s3c2412_snd_is_clkmaster(void)
286 {
287 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
288
289 DBG("Entered %s\n", __func__);
290
291 iismod &= S3C2412_IISMOD_MASTER_MASK;
292 return !(iismod == S3C2412_IISMOD_SLAVE);
293 }
294
295 /*
296 * Set S3C2412 I2S DAI format
297 */
298 static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
299 unsigned int fmt)
300 {
301 u32 iismod;
302
303
304 DBG("Entered %s\n", __func__);
305
306 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
307 DBG("hw_params r: IISMOD: %x \n", iismod);
308
309 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
310 case SND_SOC_DAIFMT_CBM_CFM:
311 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
312 iismod |= S3C2412_IISMOD_SLAVE;
313 break;
314 case SND_SOC_DAIFMT_CBS_CFS:
315 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
316 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
317 break;
318 default:
319 DBG("unknwon master/slave format\n");
320 return -EINVAL;
321 }
322
323 iismod &= ~S3C2412_IISMOD_SDF_MASK;
324
325 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
326 case SND_SOC_DAIFMT_RIGHT_J:
327 iismod |= S3C2412_IISMOD_SDF_MSB;
328 break;
329 case SND_SOC_DAIFMT_LEFT_J:
330 iismod |= S3C2412_IISMOD_SDF_LSB;
331 break;
332 case SND_SOC_DAIFMT_I2S:
333 iismod |= S3C2412_IISMOD_SDF_IIS;
334 break;
335 default:
336 DBG("Unknown data format\n");
337 return -EINVAL;
338 }
339
340 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
341 DBG("hw_params w: IISMOD: %x \n", iismod);
342 return 0;
343 }
344
345 static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
346 struct snd_pcm_hw_params *params,
347 struct snd_soc_dai *dai)
348 {
349 struct snd_soc_pcm_runtime *rtd = substream->private_data;
350 u32 iismod;
351
352 DBG("Entered %s\n", __func__);
353
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
355 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_out;
356 else
357 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_in;
358
359 /* Working copies of register */
360 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
361 DBG("%s: r: IISMOD: %x\n", __func__, iismod);
362
363 switch (params_format(params)) {
364 case SNDRV_PCM_FORMAT_S8:
365 iismod |= S3C2412_IISMOD_8BIT;
366 break;
367 case SNDRV_PCM_FORMAT_S16_LE:
368 iismod &= ~S3C2412_IISMOD_8BIT;
369 break;
370 }
371
372 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
373 DBG("%s: w: IISMOD: %x\n", __func__, iismod);
374 return 0;
375 }
376
377 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
378 struct snd_soc_dai *dai)
379 {
380 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
381 unsigned long irqs;
382 int ret = 0;
383
384 DBG("Entered %s\n", __func__);
385
386 switch (cmd) {
387 case SNDRV_PCM_TRIGGER_START:
388 /* On start, ensure that the FIFOs are cleared and reset. */
389
390 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
391 s3c2412_i2s.regs + S3C2412_IISFIC);
392
393 /* clear again, just in case */
394 writel(0x0, s3c2412_i2s.regs + S3C2412_IISFIC);
395
396 case SNDRV_PCM_TRIGGER_RESUME:
397 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
398 if (!s3c2412_snd_is_clkmaster()) {
399 ret = s3c2412_snd_lrsync();
400 if (ret)
401 goto exit_err;
402 }
403
404 local_irq_save(irqs);
405
406 if (capture)
407 s3c2412_snd_rxctrl(1);
408 else
409 s3c2412_snd_txctrl(1);
410
411 local_irq_restore(irqs);
412 break;
413
414 case SNDRV_PCM_TRIGGER_STOP:
415 case SNDRV_PCM_TRIGGER_SUSPEND:
416 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
417 local_irq_save(irqs);
418
419 if (capture)
420 s3c2412_snd_rxctrl(0);
421 else
422 s3c2412_snd_txctrl(0);
423
424 local_irq_restore(irqs);
425 break;
426 default:
427 ret = -EINVAL;
428 break;
429 }
430
431 exit_err:
432 return ret;
433 }
434
435 /* default table of all avaialable root fs divisors */
436 static unsigned int s3c2412_iis_fs[] = { 256, 512, 384, 768, 0 };
437
438 int s3c2412_iis_calc_rate(struct s3c2412_rate_calc *info,
439 unsigned int *fstab,
440 unsigned int rate, struct clk *clk)
441 {
442 unsigned long clkrate = clk_get_rate(clk);
443 unsigned int div;
444 unsigned int fsclk;
445 unsigned int actual;
446 unsigned int fs;
447 unsigned int fsdiv;
448 signed int deviation = 0;
449 unsigned int best_fs = 0;
450 unsigned int best_div = 0;
451 unsigned int best_rate = 0;
452 unsigned int best_deviation = INT_MAX;
453
454
455 if (fstab == NULL)
456 fstab = s3c2412_iis_fs;
457
458 for (fs = 0;; fs++) {
459 fsdiv = s3c2412_iis_fs[fs];
460
461 if (fsdiv == 0)
462 break;
463
464 fsclk = clkrate / fsdiv;
465 div = fsclk / rate;
466
467 if ((fsclk % rate) > (rate / 2))
468 div++;
469
470 if (div <= 1)
471 continue;
472
473 actual = clkrate / (fsdiv * div);
474 deviation = actual - rate;
475
476 printk(KERN_DEBUG "%dfs: div %d => result %d, deviation %d\n",
477 fsdiv, div, actual, deviation);
478
479 deviation = abs(deviation);
480
481 if (deviation < best_deviation) {
482 best_fs = fsdiv;
483 best_div = div;
484 best_rate = actual;
485 best_deviation = deviation;
486 }
487
488 if (deviation == 0)
489 break;
490 }
491
492 printk(KERN_DEBUG "best: fs=%d, div=%d, rate=%d\n",
493 best_fs, best_div, best_rate);
494
495 info->fs_div = best_fs;
496 info->clk_div = best_div;
497
498 return 0;
499 }
500 EXPORT_SYMBOL_GPL(s3c2412_iis_calc_rate);
501
502 /*
503 * Set S3C2412 Clock source
504 */
505 static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
506 int clk_id, unsigned int freq, int dir)
507 {
508 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
509
510 DBG("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
511 freq, dir);
512
513 switch (clk_id) {
514 case S3C2412_CLKSRC_PCLK:
515 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
516 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
517 break;
518 case S3C2412_CLKSRC_I2SCLK:
519 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
520 iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
521 break;
522 default:
523 return -EINVAL;
524 }
525
526 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
527 return 0;
528 }
529
530 /*
531 * Set S3C2412 Clock dividers
532 */
533 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
534 int div_id, int div)
535 {
536 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
537 u32 reg;
538
539 DBG("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
540
541 switch (div_id) {
542 case S3C2412_DIV_BCLK:
543 reg = readl(i2s->regs + S3C2412_IISMOD);
544 reg &= ~S3C2412_IISMOD_BCLK_MASK;
545 writel(reg | div, i2s->regs + S3C2412_IISMOD);
546
547 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
548 break;
549
550 case S3C2412_DIV_RCLK:
551 if (div > 3) {
552 /* convert value to bit field */
553
554 switch (div) {
555 case 256:
556 div = S3C2412_IISMOD_RCLK_256FS;
557 break;
558
559 case 384:
560 div = S3C2412_IISMOD_RCLK_384FS;
561 break;
562
563 case 512:
564 div = S3C2412_IISMOD_RCLK_512FS;
565 break;
566
567 case 768:
568 div = S3C2412_IISMOD_RCLK_768FS;
569 break;
570
571 default:
572 return -EINVAL;
573 }
574 }
575
576 reg = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
577 reg &= ~S3C2412_IISMOD_RCLK_MASK;
578 writel(reg | div, i2s->regs + S3C2412_IISMOD);
579 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
580 break;
581
582 case S3C2412_DIV_PRESCALER:
583 if (div >= 0) {
584 writel((div << 8) | S3C2412_IISPSR_PSREN,
585 i2s->regs + S3C2412_IISPSR);
586 } else {
587 writel(0x0, i2s->regs + S3C2412_IISPSR);
588 }
589 DBG("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
590 break;
591
592 default:
593 return -EINVAL;
594 }
595
596 return 0;
597 }
598
599 struct clk *s3c2412_get_iisclk(void)
600 {
601 return s3c2412_i2s.iis_clk;
602 }
603 EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);
604
605
606 static int s3c2412_i2s_probe(struct platform_device *pdev,
607 struct snd_soc_dai *dai)
608 {
609 DBG("Entered %s\n", __func__);
610
611 s3c2412_i2s.dev = &pdev->dev;
612
613 s3c2412_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
614 if (s3c2412_i2s.regs == NULL)
615 return -ENXIO;
616
617 s3c2412_i2s.iis_pclk = clk_get(&pdev->dev, "iis");
618 if (s3c2412_i2s.iis_pclk == NULL) {
619 DBG("failed to get iis_clock\n");
620 iounmap(s3c2412_i2s.regs);
621 return -ENODEV;
622 }
623
624 s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
625 if (s3c2412_i2s.iis_cclk == NULL) {
626 DBG("failed to get i2sclk clock\n");
627 iounmap(s3c2412_i2s.regs);
628 return -ENODEV;
629 }
630
631 clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
632
633 clk_enable(s3c2412_i2s.iis_pclk);
634 clk_enable(s3c2412_i2s.iis_cclk);
635
636 s3c2412_i2s.iis_clk = s3c2412_i2s.iis_pclk;
637
638 /* Configure the I2S pins in correct mode */
639 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
640 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
641 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
642 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
643 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
644
645 s3c2412_snd_txctrl(0);
646 s3c2412_snd_rxctrl(0);
647
648 return 0;
649 }
650
651 #ifdef CONFIG_PM
652 static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
653 {
654 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
655 u32 iismod;
656
657 if (dai->active) {
658 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
659 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
660 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
661
662 /* some basic suspend checks */
663
664 iismod = readl(i2s->regs + S3C2412_IISMOD);
665
666 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
667 pr_warning("%s: RXDMA active?\n", __func__);
668
669 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
670 pr_warning("%s: TXDMA active?\n", __func__);
671
672 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
673 pr_warning("%s: IIS active\n", __func__);
674 }
675
676 return 0;
677 }
678
679 static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
680 {
681 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
682
683 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
684 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
685
686 if (dai->active) {
687 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
688 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
689 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
690
691 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
692 i2s->regs + S3C2412_IISFIC);
693
694 ndelay(250);
695 writel(0x0, i2s->regs + S3C2412_IISFIC);
696
697 }
698
699 return 0;
700 }
701 #else
702 #define s3c2412_i2s_suspend NULL
703 #define s3c2412_i2s_resume NULL
704 #endif /* CONFIG_PM */
705
706 #define S3C2412_I2S_RATES \
707 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
708 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
709 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
710
711 struct snd_soc_dai s3c2412_i2s_dai = {
712 .name = "s3c2412-i2s",
713 .id = 0,
714 .probe = s3c2412_i2s_probe,
715 .suspend = s3c2412_i2s_suspend,
716 .resume = s3c2412_i2s_resume,
717 .playback = {
718 .channels_min = 2,
719 .channels_max = 2,
720 .rates = S3C2412_I2S_RATES,
721 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
722 },
723 .capture = {
724 .channels_min = 2,
725 .channels_max = 2,
726 .rates = S3C2412_I2S_RATES,
727 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
728 },
729 .ops = {
730 .trigger = s3c2412_i2s_trigger,
731 .hw_params = s3c2412_i2s_hw_params,
732 .set_fmt = s3c2412_i2s_set_fmt,
733 .set_clkdiv = s3c2412_i2s_set_clkdiv,
734 .set_sysclk = s3c2412_i2s_set_sysclk,
735 },
736 };
737 EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);
738
739 static int __init s3c2412_i2s_init(void)
740 {
741 return snd_soc_register_dai(&s3c2412_i2s_dai);
742 }
743 module_init(s3c2412_i2s_init);
744
745 static void __exit s3c2412_i2s_exit(void)
746 {
747 snd_soc_unregister_dai(&s3c2412_i2s_dai);
748 }
749 module_exit(s3c2412_i2s_exit);
750
751
752 /* Module information */
753 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
754 MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
755 MODULE_LICENSE("GPL");
A cbs scheduler for rt-kernel