freakusb/hw/at90usbxx2/at90usb.h

   1 /*******************************************************************
   2     Copyright (C) 2009 FreakLabs
   3     All rights reserved.
   4
   5     Redistribution and use in source and binary forms, with or without
   6     modification, are permitted provided that the following conditions
   7     are met:
   8
   9     1. Redistributions of source code must retain the above copyright
  10        notice, this list of conditions and the following disclaimer.
  11     2. Redistributions in binary form must reproduce the above copyright
  12        notice, this list of conditions and the following disclaimer in the
  13        documentation and/or other materials provided with the distribution.
  14     3. Neither the name of the the copyright holder nor the names of its contributors
  15        may be used to endorse or promote products derived from this software
  16        without specific prior written permission.
  17
  18     THIS SOFTWARE IS PROVIDED BY THE THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
  19     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20     IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21     ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
  22     FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23     DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24     OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27     OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28     SUCH DAMAGE.
  29
  30     Originally written by Christopher Wang aka Akiba.
  31     Please post support questions to the FreakLabs forum.
  32 *******************************************************************/
  33 /*!
  34     \file at90usb.h
  35     \ingroup hw_at90usb
  36 */
  37 /*******************************************************************/
  38 #ifndef AT90USB_H
  39 #define AT90USB_H
  40
  41 #include <avr/io.h>
  42
  43 #define AT90USB16
  44
  45 #define VBUS_SENSE_DDR      DDRB
  46 #define VBUS_SENSE_PORT     PORTB
  47 #define VBUS_SENSE_PIN      PINB
  48 #define VBUS_SENSE_IO       5
  49
  50 // test if vbus is present
  51 #define is_vbus_on()        ((VBUS_SENSE_PIN & (1<<VBUS_SENSE_IO)) != 0)
  52
  53 // banks
  54 #define SINGLE          0
  55 #define DUAL            1
  56
  57 #define PLL_LOCKED          (PLLCSR & (1 << PLOCK))
  58 #define FIFO_BYTE_CNT       UEBCLX
  59
  60 #define TX_DATA()           (UEINTX &= ~TX_IN_INT_MASK)
  61 #define TX_FIFO_READY       (UEINTX &   TX_IN_INT_MASK)
  62 #define SET_DEVICE_MODE()   (UHWCON |= (1<<UIMOD))
  63
  64 #define DEV_INT_MASK(intp)  (1 << intp)
  65 #define VBUS_INT_MASK       DEV_INT_MASK(VBUSTI)
  66 #define SUSP_INT_MASK       DEV_INT_MASK(SUSPI)
  67 #define RESM_INT_MASK       DEV_INT_MASK(EORSMI)
  68 #define EOR_INT_MASK        DEV_INT_MASK(EORSTI)
  69 #define WAKEUP_INT_MASK     DEV_INT_MASK(WAKEUPI)
  70
  71 #define DEV_INT_ENB_MASK(intp) (1 << intp)
  72 #define VBUS_INT_ENB_MASK   DEV_INT_ENB_MASK(VBUSTE)
  73 #define SUSP_INT_ENB_MASK   DEV_INT_ENB_MASK(SUSPE)
  74 #define RESM_INT_ENB_MASK   DEV_INT_ENB_MASK(EORSME)
  75 #define EOR_INT_ENB_MASK    DEV_INT_ENB_MASK(EORSTE)
  76 #define WAKEUP_INT_ENB_MASK DEV_INT_ENB_MASK(WAKEUPE)
  77
  78 // global intps
  79 #define VBUS_INT            (USBINT & VBUS_INT_MASK)
  80 #define VBUS_INT_ENABLED    (USBCON & VBUS_INT_ENB_MASK)
  81 #define VBUS_INT_CLR()      (USBINT &= ~VBUS_INT_MASK)
  82 #define VBUS_INT_ENB()      (USBCON |= VBUS_INT_ENB_MASK)
  83 #define VBUS_INT_DIS()      (USBCON &= ~VBUS_INT_ENB_MASK)
  84
  85 // device intps
  86 #define DEV_INT(mask)       (UDINT & mask)
  87 #define SUSP_INT            DEV_INT(SUSP_INT_MASK)
  88 #define RESM_INT            DEV_INT(RESM_INT_MASK)
  89 #define EOR_INT             DEV_INT(EOR_INT_MASK)
  90 #define WAKEUP_INT          DEV_INT(WAKEUP_INT_MASK)
  91
  92 #define DEV_INT_ENABLED(mask)       (UDIEN & mask)
  93 #define SUSP_INT_ENABLED    DEV_INT_ENABLED(SUSP_INT_ENB_MASK)
  94 #define RESM_INT_ENABLED    DEV_INT_ENABLED(RESM_INT_ENB_MASK)
  95 #define EOR_INT_ENABLED     DEV_INT_ENABLED(EOR_INT_ENB_MASK)
  96 #define WAKEUP_INT_ENABLED  DEV_INT_ENABLED(WAKEUP_INT_ENB_MASK)
  97
  98 #define DEV_INT_CLR(mask)   (UDINT &= ~mask)
  99 #define SUSP_INT_CLR()      DEV_INT_CLR(SUSP_INT_MASK)
 100 #define RESM_INT_CLR()      DEV_INT_CLR(RESM_INT_MASK)
 101 #define EOR_INT_CLR()       DEV_INT_CLR(EOR_INT_MASK)
 102 #define WAKEUP_INT_CLR()    DEV_INT_CLR(WAKEUP_INT_MASK)
 103
 104 #define DEV_INT_ENB(mask)   (UDIEN |= mask)
 105 #define SUSP_INT_ENB()      DEV_INT_ENB(SUSP_INT_ENB_MASK)
 106 #define RESM_INT_ENB()      DEV_INT_ENB(RESM_INT_ENB_MASK)
 107 #define EOR_INT_ENB()       DEV_INT_ENB(EOR_INT_ENB_MASK)
 108 #define WAKEUP_INT_ENB()    DEV_INT_ENB(WAKEUP_INT_ENB_MASK)
 109
 110 #define DEV_INT_DIS(mask)  (UDIEN &= ~mask)
 111 #define SUSP_INT_DIS()      DEV_INT_DIS(SUSP_INT_ENB_MASK)
 112 #define RESM_INT_DIS()      DEV_INT_DIS(RESM_INT_ENB_MASK)
 113 #define EOR_INT_DIS()       DEV_INT_DIS(EOR_INT_ENB_MASK)
 114 #define WAKEUP_INT_DIS()    DEV_INT_DIS(WAKEUP_INT_ENB_MASK)
 115
 116 // endpoint intps
 117 #define EP_INT_MASK(intp)   (1 << intp)
 118 #define TX_IN_INT_MASK      EP_INT_MASK(TXINI)
 119 #define STALL_INT_MASK      EP_INT_MASK(STALLEDI)
 120 #define FIFOCON_INT_MASK    EP_INT_MASK(FIFOCON)
 121 #define NAK_IN_INT_MASK     EP_INT_MASK(NAKINI)
 122 #define RWAL_INT_MASK       EP_INT_MASK(RWAL)
 123 #define NAK_OUT_INT_MASK    EP_INT_MASK(NAKOUTI)
 124 #define RX_SETUP_INT_MASK   EP_INT_MASK(RXSTPI)
 125 #define RX_OUT_INT_MASK     EP_INT_MASK(RXOUTI)
 126
 127 #define EP_INT_ENB_MASK(intp)   (1 << intp)
 128 #define TX_IN_INT_ENB_MASK      EP_INT_ENB_MASK(TXINE)
 129 #define STALL_INT_ENB_MASK      EP_INT_ENB_MASK(STALLEDE)
 130 #define FLOW_ERR_INT_ENB_MASK   EP_INT_ENB_MASK(FLERRE)
 131 #define NAK_IN_INT_ENB_MASK     EP_INT_ENB_MASK(NAKINE)
 132 #define NAK_OUT_INT_ENB_MASK    EP_INT_ENB_MASK(NAKOUTE)
 133 #define RX_SETUP_INT_ENB_MASK   EP_INT_ENB_MASK(RXSTPE)
 134 #define RX_OUT_INT_ENB_MASK     EP_INT_ENB_MASK(RXOUTE)
 135
 136 #define EP_INT(mask)        (UEINTX & mask)
 137 #define TX_IN_INT           EP_INT(TX_IN_INT_MASK)
 138 #define STALL_INT           EP_INT(STALL_INT_MASK)
 139 #define FIFOCON_INT         EP_INT(FIFOCON_INT_MASK)
 140 #define NAK_IN_INT          EP_INT(NAK_IN_INT_MASK)
 141 #define RWAL_INT            EP_INT(RWAL_INT_MASK)
 142 #define NAK_OUT_INT         EP_INT(NAK_OUT_INT_MASK)
 143 #define RX_SETUP_INT        EP_INT(RX_SETUP_INT_MASK)
 144 #define RX_OUT_INT          EP_INT(RX_OUT_INT_MASK)
 145
 146 #define EP_INT_ENABLED(mask)    (UEIENX & mask)
 147 #define TX_IN_INT_ENABLED       EP_INT_ENABLED(TX_IN_INT_ENB_MASK)
 148 #define STALL_INT_ENABLED       EP_INT_ENABLED(STALL_INT_ENB_MASK)
 149 #define FLOW_ERR_INT_ENABLED    EP_INT_ENABLED(FLOW_ERR_INT_ENB_MASK)
 150 #define NAK_IN_INT_ENABLED      EP_INT_ENABLED(NAK_IN_INT_ENB_MASK)
 151 #define NAK_OUT_INT_ENABLED     EP_INT_ENABLED(NAK_OUT_INT_ENB_MASK)
 152 #define RX_SETUP_INT_ENABLED    EP_INT_ENABLED(RX_SETUP_INT_ENB_MASK)
 153 #define RX_OUT_INT_ENABLED      EP_INT_ENABLED(RX_OUT_INT_ENB_MASK)
 154
 155 #define EP_INT_CLR(mask)    (UEINTX &= ~mask)
 156 #define TX_IN_INT_CLR()     EP_INT_CLR(TX_IN_INT_MASK)
 157 #define STALL_INT_CLR()     EP_INT_CLR(STALL_INT_MASK)
 158 #define FIFOCON_INT_CLR()   EP_INT_CLR(FIFOCON_INT_MASK)
 159 #define NAK_IN_INT_CLR()    EP_INT_CLR(NAK_IN_INT_MASK)
 160 #define RWAL_INT_CLR()      EP_INT_CLR(RWAL_INT_MASK)
 161 #define NAK_OUT_INT_CLR()   EP_INT_CLR(NAK_OUT_INT_MASK)
 162 #define RX_SETUP_INT_CLR()  EP_INT_CLR(RX_SETUP_INT_MASK)
 163 #define RX_OUT_INT_CLR()    EP_INT_CLR(RX_OUT_INT_MASK)
 164
 165 #define EP_INT_ENB(mask)    (UEIENX |= mask)
 166 #define TX_IN_INT_ENB()     EP_INT_ENB(TX_IN_INT_ENB_MASK)
 167 #define STALL_INT_ENB()     EP_INT_ENB(STALL_INT_ENB_MASK)
 168 #define FLOW_ERR_INT_ENB()  EP_INT_ENB(FLOW_ERR_INT_ENB_MASK)
 169 #define NAK_IN_INT_ENB()    EP_INT_ENB(NAK_IN_INT_ENB_MASK)
 170 #define NAK_OUT_INT_ENB()   EP_INT_ENB(NAK_OUT_INT_ENB_MASK)
 171 #define RX_SETUP_INT_ENB()  EP_INT_ENB(RX_SETUP_INT_ENB_MASK)
 172 #define RX_OUT_INT_ENB()    EP_INT_ENB(RX_OUT_INT_ENB_MASK)
 173
 174 #define EP_INT_DIS(mask)    (UEIENX &= ~mask)
 175 #define TX_IN_INT_DIS()     EP_INT_DIS(TX_IN_INT_ENB_MASK)
 176 #define STALL_INT_DIS()     EP_INT_DIS(STALL_INT_ENB_MASK)
 177 #define FLOW_ERR_INT_DIS()  EP_INT_DIS(FLOW_ERR_INT_ENB_MASK)
 178 #define NAK_IN_INT_DIS()    EP_INT_DIS(NAK_IN_INT_ENB_MASK)
 179 #define NAK_OUT_INT_DIS()   EP_INT_DIS(NAK_OUT_INT_ENB_MASK)
 180 #define RX_SETUP_INT_DIS()  EP_INT_DIS(RX_SETUP_INT_ENB_MASK)
 181 #define RX_OUT_INT_DIS()    EP_INT_DIS(RX_OUT_INT_ENB_MASK)
 182
 183 /** LED mask for the first LED on the board. */
 184 #define LED1    (1 << 4)
 185 #define LED2    (1 << 5)
 186 #define LED3    (1 << 7)
 187 #define LED4    (1 << 6)
 188
 189 #define JOY_BMASK  ((1 << 5) | (1 << 6) | (1 << 7))
 190 #define JOY_EMASK  ((1 << 4) | (1 << 5))
 191
 192 #endif
 193