base/cpu_unittest.cc

   1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #include "base/cpu.h"
   6 #include "build/build_config.h"
   7
   8 #include "testing/gtest/include/gtest/gtest.h"
   9
  10 // Tests whether we can run extended instructions represented by the CPU
  11 // information. This test actually executes some extended instructions (such as
  12 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
  13 // "undefined instruction" exceptions. That is, this test succeeds when this
  14 // test finishes without a crash.
  15 TEST(CPU, RunExtendedInstructions) {
  16 #if defined(ARCH_CPU_X86_FAMILY)
  17   // Retrieve the CPU information.
  18   base::CPU cpu;
  19
  20 #if defined(OS_WIN)
  21   ASSERT_TRUE(cpu.has_mmx());
  22
  23   // Execute an MMX instruction.
  24   __asm emms;
  25
  26   if (cpu.has_sse()) {
  27     // Execute an SSE instruction.
  28     __asm xorps xmm0, xmm0;
  29   }
  30
  31   if (cpu.has_sse2()) {
  32     // Execute an SSE 2 instruction.
  33     __asm psrldq xmm0, 0;
  34   }
  35
  36   if (cpu.has_sse3()) {
  37     // Execute an SSE 3 instruction.
  38     __asm addsubpd xmm0, xmm0;
  39   }
  40
  41   if (cpu.has_ssse3()) {
  42     // Execute a Supplimental SSE 3 instruction.
  43     __asm psignb xmm0, xmm0;
  44   }
  45
  46   if (cpu.has_sse41()) {
  47     // Execute an SSE 4.1 instruction.
  48     __asm pmuldq xmm0, xmm0;
  49   }
  50
  51   if (cpu.has_sse42()) {
  52     // Execute an SSE 4.2 instruction.
  53     __asm crc32 eax, eax;
  54   }
  55 #elif defined(OS_POSIX) && defined(__x86_64__)
  56   ASSERT_TRUE(cpu.has_mmx());
  57
  58   // Execute an MMX instruction.
  59   __asm__ __volatile__("emms\n" : : : "mm0");
  60
  61   if (cpu.has_sse()) {
  62     // Execute an SSE instruction.
  63     __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
  64   }
  65
  66   if (cpu.has_sse2()) {
  67     // Execute an SSE 2 instruction.
  68     __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
  69   }
  70
  71   if (cpu.has_sse3()) {
  72     // Execute an SSE 3 instruction.
  73     __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
  74   }
  75
  76   if (cpu.has_ssse3()) {
  77     // Execute a Supplimental SSE 3 instruction.
  78     __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
  79   }
  80
  81   if (cpu.has_sse41()) {
  82     // Execute an SSE 4.1 instruction.
  83     __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
  84   }
  85
  86   if (cpu.has_sse42()) {
  87     // Execute an SSE 4.2 instruction.
  88     __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
  89   }
  90 #endif
  91 #endif
  92 }