arch/arm/mach-at91/at91sam9rl.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9rl.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *  Copyright (C) 2007 Atmel Corporation
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pm.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <mach/cpu.h>
  19 #include <mach/at91sam9rl.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_rstc.h>
  22 #include <mach/at91_shdwc.h>
  23
  24 #include "generic.h"
  25 #include "clock.h"
  26
  27 static struct map_desc at91sam9rl_io_desc[] __initdata = {
  28         {
  29                 .virtual        = AT91_VA_BASE_SYS,
  30                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  31                 .length         = SZ_16K,
  32                 .type           = MT_DEVICE,
  33         },
  34 };
  35
  36 static struct map_desc at91sam9rl_sram_desc[] __initdata = {
  37         {
  38                 .pfn            = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
  39                 .type           = MT_DEVICE,
  40         }
  41 };
  42
  43 /* --------------------------------------------------------------------
  44  *  Clocks
  45  * -------------------------------------------------------------------- */
  46
  47 /*
  48  * The peripheral clocks.
  49  */
  50 static struct clk pioA_clk = {
  51         .name           = "pioA_clk",
  52         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk pioB_clk = {
  56         .name           = "pioB_clk",
  57         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk pioC_clk = {
  61         .name           = "pioC_clk",
  62         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk pioD_clk = {
  66         .name           = "pioD_clk",
  67         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk usart0_clk = {
  71         .name           = "usart0_clk",
  72         .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk usart1_clk = {
  76         .name           = "usart1_clk",
  77         .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk usart2_clk = {
  81         .name           = "usart2_clk",
  82         .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk usart3_clk = {
  86         .name           = "usart3_clk",
  87         .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk mmc_clk = {
  91         .name           = "mci_clk",
  92         .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk twi0_clk = {
  96         .name           = "twi0_clk",
  97         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk twi1_clk = {
 101         .name           = "twi1_clk",
 102         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk spi_clk = {
 106         .name           = "spi_clk",
 107         .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk ssc0_clk = {
 111         .name           = "ssc0_clk",
 112         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk ssc1_clk = {
 116         .name           = "ssc1_clk",
 117         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk tc0_clk = {
 121         .name           = "tc0_clk",
 122         .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk tc1_clk = {
 126         .name           = "tc1_clk",
 127         .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk tc2_clk = {
 131         .name           = "tc2_clk",
 132         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk pwm_clk = {
 136         .name           = "pwm_clk",
 137         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk tsc_clk = {
 141         .name           = "tsc_clk",
 142         .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk dma_clk = {
 146         .name           = "dma_clk",
 147         .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk udphs_clk = {
 151         .name           = "udphs_clk",
 152         .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 static struct clk lcdc_clk = {
 156         .name           = "lcdc_clk",
 157         .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
 158         .type           = CLK_TYPE_PERIPHERAL,
 159 };
 160 static struct clk ac97_clk = {
 161         .name           = "ac97_clk",
 162         .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
 163         .type           = CLK_TYPE_PERIPHERAL,
 164 };
 165
 166 static struct clk *periph_clocks[] __initdata = {
 167         &pioA_clk,
 168         &pioB_clk,
 169         &pioC_clk,
 170         &pioD_clk,
 171         &usart0_clk,
 172         &usart1_clk,
 173         &usart2_clk,
 174         &usart3_clk,
 175         &mmc_clk,
 176         &twi0_clk,
 177         &twi1_clk,
 178         &spi_clk,
 179         &ssc0_clk,
 180         &ssc1_clk,
 181         &tc0_clk,
 182         &tc1_clk,
 183         &tc2_clk,
 184         &pwm_clk,
 185         &tsc_clk,
 186         &dma_clk,
 187         &udphs_clk,
 188         &lcdc_clk,
 189         &ac97_clk,
 190         // irq0
 191 };
 192
 193 static struct clk_lookup periph_clocks_lookups[] = {
 194         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 195         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 196         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 197         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 198         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 199         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 200         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 201 };
 202
 203 static struct clk_lookup usart_clocks_lookups[] = {
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 206         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 207         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 208         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 209 };
 210
 211 /*
 212  * The two programmable clocks.
 213  * You must configure pin multiplexing to bring these signals out.
 214  */
 215 static struct clk pck0 = {
 216         .name           = "pck0",
 217         .pmc_mask       = AT91_PMC_PCK0,
 218         .type           = CLK_TYPE_PROGRAMMABLE,
 219         .id             = 0,
 220 };
 221 static struct clk pck1 = {
 222         .name           = "pck1",
 223         .pmc_mask       = AT91_PMC_PCK1,
 224         .type           = CLK_TYPE_PROGRAMMABLE,
 225         .id             = 1,
 226 };
 227
 228 static void __init at91sam9rl_register_clocks(void)
 229 {
 230         int i;
 231
 232         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 233                 clk_register(periph_clocks[i]);
 234
 235         clkdev_add_table(periph_clocks_lookups,
 236                          ARRAY_SIZE(periph_clocks_lookups));
 237         clkdev_add_table(usart_clocks_lookups,
 238                          ARRAY_SIZE(usart_clocks_lookups));
 239
 240         clk_register(&pck0);
 241         clk_register(&pck1);
 242 }
 243
 244 static struct clk_lookup console_clock_lookup;
 245
 246 void __init at91sam9rl_set_console_clock(int id)
 247 {
 248         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 249                 return;
 250
 251         console_clock_lookup.con_id = "usart";
 252         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 253         clkdev_add(&console_clock_lookup);
 254 }
 255
 256 /* --------------------------------------------------------------------
 257  *  GPIO
 258  * -------------------------------------------------------------------- */
 259
 260 static struct at91_gpio_bank at91sam9rl_gpio[] = {
 261         {
 262                 .id             = AT91SAM9RL_ID_PIOA,
 263                 .offset         = AT91_PIOA,
 264                 .clock          = &pioA_clk,
 265         }, {
 266                 .id             = AT91SAM9RL_ID_PIOB,
 267                 .offset         = AT91_PIOB,
 268                 .clock          = &pioB_clk,
 269         }, {
 270                 .id             = AT91SAM9RL_ID_PIOC,
 271                 .offset         = AT91_PIOC,
 272                 .clock          = &pioC_clk,
 273         }, {
 274                 .id             = AT91SAM9RL_ID_PIOD,
 275                 .offset         = AT91_PIOD,
 276                 .clock          = &pioD_clk,
 277         }
 278 };
 279
 280 static void at91sam9rl_poweroff(void)
 281 {
 282         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 283 }
 284
 285
 286 /* --------------------------------------------------------------------
 287  *  AT91SAM9RL processor initialization
 288  * -------------------------------------------------------------------- */
 289
 290 void __init at91sam9rl_map_io(void)
 291 {
 292         unsigned long cidr, sram_size;
 293
 294         /* Map peripherals */
 295         iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
 296
 297         cidr = at91_sys_read(AT91_DBGU_CIDR);
 298
 299         switch (cidr & AT91_CIDR_SRAMSIZ) {
 300                 case AT91_CIDR_SRAMSIZ_32K:
 301                         sram_size = 2 * SZ_16K;
 302                         break;
 303                 case AT91_CIDR_SRAMSIZ_16K:
 304                 default:
 305                         sram_size = SZ_16K;
 306         }
 307
 308         at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
 309         at91sam9rl_sram_desc->length = sram_size;
 310
 311         /* Map SRAM */
 312         iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
 313 }
 314
 315 void __init at91sam9rl_initialize(unsigned long main_clock)
 316 {
 317         at91_arch_reset = at91sam9_alt_reset;
 318         pm_power_off = at91sam9rl_poweroff;
 319         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 320
 321         /* Init clock subsystem */
 322         at91_clock_init(main_clock);
 323
 324         /* Register the processor-specific clocks */
 325         at91sam9rl_register_clocks();
 326
 327         /* Register GPIO subsystem */
 328         at91_gpio_init(at91sam9rl_gpio, 4);
 329 }
 330
 331 /* --------------------------------------------------------------------
 332  *  Interrupt initialization
 333  * -------------------------------------------------------------------- */
 334
 335 /*
 336  * The default interrupt priority levels (0 = lowest, 7 = highest).
 337  */
 338 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 339         7,      /* Advanced Interrupt Controller */
 340         7,      /* System Peripherals */
 341         1,      /* Parallel IO Controller A */
 342         1,      /* Parallel IO Controller B */
 343         1,      /* Parallel IO Controller C */
 344         1,      /* Parallel IO Controller D */
 345         5,      /* USART 0 */
 346         5,      /* USART 1 */
 347         5,      /* USART 2 */
 348         5,      /* USART 3 */
 349         0,      /* Multimedia Card Interface */
 350         6,      /* Two-Wire Interface 0 */
 351         6,      /* Two-Wire Interface 1 */
 352         5,      /* Serial Peripheral Interface */
 353         4,      /* Serial Synchronous Controller 0 */
 354         4,      /* Serial Synchronous Controller 1 */
 355         0,      /* Timer Counter 0 */
 356         0,      /* Timer Counter 1 */
 357         0,      /* Timer Counter 2 */
 358         0,
 359         0,      /* Touch Screen Controller */
 360         0,      /* DMA Controller */
 361         2,      /* USB Device High speed port */
 362         2,      /* LCD Controller */
 363         6,      /* AC97 Controller */
 364         0,
 365         0,
 366         0,
 367         0,
 368         0,
 369         0,
 370         0,      /* Advanced Interrupt Controller */
 371 };
 372
 373 void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 374 {
 375         if (!priority)
 376                 priority = at91sam9rl_default_irq_priority;
 377
 378         /* Initialize the AIC interrupt controller */
 379         at91_aic_init(priority);
 380
 381         /* Enable GPIO interrupts */
 382         at91_gpio_irq_setup();
 383 }