arch/arm/mach-imx/ehci-imx35.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/mxc_ehci.h>
  21
  22 #define USBCTRL_OTGBASE_OFFSET  0x600
  23
  24 #define MX35_OTG_SIC_SHIFT      29
  25 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
  26 #define MX35_OTG_PM_BIT         (1 << 24)
  27
  28 #define MX35_H1_SIC_SHIFT       21
  29 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
  30 #define MX35_H1_PM_BIT          (1 << 8)
  31 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
  32 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
  33 #define MX35_H1_TLL_BIT         (1 << 5)
  34 #define MX35_H1_USBTE_BIT       (1 << 4)
  35
  36 int mx35_initialize_usb_hw(int port, unsigned int flags)
  37 {
  38         unsigned int v;
  39
  40         v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  41
  42         switch (port) {
  43         case 0: /* OTG port */
  44                 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
  45                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
  46
  47                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  48                         v |= MX35_OTG_PM_BIT;
  49
  50                 break;
  51         case 1: /* H1 port */
  52                 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
  53                         MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
  54                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
  55
  56                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  57                         v |= MX35_H1_PM_BIT;
  58
  59                 if (!(flags & MXC_EHCI_TTL_ENABLED))
  60                         v |= MX35_H1_TLL_BIT;
  61
  62                 if (flags & MXC_EHCI_INTERNAL_PHY)
  63                         v |= MX35_H1_USBTE_BIT;
  64
  65                 if (flags & MXC_EHCI_IPPUE_DOWN)
  66                         v |= MX35_H1_IPPUE_DOWN_BIT;
  67
  68                 if (flags & MXC_EHCI_IPPUE_UP)
  69                         v |= MX35_H1_IPPUE_UP_BIT;
  70
  71                 break;
  72         default:
  73                 return -EINVAL;
  74         }
  75
  76         writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  77
  78         return 0;
  79 }