arch/arm/mach-omap2/board-tuna-emif.c

   1 /*
   2  * LPDDR2 data as per SAMSUNG data sheet
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *
   6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/init.h>
  14
  15 #include <mach/emif.h>
  16 #include "board-tuna.h"
  17
  18 const struct lpddr2_timings lpddr2_samsung_timings_400_mhz = {
  19         .max_freq       = 400000000,
  20         .RL             = 6,
  21         .tRPab          = 21,
  22         .tRCD           = 18,
  23         .tWR            = 15,
  24         .tRASmin        = 42,
  25         .tRRD           = 10,
  26         .tWTRx2         = 15,
  27         .tXSR           = 140,
  28         .tXPx2          = 15,
  29         .tRFCab         = 130,
  30         .tRTPx2         = 15,
  31         .tCKE           = 3,
  32         .tCKESR         = 15,
  33         .tZQCS          = 90,
  34         .tZQCL          = 360,
  35         .tZQINIT        = 1000,
  36         .tDQSCKMAXx2    = 11,
  37         .tRASmax        = 70,
  38         .tFAW           = 50,
  39 };
  40
  41 const struct lpddr2_timings lpddr2_samsung_timings_200_mhz = {
  42         .max_freq       = 200000000,
  43         .RL             = 3,
  44         .tRPab          = 21,
  45         .tRCD           = 18,
  46         .tWR            = 15,
  47         .tRASmin        = 42,
  48         .tRRD           = 10,
  49         .tWTRx2         = 20,
  50         .tXSR           = 140,
  51         .tXPx2          = 15,
  52         .tRFCab         = 130,
  53         .tRTPx2         = 15,
  54         .tCKE           = 3,
  55         .tCKESR         = 15,
  56         .tZQCS          = 90,
  57         .tZQCL          = 360,
  58         .tZQINIT        = 1000,
  59         .tDQSCKMAXx2    = 11,
  60         .tRASmax        = 70,
  61         .tFAW           = 50,
  62 };
  63
  64 const struct lpddr2_min_tck lpddr2_samsung_min_tck = {
  65         .tRL            = 3,
  66         .tRP_AB         = 3,
  67         .tRCD           = 3,
  68         .tWR            = 3,
  69         .tRAS_MIN       = 3,
  70         .tRRD           = 2,
  71         .tWTR           = 2,
  72         .tXP            = 2,
  73         .tRTP           = 2,
  74         .tCKE           = 3,
  75         .tCKESR         = 3,
  76         .tFAW           = 8
  77 };
  78
  79 struct lpddr2_device_info lpddr2_samsung_4G_S4_dev = {
  80         .device_timings = {
  81                 &lpddr2_samsung_timings_200_mhz,
  82                 &lpddr2_samsung_timings_400_mhz
  83         },
  84         .min_tck        = &lpddr2_samsung_min_tck,
  85         .type           = LPDDR2_TYPE_S4,
  86         .density        = LPDDR2_DENSITY_4Gb,
  87         .io_width       = LPDDR2_IO_WIDTH_32,
  88         .emif_ddr_selfrefresh_cycles = 262144,
  89 };
  90
  91 /*
  92  * LPDDR2 Configuration Data:
  93  * The memory organisation is as below :
  94  *      EMIF1 - CS0 -   4 Gb
  95  *      EMIF2 - CS0 -   4 Gb
  96  *      --------------------
  97  *      TOTAL -         8 Gb
  98  *
  99  * Same devices installed on EMIF1 and EMIF2
 100  */
 101 static __initdata struct emif_device_details emif_devices = {
 102         .cs0_device = &lpddr2_samsung_4G_S4_dev,
 103 };
 104
 105 void __init omap4_tuna_emif_init(void)
 106 {
 107         omap_emif_setup_device_details(&emif_devices, &emif_devices);
 108 }