2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
32 #include <plat/clock.h>
36 #include "cm2xxx_3xxx.h"
37 #include "cm-regbits-34xx.h"
38 #include "cm-regbits-44xx.h"
40 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
41 #define DPLL_AUTOIDLE_DISABLE 0x0
42 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
44 #define MAX_DPLL_WAIT_TRIES 1000000
46 /* Private functions */
48 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
49 static void _omap3_dpll_write_clken(struct clk
*clk
, u8 clken_bits
)
51 const struct dpll_data
*dd
;
56 v
= __raw_readl(dd
->control_reg
);
57 v
&= ~dd
->enable_mask
;
58 v
|= clken_bits
<< __ffs(dd
->enable_mask
);
59 __raw_writel(v
, dd
->control_reg
);
62 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
63 static int _omap3_wait_dpll_status(struct clk
*clk
, u8 state
)
65 const struct dpll_data
*dd
;
68 bool first_time
= true;
70 u32 orig_cm_div_m2_dpll_usb
;
71 u32 orig_cm_clkdcoldo_dpll_usb
;
76 state
<<= __ffs(dd
->idlest_mask
);
79 while (((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) != state
) &&
80 i
< MAX_DPLL_WAIT_TRIES
) {
85 /* restore back old values if hit work-around */
87 __raw_writel(orig_cm_div_m2_dpll_usb
,
88 OMAP4430_CM_DIV_M2_DPLL_USB
);
89 __raw_writel(orig_cm_clkdcoldo_dpll_usb
,
90 OMAP4430_CM_CLKDCOLDO_DPLL_USB
);
93 if (i
== MAX_DPLL_WAIT_TRIES
) {
94 printk(KERN_ERR
"clock: %s failed transition to '%s'\n",
95 clk
->name
, (state
) ? "locked" : "bypassed");
97 /* Try Error Recovery: for failing usbdpll locking */
98 if (!strcmp(clk
->name
, "dpll_usb_ck")) {
99 reg
= __raw_readl(dd
->mult_div1_reg
);
101 /* Put in MN bypass */
102 _omap3_dpll_write_clken(clk
, DPLL_MN_BYPASS
);
104 while (!(__raw_readl(dd
->idlest_reg
) & (1 << OMAP4430_ST_MN_BYPASS_SHIFT
)) &&
105 i
< MAX_DPLL_WAIT_TRIES
) {
110 /* MN bypass looses contents of CM_CLKSEL_DPLL_USB */
111 __raw_writel(reg
, dd
->mult_div1_reg
);
113 /* Force generate request to PRCM: put in Force mode */
115 /* a) CM_DIV_M2_DPLL_USB.DPLL_CLKOUT_GATE_CTRL = 1 */
116 orig_cm_div_m2_dpll_usb
= __raw_readl(OMAP4430_CM_DIV_M2_DPLL_USB
);
117 __raw_writel(orig_cm_div_m2_dpll_usb
|
118 (1 << OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT
),
119 OMAP4430_CM_DIV_M2_DPLL_USB
);
121 /* b) CM_CLKDCOLDO_DPLL_USB.DPLL_CLKDCOLDO_GATE_CTRL = 1 */
122 orig_cm_clkdcoldo_dpll_usb
= __raw_readl(OMAP4430_CM_CLKDCOLDO_DPLL_USB
);
123 __raw_writel(orig_cm_clkdcoldo_dpll_usb
|
124 (1 << OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT
),
125 OMAP4430_CM_CLKDCOLDO_DPLL_USB
);
127 /* Put back to locked mode */
128 _omap3_dpll_write_clken(clk
, DPLL_LOCKED
);
135 pr_info("\n========== USB DPLL DUMP ===========\n");
136 pr_info("CM_CLKMODE_DPLL_USB :%08x\n", omap_readl(0x4A008180));
137 pr_info("CM_IDLEST_DPLL_USB :%08x\n", omap_readl(0x4A008184));
138 pr_info("CM_AUTOIDLE_DPLL_USB :%08x\n", omap_readl(0x4A008188));
139 pr_info("CM_CLKSEL_DPLL_USB :%08x\n", omap_readl(0x4A00818C));
140 pr_info("CM_DIV_M2_DPLL_USB :%08x\n", omap_readl(0x4A008190));
141 pr_info("CM_SSC_DELTAMSTEP_DPLL_USB :%08x\n", omap_readl(0x4A0081A8));
142 pr_info("CM_SSC_MODFREQDIV_DPLL_USB :%08x\n", omap_readl(0x4A0081AC));
143 pr_info("CM_CLKDCOLDO_DPLL_USB :%08x\n", omap_readl(0x4A0081B4));
144 pr_info("========== USB DPLL DUMP: End ===========\n");
147 pr_debug("clock: %s transition to '%s' in %d loops\n",
148 clk
->name
, (state
) ? "locked" : "bypassed", i
);
156 /* From 3430 TRM ES2 4.7.6.2 */
157 static u16
_omap3_dpll_compute_freqsel(struct clk
*clk
, u8 n
)
162 fint
= clk
->dpll_data
->clk_ref
->rate
/ n
;
164 pr_debug("clock: fint is %lu\n", fint
);
166 if (fint
>= 750000 && fint
<= 1000000)
168 else if (fint
> 1000000 && fint
<= 1250000)
170 else if (fint
> 1250000 && fint
<= 1500000)
172 else if (fint
> 1500000 && fint
<= 1750000)
174 else if (fint
> 1750000 && fint
<= 2100000)
176 else if (fint
> 7500000 && fint
<= 10000000)
178 else if (fint
> 10000000 && fint
<= 12500000)
180 else if (fint
> 12500000 && fint
<= 15000000)
182 else if (fint
> 15000000 && fint
<= 17500000)
184 else if (fint
> 17500000 && fint
<= 21000000)
187 pr_debug("clock: unknown freqsel setting for %d\n", n
);
193 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
194 * @clk: pointer to a DPLL struct clk
196 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
197 * readiness before returning. Will save and restore the DPLL's
198 * autoidle state across the enable, per the CDP code. If the DPLL
199 * locked successfully, return 0; if the DPLL did not lock in the time
200 * allotted, or DPLL3 was passed in, return -EINVAL.
202 static int _omap3_noncore_dpll_lock(struct clk
*clk
)
204 const struct dpll_data
*dd
;
209 pr_debug("clock: locking DPLL %s\n", clk
->name
);
212 state
<<= __ffs(dd
->idlest_mask
);
214 /* Check if already locked */
215 if ((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) == state
)
218 ai
= omap3_dpll_autoidle_read(clk
);
220 omap3_dpll_deny_idle(clk
);
222 _omap3_dpll_write_clken(clk
, DPLL_LOCKED
);
224 r
= _omap3_wait_dpll_status(clk
, 1);
227 omap3_dpll_allow_idle(clk
);
234 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
235 * @clk: pointer to a DPLL struct clk
237 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
238 * bypass mode, the DPLL's rate is set equal to its parent clock's
239 * rate. Waits for the DPLL to report readiness before returning.
240 * Will save and restore the DPLL's autoidle state across the enable,
241 * per the CDP code. If the DPLL entered bypass mode successfully,
242 * return 0; if the DPLL did not enter bypass in the time allotted, or
243 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
246 static int _omap3_noncore_dpll_bypass(struct clk
*clk
)
251 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
)))
254 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
257 ai
= omap3_dpll_autoidle_read(clk
);
259 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_BYPASS
);
261 r
= _omap3_wait_dpll_status(clk
, 0);
264 omap3_dpll_allow_idle(clk
);
266 omap3_dpll_deny_idle(clk
);
272 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
273 * @clk: pointer to a DPLL struct clk
275 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
276 * restore the DPLL's autoidle state across the stop, per the CDP
277 * code. If DPLL3 was passed in, or the DPLL does not support
278 * low-power stop, return -EINVAL; otherwise, return 0.
280 static int _omap3_noncore_dpll_stop(struct clk
*clk
)
284 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_STOP
)))
287 pr_debug("clock: stopping DPLL %s\n", clk
->name
);
289 ai
= omap3_dpll_autoidle_read(clk
);
291 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_STOP
);
294 omap3_dpll_allow_idle(clk
);
296 omap3_dpll_deny_idle(clk
);
302 * _lookup_dco - Lookup DCO used by j-type DPLL
303 * @clk: pointer to a DPLL struct clk
304 * @dco: digital control oscillator selector
305 * @m: DPLL multiplier to set
306 * @n: DPLL divider to set
308 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
310 * XXX This code is not needed for 3430/AM35xx; can it be optimized
311 * out in non-multi-OMAP builds for those chips?
313 static void _lookup_dco(struct clk
*clk
, u8
*dco
, u16 m
, u8 n
)
315 unsigned long fint
, clkinp
; /* watch out for overflow */
317 clkinp
= clk
->parent
->rate
;
318 fint
= (clkinp
/ n
) * m
;
320 if (fint
< 1000000000)
327 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
328 * @clk: pointer to a DPLL struct clk
329 * @sd_div: target sigma-delta divider
330 * @m: DPLL multiplier to set
331 * @n: DPLL divider to set
333 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
335 * XXX This code is not needed for 3430/AM35xx; can it be optimized
336 * out in non-multi-OMAP builds for those chips?
338 static void _lookup_sddiv(struct clk
*clk
, u8
*sd_div
, u16 m
, u8 n
)
340 unsigned long clkinp
, sd
; /* watch out for overflow */
343 clkinp
= clk
->parent
->rate
;
346 * target sigma-delta to near 250MHz
347 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
349 clkinp
/= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
350 mod1
= (clkinp
* m
) % (250 * n
);
351 sd
= (clkinp
* m
) / (250 * n
);
361 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
362 * @clk: struct clk * of DPLL to set
363 * @m: DPLL multiplier to set
364 * @n: DPLL divider to set
365 * @freqsel: FREQSEL value to set
367 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
368 * lock.. Returns -EINVAL upon error, or 0 upon success.
370 static int omap3_noncore_dpll_program(struct clk
*clk
, u16 m
, u8 n
, u16 freqsel
)
372 struct dpll_data
*dd
= clk
->dpll_data
;
376 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
377 _omap3_noncore_dpll_bypass(clk
);
380 * Set jitter correction. No jitter correction for OMAP4 and 3630
381 * since freqsel field is no longer present
383 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
384 v
= __raw_readl(dd
->control_reg
);
385 v
&= ~dd
->freqsel_mask
;
386 v
|= freqsel
<< __ffs(dd
->freqsel_mask
);
387 __raw_writel(v
, dd
->control_reg
);
390 /* Set DPLL multiplier, divider */
391 v
= __raw_readl(dd
->mult_div1_reg
);
392 v
&= ~(dd
->mult_mask
| dd
->div1_mask
);
393 v
|= m
<< __ffs(dd
->mult_mask
);
394 v
|= (n
- 1) << __ffs(dd
->div1_mask
);
396 /* Configure dco and sd_div for dplls that have these fields */
398 _lookup_dco(clk
, &dco
, m
, n
);
399 v
&= ~(dd
->dco_mask
);
400 v
|= dco
<< __ffs(dd
->dco_mask
);
402 if (dd
->sddiv_mask
) {
403 _lookup_sddiv(clk
, &sd_div
, m
, n
);
404 v
&= ~(dd
->sddiv_mask
);
405 v
|= sd_div
<< __ffs(dd
->sddiv_mask
);
408 __raw_writel(v
, dd
->mult_div1_reg
);
410 /* We let the clock framework set the other output dividers later */
412 /* REVISIT: Set ramp-up delay? */
414 _omap3_noncore_dpll_lock(clk
);
419 /* Public functions */
422 * omap3_dpll_recalc - recalculate DPLL rate
423 * @clk: DPLL struct clk
425 * Recalculate and propagate the DPLL rate.
427 unsigned long omap3_dpll_recalc(struct clk
*clk
)
429 return omap2_get_dpll_rate(clk
);
432 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
435 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
436 * @clk: pointer to a DPLL struct clk
438 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
439 * The choice of modes depends on the DPLL's programmed rate: if it is
440 * the same as the DPLL's parent clock, it will enter bypass;
441 * otherwise, it will enter lock. This code will wait for the DPLL to
442 * indicate readiness before returning, unless the DPLL takes too long
443 * to enter the target state. Intended to be used as the struct clk's
444 * enable function. If DPLL3 was passed in, or the DPLL does not
445 * support low-power stop, or if the DPLL took too long to enter
446 * bypass or lock, return -EINVAL; otherwise, return 0.
448 int omap3_noncore_dpll_enable(struct clk
*clk
)
451 struct dpll_data
*dd
;
457 if (clk
->rate
== dd
->clk_bypass
->rate
) {
458 WARN_ON(clk
->parent
!= dd
->clk_bypass
);
459 r
= _omap3_noncore_dpll_bypass(clk
);
461 WARN_ON(clk
->parent
!= dd
->clk_ref
);
462 r
= _omap3_noncore_dpll_lock(clk
);
465 *FIXME: this is dubious - if clk->rate has changed, what about
469 clk
->rate
= omap2_get_dpll_rate(clk
);
475 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
476 * @clk: pointer to a DPLL struct clk
478 * Instructs a non-CORE DPLL to enter low-power stop. This function is
479 * intended for use in struct clkops. No return value.
481 void omap3_noncore_dpll_disable(struct clk
*clk
)
483 _omap3_noncore_dpll_stop(clk
);
487 /* Non-CORE DPLL rate set code */
490 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
491 * @clk: struct clk * of DPLL to set
492 * @rate: rounded target rate
494 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
495 * low-power bypass, and the target rate is the bypass source clock
496 * rate, then configure the DPLL for bypass. Otherwise, round the
497 * target rate if it hasn't been done already, then program and lock
498 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
500 int omap3_noncore_dpll_set_rate(struct clk
*clk
, unsigned long rate
)
502 struct clk
*new_parent
= NULL
;
504 struct dpll_data
*dd
;
514 if (rate
== omap2_get_dpll_rate(clk
))
518 * Ensure both the bypass and ref clocks are enabled prior to
519 * doing anything; we need the bypass clock running to reprogram
522 omap2_clk_enable(dd
->clk_bypass
);
523 omap2_clk_enable(dd
->clk_ref
);
525 if (dd
->clk_bypass
->rate
== rate
&&
526 (clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
))) {
527 pr_debug("clock: %s: set rate: entering bypass.\n", clk
->name
);
529 ret
= _omap3_noncore_dpll_bypass(clk
);
531 new_parent
= dd
->clk_bypass
;
533 if (dd
->last_rounded_rate
!= rate
)
534 rate
= clk
->round_rate(clk
, rate
);
536 if (dd
->last_rounded_rate
== 0)
539 /* No freqsel on OMAP4 and OMAP3630 */
540 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
541 freqsel
= _omap3_dpll_compute_freqsel(clk
,
547 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
550 ret
= omap3_noncore_dpll_program(clk
, dd
->last_rounded_m
,
551 dd
->last_rounded_n
, freqsel
);
553 new_parent
= dd
->clk_ref
;
557 * Switch the parent clock in the hierarchy, and make sure
558 * that the new parent's usecount is correct. Note: we
559 * enable the new parent before disabling the old to avoid
560 * any unnecessary hardware disable->enable transitions.
563 omap2_clk_enable(new_parent
);
564 omap2_clk_disable(clk
->parent
);
566 clk_reparent(clk
, new_parent
);
569 omap2_clk_disable(dd
->clk_ref
);
570 omap2_clk_disable(dd
->clk_bypass
);
575 /* DPLL autoidle read/set code */
578 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
579 * @clk: struct clk * of the DPLL to read
581 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
582 * -EINVAL if passed a null pointer or if the struct clk does not
583 * appear to refer to a DPLL.
585 u32
omap3_dpll_autoidle_read(struct clk
*clk
)
587 const struct dpll_data
*dd
;
590 if (!clk
|| !clk
->dpll_data
)
595 v
= __raw_readl(dd
->autoidle_reg
);
596 v
&= dd
->autoidle_mask
;
597 v
>>= __ffs(dd
->autoidle_mask
);
603 * omap3_dpll_allow_idle - enable DPLL autoidle bits
604 * @clk: struct clk * of the DPLL to operate on
606 * Enable DPLL automatic idle control. This automatic idle mode
607 * switching takes effect only when the DPLL is locked, at least on
608 * OMAP3430. The DPLL will enter low-power stop when its downstream
609 * clocks are gated. No return value.
611 void omap3_dpll_allow_idle(struct clk
*clk
)
613 const struct dpll_data
*dd
;
616 if (!clk
|| !clk
->dpll_data
)
622 * REVISIT: CORE DPLL can optionally enter low-power bypass
623 * by writing 0x5 instead of 0x1. Add some mechanism to
624 * optionally enter this mode.
626 v
= __raw_readl(dd
->autoidle_reg
);
627 v
&= ~dd
->autoidle_mask
;
628 v
|= DPLL_AUTOIDLE_LOW_POWER_STOP
<< __ffs(dd
->autoidle_mask
);
629 __raw_writel(v
, dd
->autoidle_reg
);
633 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
634 * @clk: struct clk * of the DPLL to operate on
636 * Disable DPLL automatic idle control. No return value.
638 void omap3_dpll_deny_idle(struct clk
*clk
)
640 const struct dpll_data
*dd
;
643 if (!clk
|| !clk
->dpll_data
)
648 v
= __raw_readl(dd
->autoidle_reg
);
649 v
&= ~dd
->autoidle_mask
;
650 v
|= DPLL_AUTOIDLE_DISABLE
<< __ffs(dd
->autoidle_mask
);
651 __raw_writel(v
, dd
->autoidle_reg
);
655 /* Clock control for DPLL outputs */
658 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
659 * @clk: DPLL output struct clk
661 * Using parent clock DPLL data, look up DPLL state. If locked, set our
662 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
664 unsigned long omap3_clkoutx2_recalc(struct clk
*clk
)
666 const struct dpll_data
*dd
;
671 /* Walk up the parents of clk, looking for a DPLL */
673 while (pclk
&& !pclk
->dpll_data
)
676 /* clk does not have a DPLL as a parent? */
679 dd
= pclk
->dpll_data
;
681 WARN_ON(!dd
->enable_mask
);
683 v
= __raw_readl(dd
->control_reg
) & dd
->enable_mask
;
684 v
>>= __ffs(dd
->enable_mask
);
685 if ((v
!= OMAP3XXX_EN_DPLL_LOCKED
) || (dd
->flags
& DPLL_J_TYPE
))
686 rate
= clk
->parent
->rate
;
688 rate
= clk
->parent
->rate
* 2;