2 * linux/arch/arm/mach-omap2/hsmmc.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <mach/hardware.h>
18 #include <plat/omap-pm.h>
20 #include <plat/omap_device.h>
26 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
28 static u16 control_pbias_offset
;
29 static u16 control_devconf1_offset
;
30 static u16 control_mmc1
;
32 #define HSMMC_NAME_LEN 9
35 static void omap_hsmmc1_before_set_reg(struct device
*dev
, int slot
,
36 int power_on
, int vdd
)
39 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
41 if (mmc
->slots
[0].remux
)
42 mmc
->slots
[0].remux(dev
, slot
, power_on
);
45 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
46 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
47 * 1.8V and 3.0V modes, controlled by the PBIAS register.
49 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
50 * is most naturally TWL VSIM; those pins also use PBIAS.
52 * FIXME handle VMMC1A as needed ...
55 if (cpu_is_omap2430()) {
56 reg
= omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1
);
57 if ((1 << vdd
) >= MMC_VDD_30_31
)
58 reg
|= OMAP243X_MMC1_ACTIVE_OVERWRITE
;
60 reg
&= ~OMAP243X_MMC1_ACTIVE_OVERWRITE
;
61 omap_ctrl_writel(reg
, OMAP243X_CONTROL_DEVCONF1
);
64 if (mmc
->slots
[0].internal_clock
) {
65 reg
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
);
66 reg
|= OMAP2_MMCSDIO1ADPCLKISEL
;
67 omap_ctrl_writel(reg
, OMAP2_CONTROL_DEVCONF0
);
70 reg
= omap_ctrl_readl(control_pbias_offset
);
71 if (cpu_is_omap3630()) {
72 /* Set MMC I/O to 52Mhz */
73 prog_io
= omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1
);
74 prog_io
|= OMAP3630_PRG_SDMMC1_SPEEDCTRL
;
75 omap_ctrl_writel(prog_io
, OMAP343X_CONTROL_PROG_IO1
);
77 reg
|= OMAP2_PBIASSPEEDCTRL0
;
79 reg
&= ~OMAP2_PBIASLITEPWRDNZ0
;
80 omap_ctrl_writel(reg
, control_pbias_offset
);
82 reg
= omap_ctrl_readl(control_pbias_offset
);
83 reg
&= ~OMAP2_PBIASLITEPWRDNZ0
;
84 omap_ctrl_writel(reg
, control_pbias_offset
);
88 static void omap_hsmmc1_after_set_reg(struct device
*dev
, int slot
,
89 int power_on
, int vdd
)
93 /* 100ms delay required for PBIAS configuration */
97 reg
= omap_ctrl_readl(control_pbias_offset
);
98 reg
|= (OMAP2_PBIASLITEPWRDNZ0
| OMAP2_PBIASSPEEDCTRL0
);
99 if ((1 << vdd
) <= MMC_VDD_165_195
)
100 reg
&= ~OMAP2_PBIASLITEVMODE0
;
102 reg
|= OMAP2_PBIASLITEVMODE0
;
103 omap_ctrl_writel(reg
, control_pbias_offset
);
105 reg
= omap_ctrl_readl(control_pbias_offset
);
106 reg
|= (OMAP2_PBIASSPEEDCTRL0
| OMAP2_PBIASLITEPWRDNZ0
|
107 OMAP2_PBIASLITEVMODE0
);
108 omap_ctrl_writel(reg
, control_pbias_offset
);
112 static void omap4_hsmmc1_before_set_reg(struct device
*dev
, int slot
,
113 int power_on
, int vdd
)
118 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
119 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
120 * 1.8V and 3.0V modes, controlled by the PBIAS register.
122 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
123 * is most naturally TWL VSIM; those pins also use PBIAS.
125 * FIXME handle VMMC1A as needed ...
127 reg
= omap4_ctrl_pad_readl(control_pbias_offset
);
128 reg
&= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK
|
129 OMAP4_MMC1_PWRDNZ_MASK
|
130 OMAP4_USBC1_ICUSB_PWRDNZ_MASK
);
131 omap4_ctrl_pad_writel(reg
, control_pbias_offset
);
134 static void omap4_hsmmc1_after_set_reg(struct device
*dev
, int slot
,
135 int power_on
, int vdd
)
138 unsigned long timeout
;
141 reg
= omap4_ctrl_pad_readl(control_pbias_offset
);
142 reg
|= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK
;
143 if ((1 << vdd
) <= MMC_VDD_165_195
)
144 reg
&= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK
;
146 reg
|= OMAP4_MMC1_PBIASLITE_VMODE_MASK
;
147 reg
|= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK
|
148 OMAP4_MMC1_PWRDNZ_MASK
|
149 OMAP4_USBC1_ICUSB_PWRDNZ_MASK
);
150 omap4_ctrl_pad_writel(reg
, control_pbias_offset
);
152 timeout
= jiffies
+ msecs_to_jiffies(5);
154 reg
= omap4_ctrl_pad_readl(control_pbias_offset
);
155 if (!(reg
& OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK
))
157 usleep_range(100, 200);
158 } while (!time_after(jiffies
, timeout
));
160 if (reg
& OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK
) {
161 pr_err("Pbias Voltage is not same as LDO\n");
162 /* Caution : On VMODE_ERROR Power Down MMC IO */
163 reg
&= ~(OMAP4_MMC1_PWRDNZ_MASK
|
164 OMAP4_USBC1_ICUSB_PWRDNZ_MASK
);
165 omap4_ctrl_pad_writel(reg
, control_pbias_offset
);
168 reg
= omap4_ctrl_pad_readl(control_pbias_offset
);
169 reg
|= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK
|
170 OMAP4_MMC1_PWRDNZ_MASK
|
171 OMAP4_MMC1_PBIASLITE_VMODE_MASK
|
172 OMAP4_USBC1_ICUSB_PWRDNZ_MASK
);
173 omap4_ctrl_pad_writel(reg
, control_pbias_offset
);
177 static void hsmmc23_before_set_reg(struct device
*dev
, int slot
,
178 int power_on
, int vdd
)
180 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
182 if (mmc
->slots
[0].remux
)
183 mmc
->slots
[0].remux(dev
, slot
, power_on
);
186 /* Only MMC2 supports a CLKIN */
187 if (mmc
->slots
[0].internal_clock
) {
190 reg
= omap_ctrl_readl(control_devconf1_offset
);
191 reg
|= OMAP2_MMCSDIO2ADPCLKISEL
;
192 omap_ctrl_writel(reg
, control_devconf1_offset
);
197 static int nop_mmc_set_power(struct device
*dev
, int slot
, int power_on
,
203 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data
*mmc_controller
,
206 if ((mmc_controller
->slots
[0].switch_pin
> 0) && \
207 (mmc_controller
->slots
[0].switch_pin
< OMAP_MAX_GPIO_LINES
))
208 omap_mux_init_gpio(mmc_controller
->slots
[0].switch_pin
,
209 OMAP_PIN_INPUT_PULLUP
);
210 if ((mmc_controller
->slots
[0].gpio_wp
> 0) && \
211 (mmc_controller
->slots
[0].gpio_wp
< OMAP_MAX_GPIO_LINES
))
212 omap_mux_init_gpio(mmc_controller
->slots
[0].gpio_wp
,
213 OMAP_PIN_INPUT_PULLUP
);
214 if (cpu_is_omap34xx()) {
215 if (controller_nr
== 0) {
216 omap_mux_init_signal("sdmmc1_clk",
217 OMAP_PIN_INPUT_PULLUP
);
218 omap_mux_init_signal("sdmmc1_cmd",
219 OMAP_PIN_INPUT_PULLUP
);
220 omap_mux_init_signal("sdmmc1_dat0",
221 OMAP_PIN_INPUT_PULLUP
);
222 if (mmc_controller
->slots
[0].caps
&
223 (MMC_CAP_4_BIT_DATA
| MMC_CAP_8_BIT_DATA
)) {
224 omap_mux_init_signal("sdmmc1_dat1",
225 OMAP_PIN_INPUT_PULLUP
);
226 omap_mux_init_signal("sdmmc1_dat2",
227 OMAP_PIN_INPUT_PULLUP
);
228 omap_mux_init_signal("sdmmc1_dat3",
229 OMAP_PIN_INPUT_PULLUP
);
231 if (mmc_controller
->slots
[0].caps
&
232 MMC_CAP_8_BIT_DATA
) {
233 omap_mux_init_signal("sdmmc1_dat4",
234 OMAP_PIN_INPUT_PULLUP
);
235 omap_mux_init_signal("sdmmc1_dat5",
236 OMAP_PIN_INPUT_PULLUP
);
237 omap_mux_init_signal("sdmmc1_dat6",
238 OMAP_PIN_INPUT_PULLUP
);
239 omap_mux_init_signal("sdmmc1_dat7",
240 OMAP_PIN_INPUT_PULLUP
);
243 if (controller_nr
== 1) {
245 omap_mux_init_signal("sdmmc2_clk",
246 OMAP_PIN_INPUT_PULLUP
);
247 omap_mux_init_signal("sdmmc2_cmd",
248 OMAP_PIN_INPUT_PULLUP
);
249 omap_mux_init_signal("sdmmc2_dat0",
250 OMAP_PIN_INPUT_PULLUP
);
253 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
254 * need to be muxed in the board-*.c files
256 if (mmc_controller
->slots
[0].caps
&
257 (MMC_CAP_4_BIT_DATA
| MMC_CAP_8_BIT_DATA
)) {
258 omap_mux_init_signal("sdmmc2_dat1",
259 OMAP_PIN_INPUT_PULLUP
);
260 omap_mux_init_signal("sdmmc2_dat2",
261 OMAP_PIN_INPUT_PULLUP
);
262 omap_mux_init_signal("sdmmc2_dat3",
263 OMAP_PIN_INPUT_PULLUP
);
265 if (mmc_controller
->slots
[0].caps
&
266 MMC_CAP_8_BIT_DATA
) {
267 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
268 OMAP_PIN_INPUT_PULLUP
);
269 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
270 OMAP_PIN_INPUT_PULLUP
);
271 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
272 OMAP_PIN_INPUT_PULLUP
);
273 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
274 OMAP_PIN_INPUT_PULLUP
);
279 * For MMC3 the pins need to be muxed in the board-*.c files
284 static int __init
omap_hsmmc_pdata_init(struct omap2_hsmmc_info
*c
,
285 struct omap_mmc_platform_data
*mmc
)
289 hc_name
= kzalloc(sizeof(char) * (HSMMC_NAME_LEN
+ 1), GFP_KERNEL
);
291 pr_err("Cannot allocate memory for controller slot name\n");
297 strncpy(hc_name
, c
->name
, HSMMC_NAME_LEN
);
299 snprintf(hc_name
, (HSMMC_NAME_LEN
+ 1), "mmc%islot%i",
301 mmc
->slots
[0].name
= hc_name
;
303 mmc
->slots
[0].caps
= c
->caps
;
304 mmc
->slots
[0].internal_clock
= !c
->ext_clock
;
305 mmc
->dma_mask
= 0xffffffff;
306 if (cpu_is_omap44xx())
307 mmc
->reg_offset
= OMAP4_MMC_REG_OFFSET
;
311 mmc
->slots
[0].switch_pin
= c
->gpio_cd
;
312 mmc
->slots
[0].gpio_wp
= c
->gpio_wp
;
314 mmc
->slots
[0].remux
= c
->remux
;
315 mmc
->slots
[0].init_card
= c
->init_card
;
318 mmc
->slots
[0].cover
= 1;
321 mmc
->slots
[0].nonremovable
= 1;
324 mmc
->slots
[0].power_saving
= 1;
327 mmc
->slots
[0].no_off
= 1;
330 mmc
->slots
[0].no_regulator_off_init
= c
->no_off_init
;
332 if (c
->vcc_aux_disable_is_sleep
)
333 mmc
->slots
[0].vcc_aux_disable_is_sleep
= 1;
335 if (cpu_is_omap44xx()) {
336 if (omap_rev() > OMAP4430_REV_ES1_0
)
337 mmc
->slots
[0].features
|= HSMMC_HAS_UPDATED_RESET
;
338 if (c
->mmc
>= 3 && c
->mmc
<= 5)
339 mmc
->slots
[0].features
|= HSMMC_HAS_48MHZ_MASTER_CLK
;
343 memcpy(&mmc
->slots
[0].mmc_data
, c
->mmc_data
,
344 sizeof(struct mmc_platform_data
));
345 mmc
->slots
[0].card_detect
=
346 (mmc_card_detect_func
)c
->mmc_data
->status
;
350 * NOTE: MMC slots should have a Vcc regulator set up.
351 * This may be from a TWL4030-family chip, another
352 * controllable regulator, or a fixed supply.
354 * temporary HACK: ocr_mask instead of fixed supply
356 mmc
->slots
[0].ocr_mask
= c
->ocr_mask
;
358 if (cpu_is_omap3517() || cpu_is_omap3505())
359 mmc
->slots
[0].set_power
= nop_mmc_set_power
;
361 mmc
->slots
[0].features
|= HSMMC_HAS_PBIAS
;
363 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0
))
364 mmc
->slots
[0].features
|= HSMMC_HAS_UPDATED_RESET
;
368 if (mmc
->slots
[0].features
& HSMMC_HAS_PBIAS
) {
369 /* on-chip level shifting via PBIAS0/PBIAS1 */
370 if (cpu_is_omap44xx()) {
371 mmc
->slots
[0].before_set_reg
=
372 omap4_hsmmc1_before_set_reg
;
373 mmc
->slots
[0].after_set_reg
=
374 omap4_hsmmc1_after_set_reg
;
376 mmc
->slots
[0].before_set_reg
=
377 omap_hsmmc1_before_set_reg
;
378 mmc
->slots
[0].after_set_reg
=
379 omap_hsmmc1_after_set_reg
;
383 /* OMAP3630 HSMMC1 supports only 4-bit */
384 if (cpu_is_omap3630() &&
385 (c
->caps
& MMC_CAP_8_BIT_DATA
)) {
386 c
->caps
&= ~MMC_CAP_8_BIT_DATA
;
387 c
->caps
|= MMC_CAP_4_BIT_DATA
;
388 mmc
->slots
[0].caps
= c
->caps
;
394 if (c
->transceiver
&& (c
->caps
& MMC_CAP_8_BIT_DATA
)) {
395 c
->caps
&= ~MMC_CAP_8_BIT_DATA
;
396 c
->caps
|= MMC_CAP_4_BIT_DATA
;
400 if (mmc
->slots
[0].features
& HSMMC_HAS_PBIAS
) {
401 /* off-chip level shifting, or none */
402 mmc
->slots
[0].before_set_reg
= hsmmc23_before_set_reg
;
403 mmc
->slots
[0].after_set_reg
= NULL
;
408 mmc
->slots
[0].before_set_reg
= NULL
;
409 mmc
->slots
[0].after_set_reg
= NULL
;
412 pr_err("MMC%d configuration not supported!\n", c
->mmc
);
419 static struct omap_device_pm_latency omap_hsmmc_latency
[] = {
421 .deactivate_func
= omap_device_idle_hwmods
,
422 .activate_func
= omap_device_enable_hwmods
,
423 .flags
= OMAP_DEVICE_LATENCY_AUTO_ADJUST
,
426 * XXX There should also be an entry here to power off/on the
427 * MMC regulators/PBIAS cells, etc.
431 #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
433 void __init
omap_init_hsmmc(struct omap2_hsmmc_info
*hsmmcinfo
, int ctrl_nr
)
435 struct omap_hwmod
*oh
;
436 struct omap_device
*od
;
437 struct omap_device_pm_latency
*ohl
;
438 char oh_name
[MAX_OMAP_MMC_HWMOD_NAME_LEN
];
439 struct omap_mmc_platform_data
*mmc_data
;
440 struct omap_mmc_dev_attr
*mmc_dev_attr
;
445 mmc_data
= kzalloc(sizeof(struct omap_mmc_platform_data
), GFP_KERNEL
);
447 pr_err("Cannot allocate memory for mmc device!\n");
451 if (omap_hsmmc_pdata_init(hsmmcinfo
, mmc_data
) < 0) {
452 pr_err("%s fails!\n", __func__
);
455 omap_hsmmc_mux(mmc_data
, (ctrl_nr
- 1));
458 ohl
= omap_hsmmc_latency
;
459 ohl_cnt
= ARRAY_SIZE(omap_hsmmc_latency
);
461 l
= snprintf(oh_name
, MAX_OMAP_MMC_HWMOD_NAME_LEN
,
463 WARN(l
>= MAX_OMAP_MMC_HWMOD_NAME_LEN
,
464 "String buffer overflow in MMC%d device setup\n", ctrl_nr
);
465 oh
= omap_hwmod_lookup(oh_name
);
467 pr_err("Could not look up %s\n", oh_name
);
468 kfree(mmc_data
->slots
[0].name
);
472 if (oh
->dev_attr
!= NULL
) {
473 mmc_dev_attr
= oh
->dev_attr
;
474 mmc_data
->controller_flags
= mmc_dev_attr
->flags
;
477 od
= omap_device_build(name
, ctrl_nr
- 1, oh
, mmc_data
,
478 sizeof(struct omap_mmc_platform_data
), ohl
, ohl_cnt
, false);
480 WARN(1, "Can't build omap_device for %s:%s.\n", name
, oh
->name
);
481 kfree(mmc_data
->slots
[0].name
);
485 * return device handle to board setup code
486 * required to populate for regulator framework structure
488 hsmmcinfo
->dev
= &od
->pdev
.dev
;
494 void __init
omap2_hsmmc_init(struct omap2_hsmmc_info
*controllers
)
498 if (!cpu_is_omap44xx()) {
499 if (cpu_is_omap2430()) {
500 control_pbias_offset
= OMAP243X_CONTROL_PBIAS_LITE
;
501 control_devconf1_offset
= OMAP243X_CONTROL_DEVCONF1
;
503 control_pbias_offset
= OMAP343X_CONTROL_PBIAS_LITE
;
504 control_devconf1_offset
= OMAP343X_CONTROL_DEVCONF1
;
507 control_pbias_offset
=
508 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE
;
509 control_mmc1
= OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1
;
510 reg
= omap4_ctrl_pad_readl(control_mmc1
);
511 reg
|= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK
|
512 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK
);
513 reg
&= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK
|
514 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK
);
515 reg
|= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK
|
516 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK
|
517 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK
);
518 omap4_ctrl_pad_writel(reg
, control_mmc1
);
521 for (; controllers
->mmc
; controllers
++)
522 omap_init_hsmmc(controllers
, controllers
->mmc
);