arch/arm/mach-omap2/lpddr2_jedec_data.c

   1 /*
   2  * LPDDR2 data as per JESD209-2
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  *
   6  * Aneesh V <aneesh@ti.com>
   7  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <mach/lpddr2-jedec.h>
  15 #include <mach/emif.h>
  16
  17 /*
  18  * Organization and refresh requirements for LPDDR2 devices of different
  19  * types and densities. Derived from JESD209-2 section 2.4
  20  */
  21 const struct lpddr2_addressing lpddr2_jedec_addressing_table[] = {
  22         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16      density */
  23         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },   /*64M*/
  24         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },   /*128M*/
  25         {BANKS4, T_REFI_7_8,  {ROW_13, ROW_13}, {COL_8, COL_9} },   /*256M*/
  26         {BANKS4, T_REFI_7_8,  {ROW_13, ROW_13}, {COL_9, COL_10} },  /*512M*/
  27         {BANKS8, T_REFI_7_8,  {ROW_13, ROW_13}, {COL_9, COL_10} },  /*1GS4*/
  28         {BANKS8, T_REFI_3_9,  {ROW_14, ROW_14}, {COL_9, COL_10} },  /*2GS4*/
  29         {BANKS8, T_REFI_3_9,  {ROW_14, ROW_14}, {COL_10, COL_11} }, /*4G*/
  30         {BANKS8, T_REFI_3_9,  {ROW_15, ROW_15}, {COL_10, COL_11} }, /*8G*/
  31         {BANKS4, T_REFI_7_8,  {ROW_14, ROW_14}, {COL_9, COL_10} },  /*1GS2*/
  32         {BANKS4, T_REFI_3_9,  {ROW_15, ROW_15}, {COL_9, COL_10} },  /*2GS2*/
  33 };
  34
  35 /*
  36  * Base AC Timing values specified by JESD209-2 for 400MHz operation
  37  * All devices will honour these timings at this frequency.
  38  * Some devices may have better timings. Using these timings is safe when the
  39  * timings are not available from the device data sheet.
  40  */
  41 const struct lpddr2_timings lpddr2_jedec_timings_400_mhz = {
  42         .max_freq       = 400000000,
  43         .RL             = 6,
  44         .tRPab          = 21,
  45         .tRCD           = 18,
  46         .tWR            = 15,
  47         .tRASmin        = 42,
  48         .tRRD           = 10,
  49         .tWTRx2         = 15,
  50         .tXSR           = 140,
  51         .tXPx2          = 15,
  52         .tRFCab         = 130,
  53         .tRTPx2         = 15,
  54         .tCKE           = 3,
  55         .tCKESR         = 15,
  56         .tZQCS          = 90,
  57         .tZQCL          = 360,
  58         .tZQINIT        = 1000,
  59         .tDQSCKMAXx2    = 11,
  60         .tRASmax        = 70,
  61         .tFAW           = 50
  62 };
  63
  64 /* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
  65 const struct lpddr2_timings lpddr2_jedec_timings_333_mhz = {
  66         .max_freq       = 333000000,
  67         .RL             = 5,
  68         .tRPab          = 21,
  69         .tRCD           = 18,
  70         .tWR            = 15,
  71         .tRASmin        = 42,
  72         .tRRD           = 10,
  73         .tWTRx2         = 15,
  74         .tXSR           = 140,
  75         .tXPx2          = 15,
  76         .tRFCab         = 130,
  77         .tRTPx2         = 15,
  78         .tCKE           = 3,
  79         .tCKESR         = 15,
  80         .tZQCS          = 90,
  81         .tZQCL          = 360,
  82         .tZQINIT        = 1000,
  83         .tDQSCKMAXx2    = 11,
  84         .tRASmax        = 70,
  85         .tFAW           = 50
  86 };
  87
  88 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
  89 const struct lpddr2_timings lpddr2_jedec_timings_200_mhz = {
  90         .max_freq       = 200000000,
  91         .RL             = 3,
  92         .tRPab          = 21,
  93         .tRCD           = 18,
  94         .tWR            = 15,
  95         .tRASmin        = 42,
  96         .tRRD           = 10,
  97         .tWTRx2         = 20,
  98         .tXSR           = 140,
  99         .tXPx2          = 15,
 100         .tRFCab         = 130,
 101         .tRTPx2         = 15,
 102         .tCKE           = 3,
 103         .tCKESR         = 15,
 104         .tZQCS          = 90,
 105         .tZQCL          = 360,
 106         .tZQINIT        = 1000,
 107         .tDQSCKMAXx2    = 11,
 108         .tRASmax        = 70,
 109         .tFAW           = 50
 110 };
 111
 112 /*
 113  * Min tCK values specified by JESD209-2
 114  * Min tCK specifies the minimum duration of some AC timing parameters in terms
 115  * of the number of cycles. If the calculated number of cycles based on the
 116  * absolute time value is less than the min tCK value, min tCK value should
 117  * be used instead. This typically happens at low frequencies.
 118  */
 119 const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
 120         .tRL            = 3,
 121         .tRP_AB         = 3,
 122         .tRCD           = 3,
 123         .tWR            = 3,
 124         .tRAS_MIN       = 3,
 125         .tRRD           = 2,
 126         .tWTR           = 2,
 127         .tXP            = 2,
 128         .tRTP           = 2,
 129         .tCKE           = 3,
 130         .tCKESR         = 3,
 131         .tFAW           = 8
 132 };