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ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blobbe84ed1d2fbc57b3103cca07c72d9a3f73e304e3
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "smartreflex.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35 #include "wd_timer.h"
36 #include <mach/am35xx.h>
37
38 /*
39 * OMAP3xxx hardware module integration data
40 *
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere.
45 */
46
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap34xx_sr2_hwmod;
70 static struct omap_hwmod omap34xx_mcspi1;
71 static struct omap_hwmod omap34xx_mcspi2;
72 static struct omap_hwmod omap34xx_mcspi3;
73 static struct omap_hwmod omap34xx_mcspi4;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 static struct omap_hwmod omap34xx_usb_host_hs_hwmod;
89 static struct omap_hwmod omap34xx_usbhs_ohci_hwmod;
90 static struct omap_hwmod omap34xx_usbhs_ehci_hwmod;
91 static struct omap_hwmod omap34xx_usb_tll_hs_hwmod;
92
93 /* L3 -> L4_CORE interface */
94 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
95 .master = &omap3xxx_l3_main_hwmod,
96 .slave = &omap3xxx_l4_core_hwmod,
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 };
99
100 /* L3 -> L4_PER interface */
101 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
102 .master = &omap3xxx_l3_main_hwmod,
103 .slave = &omap3xxx_l4_per_hwmod,
104 .user = OCP_USER_MPU | OCP_USER_SDMA,
105 };
106
107 /* L3 taret configuration and error log registers */
108 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
109 { .irq = INT_34XX_L3_DBG_IRQ },
110 { .irq = INT_34XX_L3_APP_IRQ },
111 };
112
113 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
114 {
115 .pa_start = 0x68000000,
116 .pa_end = 0x6800ffff,
117 .flags = ADDR_TYPE_RT,
118 },
119 };
120
121 /* MPU -> L3 interface */
122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
127 .user = OCP_USER_MPU,
128 };
129
130 /* Slave interfaces on the L3 interconnect */
131 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
132 &omap3xxx_mpu__l3_main,
133 };
134
135 /* DSS -> l3 */
136 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
137 .master = &omap3xxx_dss_core_hwmod,
138 .slave = &omap3xxx_l3_main_hwmod,
139 .fw = {
140 .omap2 = {
141 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
142 .flags = OMAP_FIREWALL_L3,
143 }
144 },
145 .user = OCP_USER_MPU | OCP_USER_SDMA,
146 };
147
148 /* Master interfaces on the L3 interconnect */
149 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
150 &omap3xxx_l3_main__l4_core,
151 &omap3xxx_l3_main__l4_per,
152 };
153
154 /* L3 */
155 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
156 .name = "l3_main",
157 .class = &l3_hwmod_class,
158 .mpu_irqs = omap3xxx_l3_main_irqs,
159 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
160 .masters = omap3xxx_l3_main_masters,
161 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
162 .slaves = omap3xxx_l3_main_slaves,
163 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
165 .flags = HWMOD_NO_IDLEST,
166 };
167
168 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
169 static struct omap_hwmod omap3xxx_uart1_hwmod;
170 static struct omap_hwmod omap3xxx_uart2_hwmod;
171 static struct omap_hwmod omap3xxx_uart3_hwmod;
172 static struct omap_hwmod omap3xxx_uart4_hwmod;
173 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
174
175 /* l3_core -> usbhsotg interface */
176 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
177 .master = &omap3xxx_usbhsotg_hwmod,
178 .slave = &omap3xxx_l3_main_hwmod,
179 .clk = "core_l3_ick",
180 .user = OCP_USER_MPU,
181 };
182
183 /* l3_core -> am35xx_usbhsotg interface */
184 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
185 .master = &am35xx_usbhsotg_hwmod,
186 .slave = &omap3xxx_l3_main_hwmod,
187 .clk = "core_l3_ick",
188 .user = OCP_USER_MPU,
189 };
190 /* L4_CORE -> L4_WKUP interface */
191 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
192 .master = &omap3xxx_l4_core_hwmod,
193 .slave = &omap3xxx_l4_wkup_hwmod,
194 .user = OCP_USER_MPU | OCP_USER_SDMA,
195 };
196
197 /* L4 CORE -> MMC1 interface */
198 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
199 {
200 .pa_start = 0x4809c000,
201 .pa_end = 0x4809c1ff,
202 .flags = ADDR_TYPE_RT,
203 },
204 };
205
206 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc1_hwmod,
209 .clk = "mmchs1_ick",
210 .addr = omap3xxx_mmc1_addr_space,
211 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
213 .flags = OMAP_FIREWALL_L4
214 };
215
216 /* L4 CORE -> MMC2 interface */
217 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
218 {
219 .pa_start = 0x480b4000,
220 .pa_end = 0x480b41ff,
221 .flags = ADDR_TYPE_RT,
222 },
223 };
224
225 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc2_hwmod,
228 .clk = "mmchs2_ick",
229 .addr = omap3xxx_mmc2_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 .flags = OMAP_FIREWALL_L4
233 };
234
235 /* L4 CORE -> MMC3 interface */
236 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
237 {
238 .pa_start = 0x480ad000,
239 .pa_end = 0x480ad1ff,
240 .flags = ADDR_TYPE_RT,
241 },
242 };
243
244 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_mmc3_hwmod,
247 .clk = "mmchs3_ick",
248 .addr = omap3xxx_mmc3_addr_space,
249 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
250 .user = OCP_USER_MPU | OCP_USER_SDMA,
251 .flags = OMAP_FIREWALL_L4
252 };
253
254 /* L4 CORE -> UART1 interface */
255 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
256 {
257 .pa_start = OMAP3_UART1_BASE,
258 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
259 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
260 },
261 };
262
263 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
264 .master = &omap3xxx_l4_core_hwmod,
265 .slave = &omap3xxx_uart1_hwmod,
266 .clk = "uart1_ick",
267 .addr = omap3xxx_uart1_addr_space,
268 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
269 .user = OCP_USER_MPU | OCP_USER_SDMA,
270 };
271
272 /* L4 CORE -> UART2 interface */
273 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
274 {
275 .pa_start = OMAP3_UART2_BASE,
276 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
277 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
278 },
279 };
280
281 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
282 .master = &omap3xxx_l4_core_hwmod,
283 .slave = &omap3xxx_uart2_hwmod,
284 .clk = "uart2_ick",
285 .addr = omap3xxx_uart2_addr_space,
286 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288 };
289
290 /* L4 PER -> UART3 interface */
291 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
292 {
293 .pa_start = OMAP3_UART3_BASE,
294 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
295 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
296 },
297 };
298
299 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
300 .master = &omap3xxx_l4_per_hwmod,
301 .slave = &omap3xxx_uart3_hwmod,
302 .clk = "uart3_ick",
303 .addr = omap3xxx_uart3_addr_space,
304 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
305 .user = OCP_USER_MPU | OCP_USER_SDMA,
306 };
307
308 /* L4 PER -> UART4 interface */
309 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
310 {
311 .pa_start = OMAP3_UART4_BASE,
312 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
313 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
314 },
315 };
316
317 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
318 .master = &omap3xxx_l4_per_hwmod,
319 .slave = &omap3xxx_uart4_hwmod,
320 .clk = "uart4_ick",
321 .addr = omap3xxx_uart4_addr_space,
322 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
323 .user = OCP_USER_MPU | OCP_USER_SDMA,
324 };
325
326 /* I2C IP block address space length (in bytes) */
327 #define OMAP2_I2C_AS_LEN 128
328
329 /* L4 CORE -> I2C1 interface */
330 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
331 {
332 .pa_start = 0x48070000,
333 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
334 .flags = ADDR_TYPE_RT,
335 },
336 };
337
338 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
339 .master = &omap3xxx_l4_core_hwmod,
340 .slave = &omap3xxx_i2c1_hwmod,
341 .clk = "i2c1_ick",
342 .addr = omap3xxx_i2c1_addr_space,
343 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
344 .fw = {
345 .omap2 = {
346 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
347 .l4_prot_group = 7,
348 .flags = OMAP_FIREWALL_L4,
349 }
350 },
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352 };
353
354 /* L4 CORE -> I2C2 interface */
355 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
356 {
357 .pa_start = 0x48072000,
358 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
359 .flags = ADDR_TYPE_RT,
360 },
361 };
362
363 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
364 .master = &omap3xxx_l4_core_hwmod,
365 .slave = &omap3xxx_i2c2_hwmod,
366 .clk = "i2c2_ick",
367 .addr = omap3xxx_i2c2_addr_space,
368 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
369 .fw = {
370 .omap2 = {
371 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
372 .l4_prot_group = 7,
373 .flags = OMAP_FIREWALL_L4,
374 }
375 },
376 .user = OCP_USER_MPU | OCP_USER_SDMA,
377 };
378
379 /* L4 CORE -> I2C3 interface */
380 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
381 {
382 .pa_start = 0x48060000,
383 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
384 .flags = ADDR_TYPE_RT,
385 },
386 };
387
388 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap3xxx_i2c3_hwmod,
391 .clk = "i2c3_ick",
392 .addr = omap3xxx_i2c3_addr_space,
393 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
394 .fw = {
395 .omap2 = {
396 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
397 .l4_prot_group = 7,
398 .flags = OMAP_FIREWALL_L4,
399 }
400 },
401 .user = OCP_USER_MPU | OCP_USER_SDMA,
402 };
403
404
405 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
406 {.name = "sr1_irq", .irq = 18},
407 };
408
409 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
410 {.name = "sr2_irq", .irq = 19},
411 };
412
413 /* L4 CORE -> SR1 interface */
414 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
415 {
416 .pa_start = OMAP34XX_SR1_BASE,
417 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
418 .flags = ADDR_TYPE_RT,
419 },
420 };
421
422 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
423 .master = &omap3xxx_l4_core_hwmod,
424 .slave = &omap34xx_sr1_hwmod,
425 .clk = "sr_l4_ick",
426 .addr = omap3_sr1_addr_space,
427 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
428 .user = OCP_USER_MPU,
429 };
430
431 /* L4 CORE -> SR1 interface */
432 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
433 {
434 .pa_start = OMAP34XX_SR2_BASE,
435 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
436 .flags = ADDR_TYPE_RT,
437 },
438 };
439
440 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
441 .master = &omap3xxx_l4_core_hwmod,
442 .slave = &omap34xx_sr2_hwmod,
443 .clk = "sr_l4_ick",
444 .addr = omap3_sr2_addr_space,
445 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
446 .user = OCP_USER_MPU,
447 };
448
449 /*
450 * usbhsotg interface data
451 */
452
453 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
454 {
455 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
456 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
457 .flags = ADDR_TYPE_RT
458 },
459 };
460
461 /* l4_core -> usbhsotg */
462 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
463 .master = &omap3xxx_l4_core_hwmod,
464 .slave = &omap3xxx_usbhsotg_hwmod,
465 .clk = "l4_ick",
466 .addr = omap3xxx_usbhsotg_addrs,
467 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
468 .user = OCP_USER_MPU,
469 };
470
471 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
472 &omap3xxx_usbhsotg__l3,
473 };
474
475 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
476 &omap3xxx_l4_core__usbhsotg,
477 };
478
479 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
480 {
481 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
482 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
483 .flags = ADDR_TYPE_RT
484 },
485 };
486
487 /* l4_core -> usbhsotg */
488 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
489 .master = &omap3xxx_l4_core_hwmod,
490 .slave = &am35xx_usbhsotg_hwmod,
491 .clk = "l4_ick",
492 .addr = am35xx_usbhsotg_addrs,
493 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
494 .user = OCP_USER_MPU,
495 };
496
497 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
498 &am35xx_usbhsotg__l3,
499 };
500
501 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
502 &am35xx_l4_core__usbhsotg,
503 };
504 /* Slave interfaces on the L4_CORE interconnect */
505 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
506 &omap3xxx_l3_main__l4_core,
507 };
508
509 /* L4 CORE */
510 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
511 .name = "l4_core",
512 .class = &l4_hwmod_class,
513 .slaves = omap3xxx_l4_core_slaves,
514 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
516 .flags = HWMOD_NO_IDLEST,
517 };
518
519 /* Slave interfaces on the L4_PER interconnect */
520 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
521 &omap3xxx_l3_main__l4_per,
522 };
523
524 /* L4 PER */
525 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
526 .name = "l4_per",
527 .class = &l4_hwmod_class,
528 .slaves = omap3xxx_l4_per_slaves,
529 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
530 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
531 .flags = HWMOD_NO_IDLEST,
532 };
533
534 /* Slave interfaces on the L4_WKUP interconnect */
535 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
536 &omap3xxx_l4_core__l4_wkup,
537 };
538
539 /* L4 WKUP */
540 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
541 .name = "l4_wkup",
542 .class = &l4_hwmod_class,
543 .slaves = omap3xxx_l4_wkup_slaves,
544 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
545 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
546 .flags = HWMOD_NO_IDLEST,
547 };
548
549 /* Master interfaces on the MPU device */
550 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
551 &omap3xxx_mpu__l3_main,
552 };
553
554 /* MPU */
555 static struct omap_hwmod omap3xxx_mpu_hwmod = {
556 .name = "mpu",
557 .class = &mpu_hwmod_class,
558 .main_clk = "arm_fck",
559 .masters = omap3xxx_mpu_masters,
560 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
562 };
563
564 /*
565 * IVA2_2 interface data
566 */
567
568 /* IVA2 <- L3 interface */
569 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
570 .master = &omap3xxx_l3_main_hwmod,
571 .slave = &omap3xxx_iva_hwmod,
572 .clk = "iva2_ck",
573 .user = OCP_USER_MPU | OCP_USER_SDMA,
574 };
575
576 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
577 &omap3xxx_l3__iva,
578 };
579
580 /*
581 * IVA2 (IVA2)
582 */
583
584 static struct omap_hwmod omap3xxx_iva_hwmod = {
585 .name = "iva",
586 .class = &iva_hwmod_class,
587 .masters = omap3xxx_iva_masters,
588 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
589 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
590 };
591
592 /* timer class */
593 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
594 .rev_offs = 0x0000,
595 .sysc_offs = 0x0010,
596 .syss_offs = 0x0014,
597 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
598 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
599 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
600 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
601 .sysc_fields = &omap_hwmod_sysc_type1,
602 };
603
604 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
605 .name = "timer",
606 .sysc = &omap3xxx_timer_1ms_sysc,
607 .rev = OMAP_TIMER_IP_VERSION_1,
608 };
609
610 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
611 .rev_offs = 0x0000,
612 .sysc_offs = 0x0010,
613 .syss_offs = 0x0014,
614 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
615 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
616 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
617 .sysc_fields = &omap_hwmod_sysc_type1,
618 };
619
620 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
621 .name = "timer",
622 .sysc = &omap3xxx_timer_sysc,
623 .rev = OMAP_TIMER_IP_VERSION_1,
624 };
625
626 /* timer1 */
627 static struct omap_hwmod omap3xxx_timer1_hwmod;
628 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
629 { .irq = 37, },
630 };
631
632 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
633 {
634 .pa_start = 0x48318000,
635 .pa_end = 0x48318000 + SZ_1K - 1,
636 .flags = ADDR_TYPE_RT
637 },
638 };
639
640 /* l4_wkup -> timer1 */
641 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
642 .master = &omap3xxx_l4_wkup_hwmod,
643 .slave = &omap3xxx_timer1_hwmod,
644 .clk = "gpt1_ick",
645 .addr = omap3xxx_timer1_addrs,
646 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
647 .user = OCP_USER_MPU | OCP_USER_SDMA,
648 };
649
650 /* timer1 slave port */
651 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
652 &omap3xxx_l4_wkup__timer1,
653 };
654
655 /* timer1 hwmod */
656 static struct omap_hwmod omap3xxx_timer1_hwmod = {
657 .name = "timer1",
658 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
659 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
660 .main_clk = "gpt1_fck",
661 .prcm = {
662 .omap2 = {
663 .prcm_reg_id = 1,
664 .module_bit = OMAP3430_EN_GPT1_SHIFT,
665 .module_offs = WKUP_MOD,
666 .idlest_reg_id = 1,
667 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
668 },
669 },
670 .slaves = omap3xxx_timer1_slaves,
671 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
672 .class = &omap3xxx_timer_1ms_hwmod_class,
673 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
674 };
675
676 /* timer2 */
677 static struct omap_hwmod omap3xxx_timer2_hwmod;
678 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
679 { .irq = 38, },
680 };
681
682 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
683 {
684 .pa_start = 0x49032000,
685 .pa_end = 0x49032000 + SZ_1K - 1,
686 .flags = ADDR_TYPE_RT
687 },
688 };
689
690 /* l4_per -> timer2 */
691 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
692 .master = &omap3xxx_l4_per_hwmod,
693 .slave = &omap3xxx_timer2_hwmod,
694 .clk = "gpt2_ick",
695 .addr = omap3xxx_timer2_addrs,
696 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
697 .user = OCP_USER_MPU | OCP_USER_SDMA,
698 };
699
700 /* timer2 slave port */
701 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
702 &omap3xxx_l4_per__timer2,
703 };
704
705 /* timer2 hwmod */
706 static struct omap_hwmod omap3xxx_timer2_hwmod = {
707 .name = "timer2",
708 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
709 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
710 .main_clk = "gpt2_fck",
711 .prcm = {
712 .omap2 = {
713 .prcm_reg_id = 1,
714 .module_bit = OMAP3430_EN_GPT2_SHIFT,
715 .module_offs = OMAP3430_PER_MOD,
716 .idlest_reg_id = 1,
717 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
718 },
719 },
720 .slaves = omap3xxx_timer2_slaves,
721 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
722 .class = &omap3xxx_timer_1ms_hwmod_class,
723 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
724 };
725
726 /* timer3 */
727 static struct omap_hwmod omap3xxx_timer3_hwmod;
728 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
729 { .irq = 39, },
730 };
731
732 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
733 {
734 .pa_start = 0x49034000,
735 .pa_end = 0x49034000 + SZ_1K - 1,
736 .flags = ADDR_TYPE_RT
737 },
738 };
739
740 /* l4_per -> timer3 */
741 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
742 .master = &omap3xxx_l4_per_hwmod,
743 .slave = &omap3xxx_timer3_hwmod,
744 .clk = "gpt3_ick",
745 .addr = omap3xxx_timer3_addrs,
746 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
747 .user = OCP_USER_MPU | OCP_USER_SDMA,
748 };
749
750 /* timer3 slave port */
751 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
752 &omap3xxx_l4_per__timer3,
753 };
754
755 /* timer3 hwmod */
756 static struct omap_hwmod omap3xxx_timer3_hwmod = {
757 .name = "timer3",
758 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
759 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
760 .main_clk = "gpt3_fck",
761 .prcm = {
762 .omap2 = {
763 .prcm_reg_id = 1,
764 .module_bit = OMAP3430_EN_GPT3_SHIFT,
765 .module_offs = OMAP3430_PER_MOD,
766 .idlest_reg_id = 1,
767 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
768 },
769 },
770 .slaves = omap3xxx_timer3_slaves,
771 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
772 .class = &omap3xxx_timer_hwmod_class,
773 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
774 };
775
776 /* timer4 */
777 static struct omap_hwmod omap3xxx_timer4_hwmod;
778 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
779 { .irq = 40, },
780 };
781
782 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
783 {
784 .pa_start = 0x49036000,
785 .pa_end = 0x49036000 + SZ_1K - 1,
786 .flags = ADDR_TYPE_RT
787 },
788 };
789
790 /* l4_per -> timer4 */
791 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
792 .master = &omap3xxx_l4_per_hwmod,
793 .slave = &omap3xxx_timer4_hwmod,
794 .clk = "gpt4_ick",
795 .addr = omap3xxx_timer4_addrs,
796 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
797 .user = OCP_USER_MPU | OCP_USER_SDMA,
798 };
799
800 /* timer4 slave port */
801 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
802 &omap3xxx_l4_per__timer4,
803 };
804
805 /* timer4 hwmod */
806 static struct omap_hwmod omap3xxx_timer4_hwmod = {
807 .name = "timer4",
808 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
809 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
810 .main_clk = "gpt4_fck",
811 .prcm = {
812 .omap2 = {
813 .prcm_reg_id = 1,
814 .module_bit = OMAP3430_EN_GPT4_SHIFT,
815 .module_offs = OMAP3430_PER_MOD,
816 .idlest_reg_id = 1,
817 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
818 },
819 },
820 .slaves = omap3xxx_timer4_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
822 .class = &omap3xxx_timer_hwmod_class,
823 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
824 };
825
826 /* timer5 */
827 static struct omap_hwmod omap3xxx_timer5_hwmod;
828 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
829 { .irq = 41, },
830 };
831
832 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
833 {
834 .pa_start = 0x49038000,
835 .pa_end = 0x49038000 + SZ_1K - 1,
836 .flags = ADDR_TYPE_RT
837 },
838 };
839
840 /* l4_per -> timer5 */
841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
842 .master = &omap3xxx_l4_per_hwmod,
843 .slave = &omap3xxx_timer5_hwmod,
844 .clk = "gpt5_ick",
845 .addr = omap3xxx_timer5_addrs,
846 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
847 .user = OCP_USER_MPU | OCP_USER_SDMA,
848 };
849
850 /* timer5 slave port */
851 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
852 &omap3xxx_l4_per__timer5,
853 };
854
855 /* timer5 hwmod */
856 static struct omap_hwmod omap3xxx_timer5_hwmod = {
857 .name = "timer5",
858 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
859 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
860 .main_clk = "gpt5_fck",
861 .prcm = {
862 .omap2 = {
863 .prcm_reg_id = 1,
864 .module_bit = OMAP3430_EN_GPT5_SHIFT,
865 .module_offs = OMAP3430_PER_MOD,
866 .idlest_reg_id = 1,
867 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
868 },
869 },
870 .slaves = omap3xxx_timer5_slaves,
871 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
872 .class = &omap3xxx_timer_hwmod_class,
873 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
874 };
875
876 /* timer6 */
877 static struct omap_hwmod omap3xxx_timer6_hwmod;
878 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
879 { .irq = 42, },
880 };
881
882 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
883 {
884 .pa_start = 0x4903A000,
885 .pa_end = 0x4903A000 + SZ_1K - 1,
886 .flags = ADDR_TYPE_RT
887 },
888 };
889
890 /* l4_per -> timer6 */
891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
892 .master = &omap3xxx_l4_per_hwmod,
893 .slave = &omap3xxx_timer6_hwmod,
894 .clk = "gpt6_ick",
895 .addr = omap3xxx_timer6_addrs,
896 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
897 .user = OCP_USER_MPU | OCP_USER_SDMA,
898 };
899
900 /* timer6 slave port */
901 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
902 &omap3xxx_l4_per__timer6,
903 };
904
905 /* timer6 hwmod */
906 static struct omap_hwmod omap3xxx_timer6_hwmod = {
907 .name = "timer6",
908 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
909 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
910 .main_clk = "gpt6_fck",
911 .prcm = {
912 .omap2 = {
913 .prcm_reg_id = 1,
914 .module_bit = OMAP3430_EN_GPT6_SHIFT,
915 .module_offs = OMAP3430_PER_MOD,
916 .idlest_reg_id = 1,
917 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
918 },
919 },
920 .slaves = omap3xxx_timer6_slaves,
921 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
922 .class = &omap3xxx_timer_hwmod_class,
923 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
924 };
925
926 /* timer7 */
927 static struct omap_hwmod omap3xxx_timer7_hwmod;
928 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
929 { .irq = 43, },
930 };
931
932 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
933 {
934 .pa_start = 0x4903C000,
935 .pa_end = 0x4903C000 + SZ_1K - 1,
936 .flags = ADDR_TYPE_RT
937 },
938 };
939
940 /* l4_per -> timer7 */
941 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
942 .master = &omap3xxx_l4_per_hwmod,
943 .slave = &omap3xxx_timer7_hwmod,
944 .clk = "gpt7_ick",
945 .addr = omap3xxx_timer7_addrs,
946 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
947 .user = OCP_USER_MPU | OCP_USER_SDMA,
948 };
949
950 /* timer7 slave port */
951 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
952 &omap3xxx_l4_per__timer7,
953 };
954
955 /* timer7 hwmod */
956 static struct omap_hwmod omap3xxx_timer7_hwmod = {
957 .name = "timer7",
958 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
959 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
960 .main_clk = "gpt7_fck",
961 .prcm = {
962 .omap2 = {
963 .prcm_reg_id = 1,
964 .module_bit = OMAP3430_EN_GPT7_SHIFT,
965 .module_offs = OMAP3430_PER_MOD,
966 .idlest_reg_id = 1,
967 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
968 },
969 },
970 .slaves = omap3xxx_timer7_slaves,
971 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
972 .class = &omap3xxx_timer_hwmod_class,
973 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
974 };
975
976 /* timer8 */
977 static struct omap_hwmod omap3xxx_timer8_hwmod;
978 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
979 { .irq = 44, },
980 };
981
982 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
983 {
984 .pa_start = 0x4903E000,
985 .pa_end = 0x4903E000 + SZ_1K - 1,
986 .flags = ADDR_TYPE_RT
987 },
988 };
989
990 /* l4_per -> timer8 */
991 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
992 .master = &omap3xxx_l4_per_hwmod,
993 .slave = &omap3xxx_timer8_hwmod,
994 .clk = "gpt8_ick",
995 .addr = omap3xxx_timer8_addrs,
996 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
997 .user = OCP_USER_MPU | OCP_USER_SDMA,
998 };
999
1000 /* timer8 slave port */
1001 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
1002 &omap3xxx_l4_per__timer8,
1003 };
1004
1005 /* timer8 hwmod */
1006 static struct omap_hwmod omap3xxx_timer8_hwmod = {
1007 .name = "timer8",
1008 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
1009 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
1010 .main_clk = "gpt8_fck",
1011 .prcm = {
1012 .omap2 = {
1013 .prcm_reg_id = 1,
1014 .module_bit = OMAP3430_EN_GPT8_SHIFT,
1015 .module_offs = OMAP3430_PER_MOD,
1016 .idlest_reg_id = 1,
1017 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1018 },
1019 },
1020 .slaves = omap3xxx_timer8_slaves,
1021 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
1022 .class = &omap3xxx_timer_hwmod_class,
1023 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1024 };
1025
1026 /* timer9 */
1027 static struct omap_hwmod omap3xxx_timer9_hwmod;
1028 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1029 { .irq = 45, },
1030 };
1031
1032 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1033 {
1034 .pa_start = 0x49040000,
1035 .pa_end = 0x49040000 + SZ_1K - 1,
1036 .flags = ADDR_TYPE_RT
1037 },
1038 };
1039
1040 /* l4_per -> timer9 */
1041 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1042 .master = &omap3xxx_l4_per_hwmod,
1043 .slave = &omap3xxx_timer9_hwmod,
1044 .clk = "gpt9_ick",
1045 .addr = omap3xxx_timer9_addrs,
1046 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1047 .user = OCP_USER_MPU | OCP_USER_SDMA,
1048 };
1049
1050 /* timer9 slave port */
1051 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1052 &omap3xxx_l4_per__timer9,
1053 };
1054
1055 /* timer9 hwmod */
1056 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1057 .name = "timer9",
1058 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1059 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1060 .main_clk = "gpt9_fck",
1061 .prcm = {
1062 .omap2 = {
1063 .prcm_reg_id = 1,
1064 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1065 .module_offs = OMAP3430_PER_MOD,
1066 .idlest_reg_id = 1,
1067 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1068 },
1069 },
1070 .slaves = omap3xxx_timer9_slaves,
1071 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1072 .class = &omap3xxx_timer_hwmod_class,
1073 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1074 };
1075
1076 /* timer10 */
1077 static struct omap_hwmod omap3xxx_timer10_hwmod;
1078 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1079 { .irq = 46, },
1080 };
1081
1082 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1083 {
1084 .pa_start = 0x48086000,
1085 .pa_end = 0x48086000 + SZ_1K - 1,
1086 .flags = ADDR_TYPE_RT
1087 },
1088 };
1089
1090 /* l4_core -> timer10 */
1091 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1092 .master = &omap3xxx_l4_core_hwmod,
1093 .slave = &omap3xxx_timer10_hwmod,
1094 .clk = "gpt10_ick",
1095 .addr = omap3xxx_timer10_addrs,
1096 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1097 .user = OCP_USER_MPU | OCP_USER_SDMA,
1098 };
1099
1100 /* timer10 slave port */
1101 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1102 &omap3xxx_l4_core__timer10,
1103 };
1104
1105 /* timer10 hwmod */
1106 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1107 .name = "timer10",
1108 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1109 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1110 .main_clk = "gpt10_fck",
1111 .prcm = {
1112 .omap2 = {
1113 .prcm_reg_id = 1,
1114 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1115 .module_offs = CORE_MOD,
1116 .idlest_reg_id = 1,
1117 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1118 },
1119 },
1120 .slaves = omap3xxx_timer10_slaves,
1121 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1122 .class = &omap3xxx_timer_1ms_hwmod_class,
1123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1124 };
1125
1126 /* timer11 */
1127 static struct omap_hwmod omap3xxx_timer11_hwmod;
1128 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1129 { .irq = 47, },
1130 };
1131
1132 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1133 {
1134 .pa_start = 0x48088000,
1135 .pa_end = 0x48088000 + SZ_1K - 1,
1136 .flags = ADDR_TYPE_RT
1137 },
1138 };
1139
1140 /* l4_core -> timer11 */
1141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1142 .master = &omap3xxx_l4_core_hwmod,
1143 .slave = &omap3xxx_timer11_hwmod,
1144 .clk = "gpt11_ick",
1145 .addr = omap3xxx_timer11_addrs,
1146 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1147 .user = OCP_USER_MPU | OCP_USER_SDMA,
1148 };
1149
1150 /* timer11 slave port */
1151 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1152 &omap3xxx_l4_core__timer11,
1153 };
1154
1155 /* timer11 hwmod */
1156 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1157 .name = "timer11",
1158 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1159 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1160 .main_clk = "gpt11_fck",
1161 .prcm = {
1162 .omap2 = {
1163 .prcm_reg_id = 1,
1164 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1165 .module_offs = CORE_MOD,
1166 .idlest_reg_id = 1,
1167 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1168 },
1169 },
1170 .slaves = omap3xxx_timer11_slaves,
1171 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1172 .class = &omap3xxx_timer_hwmod_class,
1173 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1174 };
1175
1176 /* timer12*/
1177 static struct omap_hwmod omap3xxx_timer12_hwmod;
1178 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1179 { .irq = 95, },
1180 };
1181
1182 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1183 {
1184 .pa_start = 0x48304000,
1185 .pa_end = 0x48304000 + SZ_1K - 1,
1186 .flags = ADDR_TYPE_RT
1187 },
1188 };
1189
1190 /* l4_core -> timer12 */
1191 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1192 .master = &omap3xxx_l4_core_hwmod,
1193 .slave = &omap3xxx_timer12_hwmod,
1194 .clk = "gpt12_ick",
1195 .addr = omap3xxx_timer12_addrs,
1196 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1197 .user = OCP_USER_MPU | OCP_USER_SDMA,
1198 };
1199
1200 /* timer12 slave port */
1201 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1202 &omap3xxx_l4_core__timer12,
1203 };
1204
1205 /* timer12 hwmod */
1206 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1207 .name = "timer12",
1208 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1209 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1210 .main_clk = "gpt12_fck",
1211 .prcm = {
1212 .omap2 = {
1213 .prcm_reg_id = 1,
1214 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1215 .module_offs = WKUP_MOD,
1216 .idlest_reg_id = 1,
1217 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1218 },
1219 },
1220 .slaves = omap3xxx_timer12_slaves,
1221 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1222 .class = &omap3xxx_timer_hwmod_class,
1223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1224 };
1225
1226 /* l4_wkup -> wd_timer2 */
1227 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1228 {
1229 .pa_start = 0x48314000,
1230 .pa_end = 0x4831407f,
1231 .flags = ADDR_TYPE_RT
1232 },
1233 };
1234
1235 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1236 .master = &omap3xxx_l4_wkup_hwmod,
1237 .slave = &omap3xxx_wd_timer2_hwmod,
1238 .clk = "wdt2_ick",
1239 .addr = omap3xxx_wd_timer2_addrs,
1240 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1241 .user = OCP_USER_MPU | OCP_USER_SDMA,
1242 };
1243
1244 /*
1245 * 'wd_timer' class
1246 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1247 * overflow condition
1248 */
1249
1250 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1251 .rev_offs = 0x0000,
1252 .sysc_offs = 0x0010,
1253 .syss_offs = 0x0014,
1254 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1255 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1256 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1257 SYSS_HAS_RESET_STATUS),
1258 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1259 .sysc_fields = &omap_hwmod_sysc_type1,
1260 };
1261
1262 /* I2C common */
1263 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1264 .rev_offs = 0x00,
1265 .sysc_offs = 0x20,
1266 .syss_offs = 0x10,
1267 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1268 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1269 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1270 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1271 .clockact = CLOCKACT_TEST_ICLK,
1272 .sysc_fields = &omap_hwmod_sysc_type1,
1273 };
1274
1275 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1276 .name = "wd_timer",
1277 .sysc = &omap3xxx_wd_timer_sysc,
1278 .pre_shutdown = &omap2_wd_timer_disable
1279 };
1280
1281 /* wd_timer2 */
1282 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1283 &omap3xxx_l4_wkup__wd_timer2,
1284 };
1285
1286 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1287 .name = "wd_timer2",
1288 .class = &omap3xxx_wd_timer_hwmod_class,
1289 .main_clk = "wdt2_fck",
1290 .prcm = {
1291 .omap2 = {
1292 .prcm_reg_id = 1,
1293 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1294 .module_offs = WKUP_MOD,
1295 .idlest_reg_id = 1,
1296 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1297 },
1298 },
1299 .slaves = omap3xxx_wd_timer2_slaves,
1300 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1302 /*
1303 * XXX: Use software supervised mode, HW supervised smartidle seems to
1304 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1305 */
1306 .flags = HWMOD_SWSUP_SIDLE,
1307 };
1308
1309 /* UART common */
1310
1311 static struct omap_hwmod_class_sysconfig uart_sysc = {
1312 .rev_offs = 0x50,
1313 .sysc_offs = 0x54,
1314 .syss_offs = 0x58,
1315 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1316 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1317 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1318 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1319 .sysc_fields = &omap_hwmod_sysc_type1,
1320 };
1321
1322 static struct omap_hwmod_class uart_class = {
1323 .name = "uart",
1324 .sysc = &uart_sysc,
1325 };
1326
1327 /* UART1 */
1328
1329 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1330 { .irq = INT_24XX_UART1_IRQ, },
1331 };
1332
1333 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1334 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1335 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1336 };
1337
1338 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1339 &omap3_l4_core__uart1,
1340 };
1341
1342 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1343 .name = "uart1",
1344 .mpu_irqs = uart1_mpu_irqs,
1345 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1346 .sdma_reqs = uart1_sdma_reqs,
1347 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1348 .main_clk = "uart1_fck",
1349 .prcm = {
1350 .omap2 = {
1351 .module_offs = CORE_MOD,
1352 .prcm_reg_id = 1,
1353 .module_bit = OMAP3430_EN_UART1_SHIFT,
1354 .idlest_reg_id = 1,
1355 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1356 },
1357 },
1358 .slaves = omap3xxx_uart1_slaves,
1359 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1360 .class = &uart_class,
1361 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1362 };
1363
1364 /* UART2 */
1365
1366 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1367 { .irq = INT_24XX_UART2_IRQ, },
1368 };
1369
1370 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1371 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1372 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1373 };
1374
1375 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1376 &omap3_l4_core__uart2,
1377 };
1378
1379 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1380 .name = "uart2",
1381 .mpu_irqs = uart2_mpu_irqs,
1382 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1383 .sdma_reqs = uart2_sdma_reqs,
1384 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1385 .main_clk = "uart2_fck",
1386 .prcm = {
1387 .omap2 = {
1388 .module_offs = CORE_MOD,
1389 .prcm_reg_id = 1,
1390 .module_bit = OMAP3430_EN_UART2_SHIFT,
1391 .idlest_reg_id = 1,
1392 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1393 },
1394 },
1395 .slaves = omap3xxx_uart2_slaves,
1396 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1397 .class = &uart_class,
1398 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1399 };
1400
1401 /* UART3 */
1402
1403 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1404 { .irq = INT_24XX_UART3_IRQ, },
1405 };
1406
1407 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1408 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1409 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1410 };
1411
1412 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1413 &omap3_l4_per__uart3,
1414 };
1415
1416 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1417 .name = "uart3",
1418 .mpu_irqs = uart3_mpu_irqs,
1419 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1420 .sdma_reqs = uart3_sdma_reqs,
1421 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1422 .main_clk = "uart3_fck",
1423 .prcm = {
1424 .omap2 = {
1425 .module_offs = OMAP3430_PER_MOD,
1426 .prcm_reg_id = 1,
1427 .module_bit = OMAP3430_EN_UART3_SHIFT,
1428 .idlest_reg_id = 1,
1429 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1430 },
1431 },
1432 .slaves = omap3xxx_uart3_slaves,
1433 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1434 .class = &uart_class,
1435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1436 };
1437
1438 /* UART4 */
1439
1440 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1441 { .irq = INT_36XX_UART4_IRQ, },
1442 };
1443
1444 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1445 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1446 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1447 };
1448
1449 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1450 &omap3_l4_per__uart4,
1451 };
1452
1453 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1454 .name = "uart4",
1455 .mpu_irqs = uart4_mpu_irqs,
1456 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1457 .sdma_reqs = uart4_sdma_reqs,
1458 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1459 .main_clk = "uart4_fck",
1460 .prcm = {
1461 .omap2 = {
1462 .module_offs = OMAP3430_PER_MOD,
1463 .prcm_reg_id = 1,
1464 .module_bit = OMAP3630_EN_UART4_SHIFT,
1465 .idlest_reg_id = 1,
1466 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1467 },
1468 },
1469 .slaves = omap3xxx_uart4_slaves,
1470 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1471 .class = &uart_class,
1472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1473 };
1474
1475 static struct omap_hwmod_class i2c_class = {
1476 .name = "i2c",
1477 .sysc = &i2c_sysc,
1478 .rev = OMAP_I2C_IP_VERSION_1,
1479 .reset = &omap_i2c_reset,
1480 };
1481
1482 /*
1483 * 'dss' class
1484 * display sub-system
1485 */
1486
1487 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1488 .rev_offs = 0x0000,
1489 .sysc_offs = 0x0010,
1490 .syss_offs = 0x0014,
1491 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1492 .sysc_fields = &omap_hwmod_sysc_type1,
1493 };
1494
1495 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1496 .name = "dss",
1497 .sysc = &omap3xxx_dss_sysc,
1498 };
1499
1500 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1501 { .name = "dispc", .dma_req = 5 },
1502 { .name = "dsi1", .dma_req = 74 },
1503 };
1504
1505 /* dss */
1506 /* dss master ports */
1507 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1508 &omap3xxx_dss__l3,
1509 };
1510
1511 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1512 {
1513 .pa_start = 0x48050000,
1514 .pa_end = 0x480503FF,
1515 .flags = ADDR_TYPE_RT
1516 },
1517 };
1518
1519 /* l4_core -> dss */
1520 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1521 .master = &omap3xxx_l4_core_hwmod,
1522 .slave = &omap3430es1_dss_core_hwmod,
1523 .clk = "dss_ick",
1524 .addr = omap3xxx_dss_addrs,
1525 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1526 .fw = {
1527 .omap2 = {
1528 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1529 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1530 .flags = OMAP_FIREWALL_L4,
1531 }
1532 },
1533 .user = OCP_USER_MPU | OCP_USER_SDMA,
1534 };
1535
1536 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1537 .master = &omap3xxx_l4_core_hwmod,
1538 .slave = &omap3xxx_dss_core_hwmod,
1539 .clk = "dss_ick",
1540 .addr = omap3xxx_dss_addrs,
1541 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1542 .fw = {
1543 .omap2 = {
1544 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1545 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1546 .flags = OMAP_FIREWALL_L4,
1547 }
1548 },
1549 .user = OCP_USER_MPU | OCP_USER_SDMA,
1550 };
1551
1552 /* dss slave ports */
1553 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1554 &omap3430es1_l4_core__dss,
1555 };
1556
1557 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1558 &omap3xxx_l4_core__dss,
1559 };
1560
1561 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1562 { .role = "dss_clk", .clk = "dss1_alwon_fck" },
1563 /*
1564 * The rest of the clocks are not needed by the driver,
1565 * but are needed by the hwmod to reset DSS properly.
1566 */
1567 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1568 { .role = "tv_clk", .clk = "dss_tv_fck" },
1569 /* required only on OMAP3430 */
1570 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1571 };
1572
1573 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1574 .name = "dss_core",
1575 .class = &omap3xxx_dss_hwmod_class,
1576 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1577 .sdma_reqs = omap3xxx_dss_sdma_chs,
1578 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1579
1580 .prcm = {
1581 .omap2 = {
1582 .prcm_reg_id = 1,
1583 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1584 .module_offs = OMAP3430_DSS_MOD,
1585 .idlest_reg_id = 1,
1586 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1587 },
1588 },
1589 .opt_clks = dss_opt_clks,
1590 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1591 .slaves = omap3430es1_dss_slaves,
1592 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1593 .masters = omap3xxx_dss_masters,
1594 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1595 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1596 .flags = HWMOD_NO_IDLEST,
1597 };
1598
1599 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1600 .name = "dss_core",
1601 .class = &omap3xxx_dss_hwmod_class,
1602 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1603 .sdma_reqs = omap3xxx_dss_sdma_chs,
1604 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1605
1606 .prcm = {
1607 .omap2 = {
1608 .prcm_reg_id = 1,
1609 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1610 .module_offs = OMAP3430_DSS_MOD,
1611 .idlest_reg_id = 1,
1612 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1613 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1614 },
1615 },
1616 .opt_clks = dss_opt_clks,
1617 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1618 .slaves = omap3xxx_dss_slaves,
1619 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1620 .masters = omap3xxx_dss_masters,
1621 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1622 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1623 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1624 };
1625
1626 /*
1627 * 'dispc' class
1628 * display controller
1629 */
1630
1631 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1632 .rev_offs = 0x0000,
1633 .sysc_offs = 0x0010,
1634 .syss_offs = 0x0014,
1635 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1636 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1637 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1638 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1639 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1640 .sysc_fields = &omap_hwmod_sysc_type1,
1641 };
1642
1643 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1644 .name = "dispc",
1645 .sysc = &omap3xxx_dispc_sysc,
1646 };
1647
1648 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1649 { .irq = 25 },
1650 };
1651
1652 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1653 {
1654 .pa_start = 0x48050400,
1655 .pa_end = 0x480507FF,
1656 .flags = ADDR_TYPE_RT
1657 },
1658 };
1659
1660 /* l4_core -> dss_dispc */
1661 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1662 .master = &omap3xxx_l4_core_hwmod,
1663 .slave = &omap3xxx_dss_dispc_hwmod,
1664 .clk = "dss_ick",
1665 .addr = omap3xxx_dss_dispc_addrs,
1666 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1667 .fw = {
1668 .omap2 = {
1669 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1670 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1671 .flags = OMAP_FIREWALL_L4,
1672 }
1673 },
1674 .user = OCP_USER_MPU | OCP_USER_SDMA,
1675 };
1676
1677 /* dss_dispc slave ports */
1678 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1679 &omap3xxx_l4_core__dss_dispc,
1680 };
1681
1682 static struct omap_hwmod_opt_clk dispc_opt_clks[] = {
1683 { .role = "dss_clk", .clk = "dss1_alwon_fck" },
1684 };
1685
1686 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1687 .name = "dss_dispc",
1688 .class = &omap3xxx_dispc_hwmod_class,
1689 .mpu_irqs = omap3xxx_dispc_irqs,
1690 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
1691 .main_clk = "dss1_alwon_fck",
1692 .prcm = {
1693 .omap2 = {
1694 .prcm_reg_id = 1,
1695 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1696 .module_offs = OMAP3430_DSS_MOD,
1697 },
1698 },
1699 .opt_clks = dispc_opt_clks,
1700 .opt_clks_cnt = ARRAY_SIZE(dispc_opt_clks),
1701 .slaves = omap3xxx_dss_dispc_slaves,
1702 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1703 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1704 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1705 CHIP_GE_OMAP3630ES1_1),
1706 .flags = HWMOD_NO_IDLEST,
1707 };
1708
1709 /*
1710 * 'dsi' class
1711 * display serial interface controller
1712 */
1713
1714 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1715 .name = "dsi",
1716 };
1717
1718 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1719 { .irq = 25 },
1720 };
1721
1722 /* dss_dsi1 */
1723 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1724 {
1725 .pa_start = 0x4804FC00,
1726 .pa_end = 0x4804FFFF,
1727 .flags = ADDR_TYPE_RT
1728 },
1729 };
1730
1731 /* l4_core -> dss_dsi1 */
1732 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1733 .master = &omap3xxx_l4_core_hwmod,
1734 .slave = &omap3xxx_dss_dsi1_hwmod,
1735 .addr = omap3xxx_dss_dsi1_addrs,
1736 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1737 .fw = {
1738 .omap2 = {
1739 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1740 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1741 .flags = OMAP_FIREWALL_L4,
1742 }
1743 },
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745 };
1746
1747 /* dss_dsi1 slave ports */
1748 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1749 &omap3xxx_l4_core__dss_dsi1,
1750 };
1751
1752 static struct omap_hwmod_opt_clk dsi1_opt_clks[] = {
1753 { .role = "dss_clk", .clk = "dss1_alwon_fck" },
1754 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1755 };
1756
1757 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1758 .name = "dss_dsi1",
1759 .class = &omap3xxx_dsi_hwmod_class,
1760 .mpu_irqs = omap3xxx_dsi1_irqs,
1761 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1762 .main_clk = "dss1_alwon_fck",
1763 .prcm = {
1764 .omap2 = {
1765 .prcm_reg_id = 1,
1766 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1767 .module_offs = OMAP3430_DSS_MOD,
1768 },
1769 },
1770 .opt_clks = dsi1_opt_clks,
1771 .opt_clks_cnt = ARRAY_SIZE(dsi1_opt_clks),
1772 .slaves = omap3xxx_dss_dsi1_slaves,
1773 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1774 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1775 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1776 CHIP_GE_OMAP3630ES1_1),
1777 .flags = HWMOD_NO_IDLEST,
1778 };
1779
1780 /*
1781 * 'rfbi' class
1782 * remote frame buffer interface
1783 */
1784
1785 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1786 .rev_offs = 0x0000,
1787 .sysc_offs = 0x0010,
1788 .syss_offs = 0x0014,
1789 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1790 SYSC_HAS_AUTOIDLE),
1791 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1792 .sysc_fields = &omap_hwmod_sysc_type1,
1793 };
1794
1795 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1796 .name = "rfbi",
1797 .sysc = &omap3xxx_rfbi_sysc,
1798 };
1799
1800 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1801 {
1802 .pa_start = 0x48050800,
1803 .pa_end = 0x48050BFF,
1804 .flags = ADDR_TYPE_RT
1805 },
1806 };
1807
1808 /* l4_core -> dss_rfbi */
1809 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1810 .master = &omap3xxx_l4_core_hwmod,
1811 .slave = &omap3xxx_dss_rfbi_hwmod,
1812 .clk = "dss_ick",
1813 .addr = omap3xxx_dss_rfbi_addrs,
1814 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1815 .fw = {
1816 .omap2 = {
1817 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1819 .flags = OMAP_FIREWALL_L4,
1820 }
1821 },
1822 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 };
1824
1825 /* dss_rfbi slave ports */
1826 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1827 &omap3xxx_l4_core__dss_rfbi,
1828 };
1829
1830 static struct omap_hwmod_opt_clk rfbi_opt_clks[] = {
1831 { .role = "rfbi_iclk", .clk = "dss_ick" },
1832 };
1833
1834 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1835 .name = "dss_rfbi",
1836 .class = &omap3xxx_rfbi_hwmod_class,
1837 .main_clk = "dss1_alwon_fck",
1838 .prcm = {
1839 .omap2 = {
1840 .prcm_reg_id = 1,
1841 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1842 .module_offs = OMAP3430_DSS_MOD,
1843 },
1844 },
1845 .opt_clks = rfbi_opt_clks,
1846 .opt_clks_cnt = ARRAY_SIZE(rfbi_opt_clks),
1847 .slaves = omap3xxx_dss_rfbi_slaves,
1848 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1849 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1850 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1851 CHIP_GE_OMAP3630ES1_1),
1852 .flags = HWMOD_NO_IDLEST,
1853 };
1854
1855 /*
1856 * 'venc' class
1857 * video encoder
1858 */
1859
1860 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1861 .name = "venc",
1862 };
1863
1864 /* dss_venc */
1865 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1866 {
1867 .pa_start = 0x48050C00,
1868 .pa_end = 0x48050FFF,
1869 .flags = ADDR_TYPE_RT
1870 },
1871 };
1872
1873 /* l4_core -> dss_venc */
1874 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1875 .master = &omap3xxx_l4_core_hwmod,
1876 .slave = &omap3xxx_dss_venc_hwmod,
1877 .clk = "dss_tv_fck",
1878 .addr = omap3xxx_dss_venc_addrs,
1879 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1880 .fw = {
1881 .omap2 = {
1882 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1883 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1884 .flags = OMAP_FIREWALL_L4,
1885 }
1886 },
1887 .flags = OCPIF_SWSUP_IDLE,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889 };
1890
1891 /* dss_venc slave ports */
1892 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1893 &omap3xxx_l4_core__dss_venc,
1894 };
1895
1896 static struct omap_hwmod_opt_clk venc_opt_clks[] = {
1897 { .role = "tv_clk", .clk = "dss_tv_fck" },
1898 /* required only on OMAP3430 */
1899 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1900 };
1901
1902 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1903 .name = "dss_venc",
1904 .class = &omap3xxx_venc_hwmod_class,
1905 .main_clk = "dss1_alwon_fck",
1906 .prcm = {
1907 .omap2 = {
1908 .prcm_reg_id = 1,
1909 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1910 .module_offs = OMAP3430_DSS_MOD,
1911 },
1912 },
1913 .opt_clks = venc_opt_clks,
1914 .opt_clks_cnt = ARRAY_SIZE(venc_opt_clks),
1915 .slaves = omap3xxx_dss_venc_slaves,
1916 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1917 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1918 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1919 CHIP_GE_OMAP3630ES1_1),
1920 .flags = HWMOD_NO_IDLEST,
1921 };
1922
1923 /* I2C1 */
1924
1925 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1926 .fifo_depth = 8, /* bytes */
1927 };
1928
1929 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1930 { .irq = INT_24XX_I2C1_IRQ, },
1931 };
1932
1933 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1934 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1935 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1936 };
1937
1938 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1939 &omap3_l4_core__i2c1,
1940 };
1941
1942 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1943 .name = "i2c1",
1944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1945 .mpu_irqs = i2c1_mpu_irqs,
1946 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1947 .sdma_reqs = i2c1_sdma_reqs,
1948 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1949 .main_clk = "i2c1_fck",
1950 .prcm = {
1951 .omap2 = {
1952 .module_offs = CORE_MOD,
1953 .prcm_reg_id = 1,
1954 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1955 .idlest_reg_id = 1,
1956 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1957 },
1958 },
1959 .slaves = omap3xxx_i2c1_slaves,
1960 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1961 .class = &i2c_class,
1962 .dev_attr = &i2c1_dev_attr,
1963 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1964 };
1965
1966 /* I2C2 */
1967
1968 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1969 .fifo_depth = 8, /* bytes */
1970 };
1971
1972 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1973 { .irq = INT_24XX_I2C2_IRQ, },
1974 };
1975
1976 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1977 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1978 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1979 };
1980
1981 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1982 &omap3_l4_core__i2c2,
1983 };
1984
1985 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1986 .name = "i2c2",
1987 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1988 .mpu_irqs = i2c2_mpu_irqs,
1989 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1990 .sdma_reqs = i2c2_sdma_reqs,
1991 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1992 .main_clk = "i2c2_fck",
1993 .prcm = {
1994 .omap2 = {
1995 .module_offs = CORE_MOD,
1996 .prcm_reg_id = 1,
1997 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1998 .idlest_reg_id = 1,
1999 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
2000 },
2001 },
2002 .slaves = omap3xxx_i2c2_slaves,
2003 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
2004 .class = &i2c_class,
2005 .dev_attr = &i2c2_dev_attr,
2006 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2007 };
2008
2009 /* I2C3 */
2010
2011 static struct omap_i2c_dev_attr i2c3_dev_attr = {
2012 .fifo_depth = 64, /* bytes */
2013 };
2014
2015 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
2016 { .irq = INT_34XX_I2C3_IRQ, },
2017 };
2018
2019 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
2020 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
2021 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
2022 };
2023
2024 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
2025 &omap3_l4_core__i2c3,
2026 };
2027
2028 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
2029 .name = "i2c3",
2030 .mpu_irqs = i2c3_mpu_irqs,
2031 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2032 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
2033 .sdma_reqs = i2c3_sdma_reqs,
2034 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
2035 .main_clk = "i2c3_fck",
2036 .prcm = {
2037 .omap2 = {
2038 .module_offs = CORE_MOD,
2039 .prcm_reg_id = 1,
2040 .module_bit = OMAP3430_EN_I2C3_SHIFT,
2041 .idlest_reg_id = 1,
2042 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
2043 },
2044 },
2045 .slaves = omap3xxx_i2c3_slaves,
2046 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
2047 .class = &i2c_class,
2048 .dev_attr = &i2c3_dev_attr,
2049 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2050 };
2051
2052 /* l4_wkup -> gpio1 */
2053 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2054 {
2055 .pa_start = 0x48310000,
2056 .pa_end = 0x483101ff,
2057 .flags = ADDR_TYPE_RT
2058 },
2059 };
2060
2061 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2062 .master = &omap3xxx_l4_wkup_hwmod,
2063 .slave = &omap3xxx_gpio1_hwmod,
2064 .addr = omap3xxx_gpio1_addrs,
2065 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2066 .user = OCP_USER_MPU | OCP_USER_SDMA,
2067 };
2068
2069 /* l4_per -> gpio2 */
2070 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2071 {
2072 .pa_start = 0x49050000,
2073 .pa_end = 0x490501ff,
2074 .flags = ADDR_TYPE_RT
2075 },
2076 };
2077
2078 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2079 .master = &omap3xxx_l4_per_hwmod,
2080 .slave = &omap3xxx_gpio2_hwmod,
2081 .addr = omap3xxx_gpio2_addrs,
2082 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2083 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084 };
2085
2086 /* l4_per -> gpio3 */
2087 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2088 {
2089 .pa_start = 0x49052000,
2090 .pa_end = 0x490521ff,
2091 .flags = ADDR_TYPE_RT
2092 },
2093 };
2094
2095 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2096 .master = &omap3xxx_l4_per_hwmod,
2097 .slave = &omap3xxx_gpio3_hwmod,
2098 .addr = omap3xxx_gpio3_addrs,
2099 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2100 .user = OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102
2103 /* l4_per -> gpio4 */
2104 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2105 {
2106 .pa_start = 0x49054000,
2107 .pa_end = 0x490541ff,
2108 .flags = ADDR_TYPE_RT
2109 },
2110 };
2111
2112 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2113 .master = &omap3xxx_l4_per_hwmod,
2114 .slave = &omap3xxx_gpio4_hwmod,
2115 .addr = omap3xxx_gpio4_addrs,
2116 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 /* l4_per -> gpio5 */
2121 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2122 {
2123 .pa_start = 0x49056000,
2124 .pa_end = 0x490561ff,
2125 .flags = ADDR_TYPE_RT
2126 },
2127 };
2128
2129 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2130 .master = &omap3xxx_l4_per_hwmod,
2131 .slave = &omap3xxx_gpio5_hwmod,
2132 .addr = omap3xxx_gpio5_addrs,
2133 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2134 .user = OCP_USER_MPU | OCP_USER_SDMA,
2135 };
2136
2137 /* l4_per -> gpio6 */
2138 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2139 {
2140 .pa_start = 0x49058000,
2141 .pa_end = 0x490581ff,
2142 .flags = ADDR_TYPE_RT
2143 },
2144 };
2145
2146 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2147 .master = &omap3xxx_l4_per_hwmod,
2148 .slave = &omap3xxx_gpio6_hwmod,
2149 .addr = omap3xxx_gpio6_addrs,
2150 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2151 .user = OCP_USER_MPU | OCP_USER_SDMA,
2152 };
2153
2154 /*
2155 * 'gpio' class
2156 * general purpose io module
2157 */
2158
2159 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2160 .rev_offs = 0x0000,
2161 .sysc_offs = 0x0010,
2162 .syss_offs = 0x0014,
2163 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2164 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2165 SYSS_HAS_RESET_STATUS),
2166 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2167 .sysc_fields = &omap_hwmod_sysc_type1,
2168 };
2169
2170 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2171 .name = "gpio",
2172 .sysc = &omap3xxx_gpio_sysc,
2173 .rev = 1,
2174 };
2175
2176 /* gpio_dev_attr*/
2177 static struct omap_gpio_dev_attr gpio_dev_attr = {
2178 .bank_width = 32,
2179 .dbck_flag = true,
2180 };
2181
2182 /* gpio1 */
2183 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2184 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2185 };
2186
2187 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2188 { .role = "dbclk", .clk = "gpio1_dbck", },
2189 };
2190
2191 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2192 &omap3xxx_l4_wkup__gpio1,
2193 };
2194
2195 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2196 .name = "gpio1",
2197 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2198 .mpu_irqs = omap3xxx_gpio1_irqs,
2199 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2200 .main_clk = "gpio1_ick",
2201 .opt_clks = gpio1_opt_clks,
2202 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2203 .prcm = {
2204 .omap2 = {
2205 .prcm_reg_id = 1,
2206 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2207 .module_offs = WKUP_MOD,
2208 .idlest_reg_id = 1,
2209 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2210 },
2211 },
2212 .slaves = omap3xxx_gpio1_slaves,
2213 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2214 .class = &omap3xxx_gpio_hwmod_class,
2215 .dev_attr = &gpio_dev_attr,
2216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2217 };
2218
2219 /* gpio2 */
2220 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2221 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2222 };
2223
2224 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2225 { .role = "dbclk", .clk = "gpio2_dbck", },
2226 };
2227
2228 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2229 &omap3xxx_l4_per__gpio2,
2230 };
2231
2232 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2233 .name = "gpio2",
2234 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2235 .mpu_irqs = omap3xxx_gpio2_irqs,
2236 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2237 .main_clk = "gpio2_ick",
2238 .opt_clks = gpio2_opt_clks,
2239 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2240 .prcm = {
2241 .omap2 = {
2242 .prcm_reg_id = 1,
2243 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2244 .module_offs = OMAP3430_PER_MOD,
2245 .idlest_reg_id = 1,
2246 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2247 },
2248 },
2249 .slaves = omap3xxx_gpio2_slaves,
2250 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2251 .class = &omap3xxx_gpio_hwmod_class,
2252 .dev_attr = &gpio_dev_attr,
2253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2254 };
2255
2256 /* gpio3 */
2257 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2258 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2259 };
2260
2261 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2262 { .role = "dbclk", .clk = "gpio3_dbck", },
2263 };
2264
2265 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2266 &omap3xxx_l4_per__gpio3,
2267 };
2268
2269 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2270 .name = "gpio3",
2271 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2272 .mpu_irqs = omap3xxx_gpio3_irqs,
2273 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2274 .main_clk = "gpio3_ick",
2275 .opt_clks = gpio3_opt_clks,
2276 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2277 .prcm = {
2278 .omap2 = {
2279 .prcm_reg_id = 1,
2280 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2281 .module_offs = OMAP3430_PER_MOD,
2282 .idlest_reg_id = 1,
2283 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2284 },
2285 },
2286 .slaves = omap3xxx_gpio3_slaves,
2287 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2288 .class = &omap3xxx_gpio_hwmod_class,
2289 .dev_attr = &gpio_dev_attr,
2290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2291 };
2292
2293 /* gpio4 */
2294 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2295 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2296 };
2297
2298 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2299 { .role = "dbclk", .clk = "gpio4_dbck", },
2300 };
2301
2302 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2303 &omap3xxx_l4_per__gpio4,
2304 };
2305
2306 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2307 .name = "gpio4",
2308 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2309 .mpu_irqs = omap3xxx_gpio4_irqs,
2310 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2311 .main_clk = "gpio4_ick",
2312 .opt_clks = gpio4_opt_clks,
2313 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2314 .prcm = {
2315 .omap2 = {
2316 .prcm_reg_id = 1,
2317 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2318 .module_offs = OMAP3430_PER_MOD,
2319 .idlest_reg_id = 1,
2320 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2321 },
2322 },
2323 .slaves = omap3xxx_gpio4_slaves,
2324 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2325 .class = &omap3xxx_gpio_hwmod_class,
2326 .dev_attr = &gpio_dev_attr,
2327 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2328 };
2329
2330 /* gpio5 */
2331 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2332 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2333 };
2334
2335 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2336 { .role = "dbclk", .clk = "gpio5_dbck", },
2337 };
2338
2339 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2340 &omap3xxx_l4_per__gpio5,
2341 };
2342
2343 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2344 .name = "gpio5",
2345 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2346 .mpu_irqs = omap3xxx_gpio5_irqs,
2347 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2348 .main_clk = "gpio5_ick",
2349 .opt_clks = gpio5_opt_clks,
2350 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2351 .prcm = {
2352 .omap2 = {
2353 .prcm_reg_id = 1,
2354 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2355 .module_offs = OMAP3430_PER_MOD,
2356 .idlest_reg_id = 1,
2357 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2358 },
2359 },
2360 .slaves = omap3xxx_gpio5_slaves,
2361 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2362 .class = &omap3xxx_gpio_hwmod_class,
2363 .dev_attr = &gpio_dev_attr,
2364 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2365 };
2366
2367 /* gpio6 */
2368 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2369 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2370 };
2371
2372 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2373 { .role = "dbclk", .clk = "gpio6_dbck", },
2374 };
2375
2376 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2377 &omap3xxx_l4_per__gpio6,
2378 };
2379
2380 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2381 .name = "gpio6",
2382 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2383 .mpu_irqs = omap3xxx_gpio6_irqs,
2384 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2385 .main_clk = "gpio6_ick",
2386 .opt_clks = gpio6_opt_clks,
2387 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2388 .prcm = {
2389 .omap2 = {
2390 .prcm_reg_id = 1,
2391 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2392 .module_offs = OMAP3430_PER_MOD,
2393 .idlest_reg_id = 1,
2394 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2395 },
2396 },
2397 .slaves = omap3xxx_gpio6_slaves,
2398 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2399 .class = &omap3xxx_gpio_hwmod_class,
2400 .dev_attr = &gpio_dev_attr,
2401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2402 };
2403
2404 /* dma_system -> L3 */
2405 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2406 .master = &omap3xxx_dma_system_hwmod,
2407 .slave = &omap3xxx_l3_main_hwmod,
2408 .clk = "core_l3_ick",
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* dma attributes */
2413 static struct omap_dma_dev_attr dma_dev_attr = {
2414 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2415 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2416 .lch_count = 32,
2417 };
2418
2419 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2420 .rev_offs = 0x0000,
2421 .sysc_offs = 0x002c,
2422 .syss_offs = 0x0028,
2423 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2424 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2425 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2426 SYSS_HAS_RESET_STATUS),
2427 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2428 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2429 .sysc_fields = &omap_hwmod_sysc_type1,
2430 };
2431
2432 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2433 .name = "dma",
2434 .sysc = &omap3xxx_dma_sysc,
2435 };
2436
2437 /* dma_system */
2438 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2439 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2440 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2441 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2442 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2443 };
2444
2445 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2446 {
2447 .pa_start = 0x48056000,
2448 .pa_end = 0x48056fff,
2449 .flags = ADDR_TYPE_RT
2450 },
2451 };
2452
2453 /* dma_system master ports */
2454 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2455 &omap3xxx_dma_system__l3,
2456 };
2457
2458 /* l4_cfg -> dma_system */
2459 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2460 .master = &omap3xxx_l4_core_hwmod,
2461 .slave = &omap3xxx_dma_system_hwmod,
2462 .clk = "core_l4_ick",
2463 .addr = omap3xxx_dma_system_addrs,
2464 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467
2468 /* dma_system slave ports */
2469 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2470 &omap3xxx_l4_core__dma_system,
2471 };
2472
2473 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2474 .name = "dma",
2475 .class = &omap3xxx_dma_hwmod_class,
2476 .mpu_irqs = omap3xxx_dma_system_irqs,
2477 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2478 .main_clk = "core_l3_ick",
2479 .prcm = {
2480 .omap2 = {
2481 .module_offs = CORE_MOD,
2482 .prcm_reg_id = 1,
2483 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2484 .idlest_reg_id = 1,
2485 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2486 },
2487 },
2488 .slaves = omap3xxx_dma_system_slaves,
2489 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2490 .masters = omap3xxx_dma_system_masters,
2491 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2492 .dev_attr = &dma_dev_attr,
2493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2494 .flags = HWMOD_NO_IDLEST,
2495 };
2496
2497 /*
2498 * 'mcbsp' class
2499 * multi channel buffered serial port controller
2500 */
2501
2502 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2503 .sysc_offs = 0x008c,
2504 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2505 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2506 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2507 .sysc_fields = &omap_hwmod_sysc_type1,
2508 .clockact = 0x2,
2509 };
2510
2511 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2512 .name = "mcbsp",
2513 .sysc = &omap3xxx_mcbsp_sysc,
2514 .rev = MCBSP_CONFIG_TYPE3,
2515 };
2516
2517 /* mcbsp1 */
2518 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2519 { .name = "irq", .irq = 16 },
2520 { .name = "tx", .irq = 59 },
2521 { .name = "rx", .irq = 60 },
2522 };
2523
2524 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2525 { .name = "rx", .dma_req = 32 },
2526 { .name = "tx", .dma_req = 31 },
2527 };
2528
2529 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2530 {
2531 .name = "mpu",
2532 .pa_start = 0x48074000,
2533 .pa_end = 0x480740ff,
2534 .flags = ADDR_TYPE_RT
2535 },
2536 };
2537
2538 /* l4_core -> mcbsp1 */
2539 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2540 .master = &omap3xxx_l4_core_hwmod,
2541 .slave = &omap3xxx_mcbsp1_hwmod,
2542 .clk = "mcbsp1_ick",
2543 .addr = omap3xxx_mcbsp1_addrs,
2544 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2545 .user = OCP_USER_MPU | OCP_USER_SDMA,
2546 };
2547
2548 /* mcbsp1 slave ports */
2549 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2550 &omap3xxx_l4_core__mcbsp1,
2551 };
2552
2553 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2554 .name = "mcbsp1",
2555 .class = &omap3xxx_mcbsp_hwmod_class,
2556 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2557 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2558 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2559 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2560 .main_clk = "mcbsp1_fck",
2561 .prcm = {
2562 .omap2 = {
2563 .prcm_reg_id = 1,
2564 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2565 .module_offs = CORE_MOD,
2566 .idlest_reg_id = 1,
2567 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2568 },
2569 },
2570 .slaves = omap3xxx_mcbsp1_slaves,
2571 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2572 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2573 };
2574
2575 /* mcbsp2 */
2576 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2577 { .name = "irq", .irq = 17 },
2578 { .name = "tx", .irq = 62 },
2579 { .name = "rx", .irq = 63 },
2580 };
2581
2582 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2583 { .name = "rx", .dma_req = 34 },
2584 { .name = "tx", .dma_req = 33 },
2585 };
2586
2587 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2588 {
2589 .name = "mpu",
2590 .pa_start = 0x49022000,
2591 .pa_end = 0x490220ff,
2592 .flags = ADDR_TYPE_RT
2593 },
2594 };
2595
2596 /* l4_per -> mcbsp2 */
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2598 .master = &omap3xxx_l4_per_hwmod,
2599 .slave = &omap3xxx_mcbsp2_hwmod,
2600 .clk = "mcbsp2_ick",
2601 .addr = omap3xxx_mcbsp2_addrs,
2602 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604 };
2605
2606 /* mcbsp2 slave ports */
2607 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2608 &omap3xxx_l4_per__mcbsp2,
2609 };
2610
2611 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2612 .sidetone = "mcbsp2_sidetone",
2613 };
2614
2615 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2616 .name = "mcbsp2",
2617 .class = &omap3xxx_mcbsp_hwmod_class,
2618 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2619 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2620 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2621 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2622 .main_clk = "mcbsp2_fck",
2623 .prcm = {
2624 .omap2 = {
2625 .prcm_reg_id = 1,
2626 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2627 .module_offs = OMAP3430_PER_MOD,
2628 .idlest_reg_id = 1,
2629 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2630 },
2631 },
2632 .slaves = omap3xxx_mcbsp2_slaves,
2633 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2634 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2635 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2636 };
2637
2638 /* mcbsp3 */
2639 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2640 { .name = "irq", .irq = 22 },
2641 { .name = "tx", .irq = 89 },
2642 { .name = "rx", .irq = 90 },
2643 };
2644
2645 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2646 { .name = "rx", .dma_req = 18 },
2647 { .name = "tx", .dma_req = 17 },
2648 };
2649
2650 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2651 {
2652 .name = "mpu",
2653 .pa_start = 0x49024000,
2654 .pa_end = 0x490240ff,
2655 .flags = ADDR_TYPE_RT
2656 },
2657 };
2658
2659 /* l4_per -> mcbsp3 */
2660 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2661 .master = &omap3xxx_l4_per_hwmod,
2662 .slave = &omap3xxx_mcbsp3_hwmod,
2663 .clk = "mcbsp3_ick",
2664 .addr = omap3xxx_mcbsp3_addrs,
2665 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* mcbsp3 slave ports */
2670 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2671 &omap3xxx_l4_per__mcbsp3,
2672 };
2673
2674 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2675 .sidetone = "mcbsp3_sidetone",
2676 };
2677
2678 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2679 .name = "mcbsp3",
2680 .class = &omap3xxx_mcbsp_hwmod_class,
2681 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2682 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2683 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2684 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2685 .main_clk = "mcbsp3_fck",
2686 .prcm = {
2687 .omap2 = {
2688 .prcm_reg_id = 1,
2689 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2690 .module_offs = OMAP3430_PER_MOD,
2691 .idlest_reg_id = 1,
2692 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2693 },
2694 },
2695 .slaves = omap3xxx_mcbsp3_slaves,
2696 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2697 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2698 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2699 };
2700
2701 /* mcbsp4 */
2702 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2703 { .name = "irq", .irq = 23 },
2704 { .name = "tx", .irq = 54 },
2705 { .name = "rx", .irq = 55 },
2706 };
2707
2708 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2709 { .name = "rx", .dma_req = 20 },
2710 { .name = "tx", .dma_req = 19 },
2711 };
2712
2713 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2714 {
2715 .name = "mpu",
2716 .pa_start = 0x49026000,
2717 .pa_end = 0x490260ff,
2718 .flags = ADDR_TYPE_RT
2719 },
2720 };
2721
2722 /* l4_per -> mcbsp4 */
2723 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2724 .master = &omap3xxx_l4_per_hwmod,
2725 .slave = &omap3xxx_mcbsp4_hwmod,
2726 .clk = "mcbsp4_ick",
2727 .addr = omap3xxx_mcbsp4_addrs,
2728 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2729 .user = OCP_USER_MPU | OCP_USER_SDMA,
2730 };
2731
2732 /* mcbsp4 slave ports */
2733 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2734 &omap3xxx_l4_per__mcbsp4,
2735 };
2736
2737 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2738 .name = "mcbsp4",
2739 .class = &omap3xxx_mcbsp_hwmod_class,
2740 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2741 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2742 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2743 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2744 .main_clk = "mcbsp4_fck",
2745 .prcm = {
2746 .omap2 = {
2747 .prcm_reg_id = 1,
2748 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2749 .module_offs = OMAP3430_PER_MOD,
2750 .idlest_reg_id = 1,
2751 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2752 },
2753 },
2754 .slaves = omap3xxx_mcbsp4_slaves,
2755 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2756 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2757 };
2758
2759 /* mcbsp5 */
2760 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2761 { .name = "irq", .irq = 27 },
2762 { .name = "tx", .irq = 81 },
2763 { .name = "rx", .irq = 82 },
2764 };
2765
2766 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2767 { .name = "rx", .dma_req = 22 },
2768 { .name = "tx", .dma_req = 21 },
2769 };
2770
2771 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2772 {
2773 .name = "mpu",
2774 .pa_start = 0x48096000,
2775 .pa_end = 0x480960ff,
2776 .flags = ADDR_TYPE_RT
2777 },
2778 };
2779
2780 /* l4_core -> mcbsp5 */
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2782 .master = &omap3xxx_l4_core_hwmod,
2783 .slave = &omap3xxx_mcbsp5_hwmod,
2784 .clk = "mcbsp5_ick",
2785 .addr = omap3xxx_mcbsp5_addrs,
2786 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2788 };
2789
2790 /* mcbsp5 slave ports */
2791 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2792 &omap3xxx_l4_core__mcbsp5,
2793 };
2794
2795 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2796 .name = "mcbsp5",
2797 .class = &omap3xxx_mcbsp_hwmod_class,
2798 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2799 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2800 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2801 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2802 .main_clk = "mcbsp5_fck",
2803 .prcm = {
2804 .omap2 = {
2805 .prcm_reg_id = 1,
2806 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2807 .module_offs = CORE_MOD,
2808 .idlest_reg_id = 1,
2809 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2810 },
2811 },
2812 .slaves = omap3xxx_mcbsp5_slaves,
2813 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2814 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2815 };
2816 /* 'mcbsp sidetone' class */
2817
2818 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2819 .sysc_offs = 0x0010,
2820 .sysc_flags = SYSC_HAS_AUTOIDLE,
2821 .sysc_fields = &omap_hwmod_sysc_type1,
2822 };
2823
2824 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2825 .name = "mcbsp_sidetone",
2826 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2827 };
2828
2829 /* mcbsp2_sidetone */
2830 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2831 { .name = "irq", .irq = 4 },
2832 };
2833
2834 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2835 {
2836 .name = "sidetone",
2837 .pa_start = 0x49028000,
2838 .pa_end = 0x490280ff,
2839 .flags = ADDR_TYPE_RT
2840 },
2841 };
2842
2843 /* l4_per -> mcbsp2_sidetone */
2844 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2845 .master = &omap3xxx_l4_per_hwmod,
2846 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2847 .clk = "mcbsp2_ick",
2848 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2849 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2850 .user = OCP_USER_MPU,
2851 };
2852
2853 /* mcbsp2_sidetone slave ports */
2854 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2855 &omap3xxx_l4_per__mcbsp2_sidetone,
2856 };
2857
2858 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2859 .name = "mcbsp2_sidetone",
2860 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2861 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2862 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2863 .main_clk = "mcbsp2_fck",
2864 .prcm = {
2865 .omap2 = {
2866 .prcm_reg_id = 1,
2867 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2868 .module_offs = OMAP3430_PER_MOD,
2869 .idlest_reg_id = 1,
2870 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2871 },
2872 },
2873 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2874 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2875 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2876 };
2877
2878 /* mcbsp3_sidetone */
2879 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2880 { .name = "irq", .irq = 5 },
2881 };
2882
2883 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2884 {
2885 .name = "sidetone",
2886 .pa_start = 0x4902A000,
2887 .pa_end = 0x4902A0ff,
2888 .flags = ADDR_TYPE_RT
2889 },
2890 };
2891
2892 /* l4_per -> mcbsp3_sidetone */
2893 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2894 .master = &omap3xxx_l4_per_hwmod,
2895 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2896 .clk = "mcbsp3_ick",
2897 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2898 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2899 .user = OCP_USER_MPU,
2900 };
2901
2902 /* mcbsp3_sidetone slave ports */
2903 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2904 &omap3xxx_l4_per__mcbsp3_sidetone,
2905 };
2906
2907 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2908 .name = "mcbsp3_sidetone",
2909 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2910 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2911 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2912 .main_clk = "mcbsp3_fck",
2913 .prcm = {
2914 .omap2 = {
2915 .prcm_reg_id = 1,
2916 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2917 .module_offs = OMAP3430_PER_MOD,
2918 .idlest_reg_id = 1,
2919 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2920 },
2921 },
2922 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2923 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2924 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2925 };
2926
2927
2928 /* SR common */
2929 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2930 .clkact_shift = 20,
2931 };
2932
2933 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2934 .sysc_offs = 0x24,
2935 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2936 .clockact = CLOCKACT_TEST_ICLK,
2937 .sysc_fields = &omap34xx_sr_sysc_fields,
2938 };
2939
2940 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2941 .name = "smartreflex",
2942 .sysc = &omap34xx_sr_sysc,
2943 .rev = 1,
2944 };
2945
2946 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2947 .sidle_shift = 24,
2948 .enwkup_shift = 26
2949 };
2950
2951 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2952 .sysc_offs = 0x38,
2953 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2954 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2955 SYSC_NO_CACHE),
2956 .sysc_fields = &omap36xx_sr_sysc_fields,
2957 };
2958
2959 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2960 .name = "smartreflex",
2961 .sysc = &omap36xx_sr_sysc,
2962 .rev = 2,
2963 };
2964
2965 /* SR1 */
2966 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2967 .sensor_voltdm_name = "mpu_iva",
2968 };
2969
2970 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2971 &omap3_l4_core__sr1,
2972 };
2973
2974 static struct omap_hwmod omap34xx_sr1_hwmod = {
2975 .name = "sr1_hwmod",
2976 .class = &omap34xx_smartreflex_hwmod_class,
2977 .main_clk = "sr1_fck",
2978 .prcm = {
2979 .omap2 = {
2980 .prcm_reg_id = 1,
2981 .module_bit = OMAP3430_EN_SR1_SHIFT,
2982 .module_offs = WKUP_MOD,
2983 .idlest_reg_id = 1,
2984 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2985 },
2986 },
2987 .slaves = omap3_sr1_slaves,
2988 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2989 .dev_attr = &sr1_dev_attr,
2990 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2991 CHIP_IS_OMAP3430ES3_0 |
2992 CHIP_IS_OMAP3430ES3_1),
2993 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2994 .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
2995 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2996 };
2997
2998 static struct omap_hwmod omap36xx_sr1_hwmod = {
2999 .name = "sr1_hwmod",
3000 .class = &omap36xx_smartreflex_hwmod_class,
3001 .main_clk = "sr1_fck",
3002 .prcm = {
3003 .omap2 = {
3004 .prcm_reg_id = 1,
3005 .module_bit = OMAP3430_EN_SR1_SHIFT,
3006 .module_offs = WKUP_MOD,
3007 .idlest_reg_id = 1,
3008 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
3009 },
3010 },
3011 .slaves = omap3_sr1_slaves,
3012 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
3013 .dev_attr = &sr1_dev_attr,
3014 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
3015 .mpu_irqs = omap3_smartreflex_mpu_irqs,
3016 .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_mpu_irqs),
3017 };
3018
3019 /* SR2 */
3020 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
3021 .sensor_voltdm_name = "core",
3022 };
3023
3024 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
3025 &omap3_l4_core__sr2,
3026 };
3027
3028 static struct omap_hwmod omap34xx_sr2_hwmod = {
3029 .name = "sr2_hwmod",
3030 .class = &omap34xx_smartreflex_hwmod_class,
3031 .main_clk = "sr2_fck",
3032 .prcm = {
3033 .omap2 = {
3034 .prcm_reg_id = 1,
3035 .module_bit = OMAP3430_EN_SR2_SHIFT,
3036 .module_offs = WKUP_MOD,
3037 .idlest_reg_id = 1,
3038 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
3039 },
3040 },
3041 .slaves = omap3_sr2_slaves,
3042 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
3043 .dev_attr = &sr2_dev_attr,
3044 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
3045 CHIP_IS_OMAP3430ES3_0 |
3046 CHIP_IS_OMAP3430ES3_1),
3047 .mpu_irqs = omap3_smartreflex_core_irqs,
3048 .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
3049 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3050 };
3051
3052 static struct omap_hwmod omap36xx_sr2_hwmod = {
3053 .name = "sr2_hwmod",
3054 .class = &omap36xx_smartreflex_hwmod_class,
3055 .main_clk = "sr2_fck",
3056 .prcm = {
3057 .omap2 = {
3058 .prcm_reg_id = 1,
3059 .module_bit = OMAP3430_EN_SR2_SHIFT,
3060 .module_offs = WKUP_MOD,
3061 .idlest_reg_id = 1,
3062 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
3063 },
3064 },
3065 .slaves = omap3_sr2_slaves,
3066 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
3067 .dev_attr = &sr2_dev_attr,
3068 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
3069 .mpu_irqs = omap3_smartreflex_core_irqs,
3070 .mpu_irqs_cnt = ARRAY_SIZE(omap3_smartreflex_core_irqs),
3071 };
3072
3073 /*
3074 * 'mailbox' class
3075 * mailbox module allowing communication between the on-chip processors
3076 * using a queued mailbox-interrupt mechanism.
3077 */
3078
3079 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3080 .rev_offs = 0x000,
3081 .sysc_offs = 0x010,
3082 .syss_offs = 0x014,
3083 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3084 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3085 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3086 .sysc_fields = &omap_hwmod_sysc_type1,
3087 };
3088
3089 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3090 .name = "mailbox",
3091 .sysc = &omap3xxx_mailbox_sysc,
3092 };
3093
3094 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3095 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3096 { .irq = 26 },
3097 };
3098
3099 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3100 {
3101 .pa_start = 0x48094000,
3102 .pa_end = 0x480941ff,
3103 .flags = ADDR_TYPE_RT,
3104 },
3105 };
3106
3107 /* l4_core -> mailbox */
3108 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3109 .master = &omap3xxx_l4_core_hwmod,
3110 .slave = &omap3xxx_mailbox_hwmod,
3111 .addr = omap3xxx_mailbox_addrs,
3112 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3113 .user = OCP_USER_MPU | OCP_USER_SDMA,
3114 };
3115
3116 /* mailbox slave ports */
3117 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3118 &omap3xxx_l4_core__mailbox,
3119 };
3120
3121 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3122 .name = "mailbox",
3123 .class = &omap3xxx_mailbox_hwmod_class,
3124 .mpu_irqs = omap3xxx_mailbox_irqs,
3125 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3126 .main_clk = "mailboxes_ick",
3127 .prcm = {
3128 .omap2 = {
3129 .prcm_reg_id = 1,
3130 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3131 .module_offs = CORE_MOD,
3132 .idlest_reg_id = 1,
3133 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3134 },
3135 },
3136 .slaves = omap3xxx_mailbox_slaves,
3137 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3139 };
3140
3141 /* l4 core -> mcspi1 interface */
3142 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3143 {
3144 .pa_start = 0x48098000,
3145 .pa_end = 0x480980ff,
3146 .flags = ADDR_TYPE_RT,
3147 },
3148 };
3149
3150 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3151 .master = &omap3xxx_l4_core_hwmod,
3152 .slave = &omap34xx_mcspi1,
3153 .clk = "mcspi1_ick",
3154 .addr = omap34xx_mcspi1_addr_space,
3155 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157 };
3158
3159 /* l4 core -> mcspi2 interface */
3160 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3161 {
3162 .pa_start = 0x4809a000,
3163 .pa_end = 0x4809a0ff,
3164 .flags = ADDR_TYPE_RT,
3165 },
3166 };
3167
3168 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3169 .master = &omap3xxx_l4_core_hwmod,
3170 .slave = &omap34xx_mcspi2,
3171 .clk = "mcspi2_ick",
3172 .addr = omap34xx_mcspi2_addr_space,
3173 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3176
3177 /* l4 core -> mcspi3 interface */
3178 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3179 {
3180 .pa_start = 0x480b8000,
3181 .pa_end = 0x480b80ff,
3182 .flags = ADDR_TYPE_RT,
3183 },
3184 };
3185
3186 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3187 .master = &omap3xxx_l4_core_hwmod,
3188 .slave = &omap34xx_mcspi3,
3189 .clk = "mcspi3_ick",
3190 .addr = omap34xx_mcspi3_addr_space,
3191 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3192 .user = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* l4 core -> mcspi4 interface */
3196 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3197 {
3198 .pa_start = 0x480ba000,
3199 .pa_end = 0x480ba0ff,
3200 .flags = ADDR_TYPE_RT,
3201 },
3202 };
3203
3204 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3205 .master = &omap3xxx_l4_core_hwmod,
3206 .slave = &omap34xx_mcspi4,
3207 .clk = "mcspi4_ick",
3208 .addr = omap34xx_mcspi4_addr_space,
3209 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3210 .user = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3212
3213 /*
3214 * 'mcspi' class
3215 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3216 * bus
3217 */
3218
3219 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3220 .rev_offs = 0x0000,
3221 .sysc_offs = 0x0010,
3222 .syss_offs = 0x0014,
3223 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3224 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3225 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3227 .sysc_fields = &omap_hwmod_sysc_type1,
3228 };
3229
3230 static struct omap_hwmod_class omap34xx_mcspi_class = {
3231 .name = "mcspi",
3232 .sysc = &omap34xx_mcspi_sysc,
3233 .rev = OMAP3_MCSPI_REV,
3234 };
3235
3236 /* mcspi1 */
3237 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3238 { .name = "irq", .irq = 65 },
3239 };
3240
3241 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3242 { .name = "tx0", .dma_req = 35 },
3243 { .name = "rx0", .dma_req = 36 },
3244 { .name = "tx1", .dma_req = 37 },
3245 { .name = "rx1", .dma_req = 38 },
3246 { .name = "tx2", .dma_req = 39 },
3247 { .name = "rx2", .dma_req = 40 },
3248 { .name = "tx3", .dma_req = 41 },
3249 { .name = "rx3", .dma_req = 42 },
3250 };
3251
3252 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3253 &omap34xx_l4_core__mcspi1,
3254 };
3255
3256 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3257 .num_chipselect = 4,
3258 };
3259
3260 static struct omap_hwmod omap34xx_mcspi1 = {
3261 .name = "mcspi1",
3262 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
3263 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3264 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3265 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3266 .main_clk = "mcspi1_fck",
3267 .prcm = {
3268 .omap2 = {
3269 .module_offs = CORE_MOD,
3270 .prcm_reg_id = 1,
3271 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3272 .idlest_reg_id = 1,
3273 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3274 },
3275 },
3276 .slaves = omap34xx_mcspi1_slaves,
3277 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3278 .class = &omap34xx_mcspi_class,
3279 .dev_attr = &omap_mcspi1_dev_attr,
3280 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3281 };
3282
3283 /* mcspi2 */
3284 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3285 { .name = "irq", .irq = 66 },
3286 };
3287
3288 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3289 { .name = "tx0", .dma_req = 43 },
3290 { .name = "rx0", .dma_req = 44 },
3291 { .name = "tx1", .dma_req = 45 },
3292 { .name = "rx1", .dma_req = 46 },
3293 };
3294
3295 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3296 &omap34xx_l4_core__mcspi2,
3297 };
3298
3299 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3300 .num_chipselect = 2,
3301 };
3302
3303 static struct omap_hwmod omap34xx_mcspi2 = {
3304 .name = "mcspi2",
3305 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
3306 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3307 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3308 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3309 .main_clk = "mcspi2_fck",
3310 .prcm = {
3311 .omap2 = {
3312 .module_offs = CORE_MOD,
3313 .prcm_reg_id = 1,
3314 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3315 .idlest_reg_id = 1,
3316 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3317 },
3318 },
3319 .slaves = omap34xx_mcspi2_slaves,
3320 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3321 .class = &omap34xx_mcspi_class,
3322 .dev_attr = &omap_mcspi2_dev_attr,
3323 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3324 };
3325
3326 /* mcspi3 */
3327 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3328 { .name = "irq", .irq = 91 }, /* 91 */
3329 };
3330
3331 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3332 { .name = "tx0", .dma_req = 15 },
3333 { .name = "rx0", .dma_req = 16 },
3334 { .name = "tx1", .dma_req = 23 },
3335 { .name = "rx1", .dma_req = 24 },
3336 };
3337
3338 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3339 &omap34xx_l4_core__mcspi3,
3340 };
3341
3342 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3343 .num_chipselect = 2,
3344 };
3345
3346 static struct omap_hwmod omap34xx_mcspi3 = {
3347 .name = "mcspi3",
3348 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3349 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3350 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3351 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3352 .main_clk = "mcspi3_fck",
3353 .prcm = {
3354 .omap2 = {
3355 .module_offs = CORE_MOD,
3356 .prcm_reg_id = 1,
3357 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3358 .idlest_reg_id = 1,
3359 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3360 },
3361 },
3362 .slaves = omap34xx_mcspi3_slaves,
3363 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3364 .class = &omap34xx_mcspi_class,
3365 .dev_attr = &omap_mcspi3_dev_attr,
3366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3367 };
3368
3369 /* SPI4 */
3370 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3371 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3372 };
3373
3374 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3375 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3376 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3377 };
3378
3379 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3380 &omap34xx_l4_core__mcspi4,
3381 };
3382
3383 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3384 .num_chipselect = 1,
3385 };
3386
3387 static struct omap_hwmod omap34xx_mcspi4 = {
3388 .name = "mcspi4",
3389 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3390 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3391 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3392 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3393 .main_clk = "mcspi4_fck",
3394 .prcm = {
3395 .omap2 = {
3396 .module_offs = CORE_MOD,
3397 .prcm_reg_id = 1,
3398 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3399 .idlest_reg_id = 1,
3400 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3401 },
3402 },
3403 .slaves = omap34xx_mcspi4_slaves,
3404 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3405 .class = &omap34xx_mcspi_class,
3406 .dev_attr = &omap_mcspi4_dev_attr,
3407 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3408 };
3409
3410 /*
3411 * usbhsotg
3412 */
3413 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3414 .rev_offs = 0x0400,
3415 .sysc_offs = 0x0404,
3416 .syss_offs = 0x0408,
3417 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3418 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3419 SYSC_HAS_AUTOIDLE),
3420 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3421 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3422 .sysc_fields = &omap_hwmod_sysc_type1,
3423 };
3424
3425 static struct omap_hwmod_class usbotg_class = {
3426 .name = "usbotg",
3427 .sysc = &omap3xxx_usbhsotg_sysc,
3428 };
3429 /* usb_otg_hs */
3430 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3431
3432 { .name = "mc", .irq = 92 },
3433 { .name = "dma", .irq = 93 },
3434 };
3435
3436 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3437 .name = "usb_otg_hs",
3438 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3439 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3440 .main_clk = "hsotgusb_ick",
3441 .prcm = {
3442 .omap2 = {
3443 .prcm_reg_id = 1,
3444 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3445 .module_offs = CORE_MOD,
3446 .idlest_reg_id = 1,
3447 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3448 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3449 },
3450 },
3451 .masters = omap3xxx_usbhsotg_masters,
3452 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3453 .slaves = omap3xxx_usbhsotg_slaves,
3454 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3455 .class = &usbotg_class,
3456
3457 /*
3458 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3459 * broken when autoidle is enabled
3460 * workaround is to disable the autoidle bit at module level.
3461 */
3462 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3463 | HWMOD_SWSUP_MSTANDBY,
3464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3465 };
3466
3467 /* usb_otg_hs */
3468 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3469
3470 { .name = "mc", .irq = 71 },
3471 };
3472
3473 static struct omap_hwmod_class am35xx_usbotg_class = {
3474 .name = "am35xx_usbotg",
3475 .sysc = NULL,
3476 };
3477
3478 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3479 .name = "am35x_otg_hs",
3480 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3481 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3482 .main_clk = NULL,
3483 .prcm = {
3484 .omap2 = {
3485 },
3486 },
3487 .masters = am35xx_usbhsotg_masters,
3488 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3489 .slaves = am35xx_usbhsotg_slaves,
3490 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3491 .class = &am35xx_usbotg_class,
3492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3493 };
3494
3495 /* MMC/SD/SDIO common */
3496
3497 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3498 .rev_offs = 0x1fc,
3499 .sysc_offs = 0x10,
3500 .syss_offs = 0x14,
3501 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3502 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3503 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3504 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3505 .sysc_fields = &omap_hwmod_sysc_type1,
3506 };
3507
3508 static struct omap_hwmod_class omap34xx_mmc_class = {
3509 .name = "mmc",
3510 .sysc = &omap34xx_mmc_sysc,
3511 };
3512
3513 /* MMC/SD/SDIO1 */
3514
3515 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3516 { .irq = 83, },
3517 };
3518
3519 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3520 { .name = "tx", .dma_req = 61, },
3521 { .name = "rx", .dma_req = 62, },
3522 };
3523
3524 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3525 { .role = "dbck", .clk = "omap_32k_fck", },
3526 };
3527
3528 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3529 &omap3xxx_l4_core__mmc1,
3530 };
3531
3532 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3533 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3534 };
3535
3536 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3537 .name = "mmc1",
3538 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3539 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3540 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3541 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3542 .opt_clks = omap34xx_mmc1_opt_clks,
3543 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3544 .main_clk = "mmchs1_fck",
3545 .prcm = {
3546 .omap2 = {
3547 .module_offs = CORE_MOD,
3548 .prcm_reg_id = 1,
3549 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3550 .idlest_reg_id = 1,
3551 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3552 },
3553 },
3554 .dev_attr = &mmc1_dev_attr,
3555 .slaves = omap3xxx_mmc1_slaves,
3556 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3557 .class = &omap34xx_mmc_class,
3558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3559 };
3560
3561 /* MMC/SD/SDIO2 */
3562
3563 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3564 { .irq = INT_24XX_MMC2_IRQ, },
3565 };
3566
3567 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3568 { .name = "tx", .dma_req = 47, },
3569 { .name = "rx", .dma_req = 48, },
3570 };
3571
3572 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3573 { .role = "dbck", .clk = "omap_32k_fck", },
3574 };
3575
3576 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3577 &omap3xxx_l4_core__mmc2,
3578 };
3579
3580 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3581 .name = "mmc2",
3582 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3583 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3584 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3585 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3586 .opt_clks = omap34xx_mmc2_opt_clks,
3587 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3588 .main_clk = "mmchs2_fck",
3589 .prcm = {
3590 .omap2 = {
3591 .module_offs = CORE_MOD,
3592 .prcm_reg_id = 1,
3593 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3594 .idlest_reg_id = 1,
3595 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3596 },
3597 },
3598 .slaves = omap3xxx_mmc2_slaves,
3599 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3600 .class = &omap34xx_mmc_class,
3601 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3602 };
3603
3604 /* MMC/SD/SDIO3 */
3605
3606 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3607 { .irq = 94, },
3608 };
3609
3610 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3611 { .name = "tx", .dma_req = 77, },
3612 { .name = "rx", .dma_req = 78, },
3613 };
3614
3615 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3616 { .role = "dbck", .clk = "omap_32k_fck", },
3617 };
3618
3619 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3620 &omap3xxx_l4_core__mmc3,
3621 };
3622
3623 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3624 .name = "mmc3",
3625 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3626 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3627 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3628 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3629 .opt_clks = omap34xx_mmc3_opt_clks,
3630 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3631 .main_clk = "mmchs3_fck",
3632 .prcm = {
3633 .omap2 = {
3634 .prcm_reg_id = 1,
3635 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3636 .idlest_reg_id = 1,
3637 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3638 },
3639 },
3640 .slaves = omap3xxx_mmc3_slaves,
3641 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3642 .class = &omap34xx_mmc_class,
3643 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3644 };
3645
3646 /*
3647 * 'usb_host_hs' class
3648 * high-speed multi-port usb host controller
3649 */
3650 static struct omap_hwmod_ocp_if omap34xx_usb_host_hs__l3_main_2 = {
3651 .master = &omap34xx_usb_host_hs_hwmod,
3652 .slave = &omap3xxx_l3_main_hwmod,
3653 .clk = "core_l3_ick",
3654 .user = OCP_USER_MPU,
3655 };
3656
3657 static struct omap_hwmod_class_sysconfig omap34xx_usb_host_hs_sysc = {
3658 .rev_offs = 0x0000,
3659 .sysc_offs = 0x0010,
3660 .syss_offs = 0x0014,
3661 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
3662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3663 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3664 .sysc_fields = &omap_hwmod_sysc_type1,
3665 };
3666
3667 static struct omap_hwmod_class omap34xx_usb_host_hs_hwmod_class = {
3668 .name = "usbhs_uhh",
3669 .sysc = &omap34xx_usb_host_hs_sysc,
3670 };
3671
3672 static struct omap_hwmod_ocp_if *omap34xx_usb_host_hs_masters[] = {
3673 &omap34xx_usb_host_hs__l3_main_2,
3674 };
3675
3676 static struct omap_hwmod_addr_space omap34xx_usb_host_hs_addrs[] = {
3677 {
3678 .name = "uhh",
3679 .pa_start = 0x48064000,
3680 .pa_end = 0x480643ff,
3681 .flags = ADDR_TYPE_RT
3682 }
3683 };
3684
3685 static struct omap_hwmod_ocp_if omap34xx_l4_cfg__usb_host_hs = {
3686 .master = &omap3xxx_l4_core_hwmod,
3687 .slave = &omap34xx_usb_host_hs_hwmod,
3688 .clk = "l4_ick",
3689 .addr = omap34xx_usb_host_hs_addrs,
3690 .addr_cnt = ARRAY_SIZE(omap34xx_usb_host_hs_addrs),
3691 .user = OCP_USER_MPU | OCP_USER_SDMA,
3692 };
3693
3694 static struct omap_hwmod_ocp_if omap34xx_f128m_cfg__usb_host_hs = {
3695 .clk = "usbhost_120m_fck",
3696 .user = OCP_USER_MPU,
3697 .flags = OCPIF_SWSUP_IDLE,
3698 };
3699
3700 static struct omap_hwmod_ocp_if omap34xx_f48m_cfg__usb_host_hs = {
3701 .clk = "usbhost_48m_fck",
3702 .user = OCP_USER_MPU,
3703 .flags = OCPIF_SWSUP_IDLE,
3704 };
3705
3706 static struct omap_hwmod_ocp_if *omap34xx_usb_host_hs_slaves[] = {
3707 &omap34xx_l4_cfg__usb_host_hs,
3708 &omap34xx_f128m_cfg__usb_host_hs,
3709 &omap34xx_f48m_cfg__usb_host_hs,
3710 };
3711
3712 static struct omap_hwmod omap34xx_usb_host_hs_hwmod = {
3713 .name = "usbhs_uhh",
3714 .class = &omap34xx_usb_host_hs_hwmod_class,
3715 .main_clk = "usbhost_ick",
3716 .prcm = {
3717 .omap2 = {
3718 .module_offs = OMAP3430ES2_USBHOST_MOD,
3719 .prcm_reg_id = 1,
3720 .module_bit = 0,
3721 .idlest_reg_id = 1,
3722 .idlest_idle_bit = 1,
3723 .idlest_stdby_bit = 0,
3724 },
3725 },
3726 .slaves = omap34xx_usb_host_hs_slaves,
3727 .slaves_cnt = ARRAY_SIZE(omap34xx_usb_host_hs_slaves),
3728 .masters = omap34xx_usb_host_hs_masters,
3729 .masters_cnt = ARRAY_SIZE(omap34xx_usb_host_hs_masters),
3730 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3731 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3732 };
3733
3734 /* 'usbhs_ohci' class */
3735 static struct omap_hwmod_ocp_if omap34xx_usbhs_ohci__l3_main_2 = {
3736 .master = &omap34xx_usbhs_ohci_hwmod,
3737 .slave = &omap3xxx_l3_main_hwmod,
3738 .clk = "core_l3_ick",
3739 .user = OCP_USER_MPU,
3740 };
3741
3742 static struct omap_hwmod_class omap34xx_usbhs_ohci_hwmod_class = {
3743 .name = "usbhs_ohci",
3744 };
3745
3746 static struct omap_hwmod_ocp_if *omap34xx_usbhs_ohci_masters[] = {
3747 &omap34xx_usbhs_ohci__l3_main_2,
3748 };
3749
3750 static struct omap_hwmod_irq_info omap34xx_usbhs_ohci_irqs[] = {
3751 { .name = "ohci-irq", .irq = 76 },
3752 };
3753
3754 static struct omap_hwmod_addr_space omap34xx_usbhs_ohci_addrs[] = {
3755 {
3756 .name = "ohci",
3757 .pa_start = 0x48064400,
3758 .pa_end = 0x480647FF,
3759 .flags = ADDR_MAP_ON_INIT
3760 }
3761 };
3762
3763 static struct omap_hwmod_ocp_if omap34xx_l4_cfg__usbhs_ohci = {
3764 .master = &omap3xxx_l4_core_hwmod,
3765 .slave = &omap34xx_usbhs_ohci_hwmod,
3766 .clk = "l4_ick",
3767 .addr = omap34xx_usbhs_ohci_addrs,
3768 .addr_cnt = ARRAY_SIZE(omap34xx_usbhs_ohci_addrs),
3769 .user = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3771
3772 static struct omap_hwmod_ocp_if *omap34xx_usbhs_ohci_slaves[] = {
3773 &omap34xx_l4_cfg__usbhs_ohci,
3774 };
3775
3776 static struct omap_hwmod omap34xx_usbhs_ohci_hwmod = {
3777 .name = "usbhs_ohci",
3778 .class = &omap34xx_usbhs_ohci_hwmod_class,
3779 .mpu_irqs = omap34xx_usbhs_ohci_irqs,
3780 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_usbhs_ohci_irqs),
3781 .slaves = omap34xx_usbhs_ohci_slaves,
3782 .slaves_cnt = ARRAY_SIZE(omap34xx_usbhs_ohci_slaves),
3783 .masters = omap34xx_usbhs_ohci_masters,
3784 .masters_cnt = ARRAY_SIZE(omap34xx_usbhs_ohci_masters),
3785 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
3786 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3787 };
3788
3789 /* 'usbhs_ehci' class */
3790 static struct omap_hwmod_ocp_if omap34xx_usbhs_ehci__l3_main_2 = {
3791 .master = &omap34xx_usbhs_ehci_hwmod,
3792 .slave = &omap3xxx_l3_main_hwmod,
3793 .clk = "core_l3_ick",
3794 .user = OCP_USER_MPU,
3795 };
3796
3797 static struct omap_hwmod_class omap34xx_usbhs_ehci_hwmod_class = {
3798 .name = "usbhs_ehci",
3799 };
3800
3801 static struct omap_hwmod_ocp_if *omap34xx_usbhs_ehci_masters[] = {
3802 &omap34xx_usbhs_ehci__l3_main_2,
3803 };
3804
3805 static struct omap_hwmod_irq_info omap34xx_usbhs_ehci_irqs[] = {
3806 { .name = "ehci-irq", .irq = 77 },
3807 };
3808
3809 static struct omap_hwmod_addr_space omap34xx_usbhs_ehci_addrs[] = {
3810 {
3811 .name = "ehci",
3812 .pa_start = 0x48064800,
3813 .pa_end = 0x48064CFF,
3814 .flags = ADDR_MAP_ON_INIT
3815 }
3816 };
3817
3818 static struct omap_hwmod_ocp_if omap34xx_l4_cfg__usbhs_ehci = {
3819 .master = &omap3xxx_l4_core_hwmod,
3820 .slave = &omap34xx_usbhs_ehci_hwmod,
3821 .clk = "l4_ick",
3822 .addr = omap34xx_usbhs_ehci_addrs,
3823 .addr_cnt = ARRAY_SIZE(omap34xx_usbhs_ehci_addrs),
3824 .user = OCP_USER_MPU | OCP_USER_SDMA,
3825 };
3826
3827 static struct omap_hwmod_ocp_if *omap34xx_usbhs_ehci_slaves[] = {
3828 &omap34xx_l4_cfg__usbhs_ehci,
3829 };
3830
3831 static struct omap_hwmod omap34xx_usbhs_ehci_hwmod = {
3832 .name = "usbhs_ehci",
3833 .class = &omap34xx_usbhs_ehci_hwmod_class,
3834 .mpu_irqs = omap34xx_usbhs_ehci_irqs,
3835 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_usbhs_ehci_irqs),
3836 .slaves = omap34xx_usbhs_ehci_slaves,
3837 .slaves_cnt = ARRAY_SIZE(omap34xx_usbhs_ehci_slaves),
3838 .masters = omap34xx_usbhs_ehci_masters,
3839 .masters_cnt = ARRAY_SIZE(omap34xx_usbhs_ehci_masters),
3840 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
3841 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3842 };
3843
3844 /*
3845 * 'usb_tll_hs' class
3846 * usb_tll_hs module is the adapter on the usb_host_hs ports
3847 */
3848 static struct omap_hwmod_class_sysconfig omap34xx_usb_tll_hs_sysc = {
3849 .rev_offs = 0x0000,
3850 .sysc_offs = 0x0010,
3851 .syss_offs = 0x0014,
3852 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE),
3853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3854 .sysc_fields = &omap_hwmod_sysc_type1,
3855 };
3856
3857 static struct omap_hwmod_class omap34xx_usb_tll_hs_hwmod_class = {
3858 .name = "usbhs_tll",
3859 .sysc = &omap34xx_usb_tll_hs_sysc,
3860 };
3861
3862 static struct omap_hwmod_irq_info omap34xx_usb_tll_hs_irqs[] = {
3863 { .name = "tll-irq", .irq = 78 },
3864 };
3865
3866 static struct omap_hwmod_addr_space omap34xx_usb_tll_hs_addrs[] = {
3867 {
3868 .name = "tll",
3869 .pa_start = 0x48062000,
3870 .pa_end = 0x48062fff,
3871 .flags = ADDR_TYPE_RT
3872 },
3873 };
3874
3875 static struct omap_hwmod_ocp_if omap34xx_f_cfg__usb_tll_hs = {
3876 .clk = "usbtll_fck",
3877 .user = OCP_USER_MPU,
3878 .flags = OCPIF_SWSUP_IDLE,
3879 };
3880
3881 static struct omap_hwmod_ocp_if omap34xx_l4_cfg__usb_tll_hs = {
3882 .master = &omap3xxx_l4_core_hwmod,
3883 .slave = &omap34xx_usb_tll_hs_hwmod,
3884 .clk = "l4_ick",
3885 .addr = omap34xx_usb_tll_hs_addrs,
3886 .addr_cnt = ARRAY_SIZE(omap34xx_usb_tll_hs_addrs),
3887 .user = OCP_USER_MPU | OCP_USER_SDMA,
3888 };
3889
3890 static struct omap_hwmod_ocp_if *omap34xx_usb_tll_hs_slaves[] = {
3891 &omap34xx_l4_cfg__usb_tll_hs,
3892 &omap34xx_f_cfg__usb_tll_hs,
3893 };
3894
3895 static struct omap_hwmod omap34xx_usb_tll_hs_hwmod = {
3896 .name = "usbhs_tll",
3897 .class = &omap34xx_usb_tll_hs_hwmod_class,
3898 .mpu_irqs = omap34xx_usb_tll_hs_irqs,
3899 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_usb_tll_hs_irqs),
3900 .main_clk = "usbtll_ick",
3901 .prcm = {
3902 .omap2 = {
3903 .module_offs = CORE_MOD,
3904 .prcm_reg_id = 3,
3905 .module_bit = 2,
3906 .idlest_reg_id = 3,
3907 .idlest_idle_bit = 2,
3908 },
3909 },
3910 .slaves = omap34xx_usb_tll_hs_slaves,
3911 .slaves_cnt = ARRAY_SIZE(omap34xx_usb_tll_hs_slaves),
3912 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3913 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3914 };
3915
3916 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3917 &omap3xxx_l3_main_hwmod,
3918 &omap3xxx_l4_core_hwmod,
3919 &omap3xxx_l4_per_hwmod,
3920 &omap3xxx_l4_wkup_hwmod,
3921 &omap3xxx_mmc1_hwmod,
3922 &omap3xxx_mmc2_hwmod,
3923 &omap3xxx_mmc3_hwmod,
3924 &omap3xxx_mpu_hwmod,
3925 &omap3xxx_iva_hwmod,
3926
3927 &omap3xxx_timer1_hwmod,
3928 &omap3xxx_timer2_hwmod,
3929 &omap3xxx_timer3_hwmod,
3930 &omap3xxx_timer4_hwmod,
3931 &omap3xxx_timer5_hwmod,
3932 &omap3xxx_timer6_hwmod,
3933 &omap3xxx_timer7_hwmod,
3934 &omap3xxx_timer8_hwmod,
3935 &omap3xxx_timer9_hwmod,
3936 &omap3xxx_timer10_hwmod,
3937 &omap3xxx_timer11_hwmod,
3938 &omap3xxx_timer12_hwmod,
3939
3940 &omap3xxx_wd_timer2_hwmod,
3941 &omap3xxx_uart1_hwmod,
3942 &omap3xxx_uart2_hwmod,
3943 &omap3xxx_uart3_hwmod,
3944 &omap3xxx_uart4_hwmod,
3945 /* dss class */
3946 &omap3430es1_dss_core_hwmod,
3947 &omap3xxx_dss_core_hwmod,
3948 &omap3xxx_dss_dispc_hwmod,
3949 &omap3xxx_dss_dsi1_hwmod,
3950 &omap3xxx_dss_rfbi_hwmod,
3951 &omap3xxx_dss_venc_hwmod,
3952
3953 /* i2c class */
3954 &omap3xxx_i2c1_hwmod,
3955 &omap3xxx_i2c2_hwmod,
3956 &omap3xxx_i2c3_hwmod,
3957 &omap34xx_sr1_hwmod,
3958 &omap34xx_sr2_hwmod,
3959 &omap36xx_sr1_hwmod,
3960 &omap36xx_sr2_hwmod,
3961
3962
3963 /* gpio class */
3964 &omap3xxx_gpio1_hwmod,
3965 &omap3xxx_gpio2_hwmod,
3966 &omap3xxx_gpio3_hwmod,
3967 &omap3xxx_gpio4_hwmod,
3968 &omap3xxx_gpio5_hwmod,
3969 &omap3xxx_gpio6_hwmod,
3970
3971 /* dma_system class*/
3972 &omap3xxx_dma_system_hwmod,
3973
3974 /* mcbsp class */
3975 &omap3xxx_mcbsp1_hwmod,
3976 &omap3xxx_mcbsp2_hwmod,
3977 &omap3xxx_mcbsp3_hwmod,
3978 &omap3xxx_mcbsp4_hwmod,
3979 &omap3xxx_mcbsp5_hwmod,
3980 &omap3xxx_mcbsp2_sidetone_hwmod,
3981 &omap3xxx_mcbsp3_sidetone_hwmod,
3982
3983 /* mailbox class */
3984 &omap3xxx_mailbox_hwmod,
3985
3986 /* mcspi class */
3987 &omap34xx_mcspi1,
3988 &omap34xx_mcspi2,
3989 &omap34xx_mcspi3,
3990 &omap34xx_mcspi4,
3991
3992 /* usbotg class */
3993 &omap3xxx_usbhsotg_hwmod,
3994
3995 /* usbotg for am35x */
3996 &am35xx_usbhsotg_hwmod,
3997
3998 &omap34xx_usb_host_hs_hwmod,
3999 &omap34xx_usbhs_ohci_hwmod,
4000 &omap34xx_usbhs_ehci_hwmod,
4001 &omap34xx_usb_tll_hs_hwmod,
4002
4003 NULL,
4004 };
4005
4006 int __init omap3xxx_hwmod_init(void)
4007 {
4008 return omap_hwmod_register(omap3xxx_hwmods);
4009 }