arch/arm/mach-omap2/omap_l3_noc.h

   1  /*
   2   * OMAP4XXX L3 Interconnect  error handling driver header
   3   *
   4   * Copyright (C) 2011 Texas Corporation
   5   *     Santosh Shilimkar <santosh.shilimkar@ti.com>
   6   *     sricharan <r.sricharan@ti.com>
   7   *
   8   * This program is free software; you can redistribute it and/or modify
   9   * it under the terms of the GNU General Public License as published by
  10   * the Free Software Foundation; either version 2 of the License, or
  11   * (at your option) any later version.
  12   *
  13   * This program is distributed in the hope that it will be useful,
  14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   * GNU General Public License for more details.
  17   *
  18   * You should have received a copy of the GNU General Public License
  19   * along with this program; if not, write to the Free Software
  20   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  21   * USA
  22   */
  23 #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
  24 #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
  25
  26 /*
  27  * L3 register offsets
  28  */
  29 #define L3_MODULES                      3
  30 #define CLEAR_STDERR_LOG                (1 << 31)
  31 #define CUSTOM_ERROR                    0x2
  32 #define STANDARD_ERROR                  0x0
  33 #define INBAND_ERROR                    0x0
  34 #define EMIF_KERRLOG_OFFSET             0x10
  35 #define L3_SLAVE_ADDRESS_OFFSET         0x14
  36 #define LOGICAL_ADDR_ERRORLOG           0x4
  37 #define L3_APPLICATION_ERROR            0x0
  38 #define L3_DEBUG_ERROR                  0x1
  39
  40 #define L3_COREREG                      0x00
  41 #define L3_VERSIONREG                   0x04
  42 #define L3_MAINCTLREG                   0x08
  43 #define L3_NTTPADDR_0                   0x10
  44 #define L3_SVRTSTDLVL                   0x40
  45 #define L3_SVRTCUSTOMLVL                0x44
  46 #define L3_MAIN                         0x48
  47 #define L3_HDR                          0x4C
  48 #define L3_MSTADDR                      0x50
  49 #define L3_SLVADDR                      0x54
  50 #define L3_INFO                         0x58
  51 #define L3_SLVOFSLSB                    0x5C
  52 #define L3_SLVOFSMSB                    0x60
  53 #define L3_CUSTOMINFO_INFO              0x64
  54 #define L3_CUSTOMINFO_MSTADDR           0x68
  55 #define L3_CUSTOMINFO_OPCODE            0x6C
  56 #define L3_ADDRSPACESIZELOG             0x80
  57
  58 u32 l3_flagmux[L3_MODULES] = {
  59         0x50C,
  60         0x100C,
  61         0X020C
  62 };
  63
  64 /*
  65  * L3 Target standard Error register offsets
  66  */
  67 u32 l3_targ_stderrlog_main_clk1[] = {
  68         0x148, /* DMM1 */
  69         0x248, /* DMM2 */
  70         0x348, /* ABE */
  71         0x448, /* L4CFG */
  72         0x648  /* CLK2 PWR DISC */
  73 };
  74
  75 u32 l3_targ_stderrlog_main_clk2[] = {
  76         0x548,          /* CORTEX M3 */
  77         0x348,          /* DSS */
  78         0x148,          /* GPMC */
  79         0x448,          /* ISS */
  80         0x748,          /* IVAHD */
  81         0xD48,          /* missing in TRM  corresponds to AES1*/
  82         0x948,          /* L4 PER0*/
  83         0x248,          /* OCMRAM */
  84         0x148,          /* missing in TRM corresponds to GPMC sERROR*/
  85         0x648,          /* SGX */
  86         0x848,          /* SL2 */
  87         0x1648,         /* C2C */
  88         0x1148,         /* missing in TRM corresponds PWR DISC CLK1*/
  89         0xF48,          /* missing in TRM corrsponds to SHA1*/
  90         0xE48,          /* missing in TRM corresponds to AES2*/
  91         0xC48,          /* L4 PER3 */
  92         0xA48,          /* L4 PER1*/
  93         0xB48           /* L4 PER2*/
  94 };
  95
  96 u32 l3_targ_stderrlog_main_clk3[] = {
  97         0x0148  /* EMUSS */
  98 };
  99
 100 struct l3_masters_data {
 101         u32 id;
 102         char name[15];
 103 };
 104
 105 struct l3_masters_data l3_masters[] = {
 106          { 0x0 , "MPU"},
 107          { 0x10, "CS_ADP"},
 108          { 0x14, "Unknown"},
 109          { 0x20, "DSP"},
 110          { 0x30, "IVAHD"},
 111          { 0x40, "ISS"},
 112          { 0x44, "DucatiM3"},
 113          { 0x48, "FaceDetect"},
 114          { 0x50, "SDMA_Rd"},
 115          { 0x54, "SDMA_Wr"},
 116          { 0x58, "Unknown"},
 117          { 0x5C, "Unknown"},
 118          { 0x60, "SGX"},
 119          { 0x70, "DSS"},
 120          { 0x80, "C2C"},
 121          { 0x88, "Unknown"},
 122          { 0x8C, "Unknown"},
 123          { 0x90, "HSI"},
 124          { 0xA0, "MMC1"},
 125          { 0xA4, "MMC2"},
 126 };
 127
 128 char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
 129         {
 130         "DMM1",
 131         "DMM2",
 132         "ABE",
 133         "L4CFG",
 134         "CLK2 PWR DISC",
 135         },
 136         {
 137         "CORTEX M3" ,
 138         "DSS ",
 139         "GPMC ",
 140         "ISS ",
 141         "IVAHD ",
 142         "AES1",
 143         "L4 PER0",
 144         "OCMRAM ",
 145         "GPMC sERROR",
 146         "SGX ",
 147         "SL2 ",
 148         "C2C ",
 149         "PWR DISC CLK1",
 150         "SHA1",
 151         "AES2",
 152         "L4 PER3",
 153         "L4 PER1",
 154         "L4 PER2",
 155         },
 156         {
 157         "EMUSS",
 158         },
 159 };
 160
 161 u32 targ_reg_offset[L3_MODULES][18] = {
 162         {
 163         0x100,
 164         0x200,
 165         0x300,
 166         0x400,
 167         0x0,
 168         },
 169         {
 170         0x500,
 171         0x300,
 172         0x100,
 173         0x400,
 174         0x700,
 175         0x000,
 176         0x000,
 177         0x000,
 178         0x000,
 179         0x600,
 180         0x800,
 181         0x000,
 182         0x000,
 183         0x000,
 184         0x000,
 185         0x100,
 186         0xA00,
 187         0xB00,
 188         },
 189         {
 190         0x000000
 191         },
 192 };
 193
 194 u32 *l3_targ[L3_MODULES] = {
 195         l3_targ_stderrlog_main_clk1,
 196         l3_targ_stderrlog_main_clk2,
 197         l3_targ_stderrlog_main_clk3,
 198 };
 199
 200 struct omap4_l3 {
 201         struct device   *dev;
 202         struct clk      *ick;
 203
 204         /* memory base */
 205         void __iomem *l3_base[4];
 206
 207         int             debug_irq;
 208         int             app_irq;
 209 };
 210
 211 #endif