ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / mach-omap2 / opp3xxx_data.c
blob41619ea846798e2241ff3e7aa2fbaba468a45df5
1 /*
2 * OMAP3 OPP table definitions.
4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon
6 * Kevin Hilman
7 * Copyright (C) 2010-2011 Nokia Corporation.
8 * Eduardo Valentin
9 * Paul Walmsley
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16 * kind, whether express or implied; without even the implied warranty
17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 #include <linux/module.h>
22 #include <plat/cpu.h>
24 #include "control.h"
25 #include "omap_opp_data.h"
26 #include "pm.h"
28 /* 34xx */
30 /* VDD1 */
32 #define OMAP3430_VDD_MPU_OPP1_UV 975000
33 #define OMAP3430_VDD_MPU_OPP2_UV 1075000
34 #define OMAP3430_VDD_MPU_OPP3_UV 1200000
35 #define OMAP3430_VDD_MPU_OPP4_UV 1270000
36 #define OMAP3430_VDD_MPU_OPP5_UV 1350000
38 struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
39 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, 0, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c, OMAP_ABB_NONE),
40 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, 0, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c, OMAP_ABB_NONE),
41 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, 0, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18, OMAP_ABB_NONE),
42 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, 0, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18, OMAP_ABB_NONE),
43 VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, 0, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18, OMAP_ABB_NONE),
44 VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
47 /* VDD2 */
49 #define OMAP3430_VDD_CORE_OPP1_UV 975000
50 #define OMAP3430_VDD_CORE_OPP2_UV 1050000
51 #define OMAP3430_VDD_CORE_OPP3_UV 1150000
53 struct omap_volt_data omap34xx_vddcore_volt_data[] = {
54 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, 0, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c, OMAP_ABB_NONE),
55 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, 0, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c, OMAP_ABB_NONE),
56 VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, 0, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18, OMAP_ABB_NONE),
57 VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
60 /* OMAP 3430 MPU Core VDD dependency table */
61 static struct omap_vdd_dep_volt omap34xx_vdd_mpu_core_dep_data[] = {
62 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP1_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV},
63 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP2_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP2_UV},
64 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP3_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
65 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP4_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
66 {.main_vdd_volt = OMAP3430_VDD_MPU_OPP5_UV, .dep_vdd_volt = OMAP3430_VDD_CORE_OPP3_UV},
69 struct omap_vdd_dep_info omap34xx_vddmpu_dep_info[] = {
71 .name = "core",
72 .dep_table = omap34xx_vdd_mpu_core_dep_data,
73 .nr_dep_entries = ARRAY_SIZE(omap34xx_vdd_mpu_core_dep_data),
75 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
78 /* 36xx */
80 /* VDD1 */
82 #define OMAP3630_VDD_MPU_OPP50_UV 1012500
83 #define OMAP3630_VDD_MPU_OPP100_UV 1200000
84 #define OMAP3630_VDD_MPU_OPP120_UV 1325000
85 #define OMAP3630_VDD_MPU_OPP1G_UV 1375000
87 struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
88 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, 0, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
89 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, 0, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
90 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, 0, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
91 VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, 0, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
92 VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
95 /* VDD2 */
97 #define OMAP3630_VDD_CORE_OPP50_UV 1000000
98 #define OMAP3630_VDD_CORE_OPP100_UV 1200000
100 struct omap_volt_data omap36xx_vddcore_volt_data[] = {
101 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, 0, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c, OMAP_ABB_NONE),
102 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, 0, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16, OMAP_ABB_NONE),
103 VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
106 /* OPP data */
108 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
109 /* MPU OPP1 */
110 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
111 /* MPU OPP2 */
112 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
113 /* MPU OPP3 */
114 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
115 /* MPU OPP4 */
116 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
117 /* MPU OPP5 */
118 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
121 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
122 * almost the same than the one at 83MHz thus providing very little
123 * gain for the power point of view. In term of energy it will even
124 * increase the consumption due to the very negative performance
125 * impact that frequency will do to the MPU and the whole system in
126 * general.
128 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
129 /* L3 OPP2 */
130 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
131 /* L3 OPP3 */
132 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
134 /* DSP OPP1 */
135 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
136 /* DSP OPP2 */
137 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
138 /* DSP OPP3 */
139 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
140 /* DSP OPP4 */
141 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
142 /* DSP OPP5 */
143 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
146 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
147 /* MPU OPP1 - OPP50 */
148 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV),
149 /* MPU OPP2 - OPP100 */
150 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV),
151 /* MPU OPP3 - OPP-Turbo */
152 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
153 /* MPU OPP4 - OPP-SB */
154 OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
156 /* L3 OPP1 - OPP50 */
157 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
158 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
159 OPP_INITIALIZER("l3_main", "dpll3_ck", "core", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
161 /* DSP OPP1 - OPP50 */
162 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV),
163 /* DSP OPP2 - OPP100 */
164 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV),
165 /* DSP OPP3 - OPP-Turbo */
166 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
167 /* DSP OPP4 - OPP-SB */
168 OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
171 /* OMAP 3630 MPU Core VDD dependency table */
172 static struct omap_vdd_dep_volt omap36xx_vdd_mpu_core_dep_data[] = {
173 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP50_UV},
174 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
175 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP120_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
176 {.main_vdd_volt = OMAP3630_VDD_MPU_OPP1G_UV, .dep_vdd_volt = OMAP3630_VDD_CORE_OPP100_UV},
179 struct omap_vdd_dep_info omap36xx_vddmpu_dep_info[] = {
181 .name = "core",
182 .dep_table = omap36xx_vdd_mpu_core_dep_data,
183 .nr_dep_entries = ARRAY_SIZE(omap36xx_vdd_mpu_core_dep_data),
185 {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
189 * omap3_opp_init() - initialize omap3 opp table
191 int __init omap3_opp_init(void)
193 int r = -ENODEV;
195 if (!cpu_is_omap34xx())
196 return r;
198 if (cpu_is_omap3630())
199 r = omap_init_opp_table(omap36xx_opp_def_list,
200 ARRAY_SIZE(omap36xx_opp_def_list));
201 else
202 r = omap_init_opp_table(omap34xx_opp_def_list,
203 ARRAY_SIZE(omap34xx_opp_def_list));
205 return r;
207 device_initcall(omap3_opp_init);