arch/arm/mach-omap2/opp4xxx_data.c

   1 /*
   2  * OMAP4 OPP table definitions.
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Nishanth Menon
   6  *      Kevin Hilman
   7  *      Thara Gopinath
   8  * Copyright (C) 2010-2011 Nokia Corporation.
   9  *      Eduardo Valentin
  10  *      Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  17  * kind, whether express or implied; without even the implied warranty
  18  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21 #include <linux/module.h>
  22 #include <linux/opp.h>
  23
  24 #include <plat/cpu.h>
  25 #include <plat/common.h>
  26
  27 #include "control.h"
  28 #include "omap_opp_data.h"
  29 #include "pm.h"
  30
  31 /*
  32  * Structures containing OMAP4430 voltage supported and various
  33  * voltage dependent data for each VDD.
  34  */
  35
  36 #define OMAP4430_VDD_MPU_OPP50_UV               1025000
  37 #define OMAP4430_VDD_MPU_OPP100_UV              1200000
  38 #define OMAP4430_VDD_MPU_OPPTURBO_UV            1325000
  39 #define OMAP4430_VDD_MPU_OPPNITRO_UV            1388000
  40
  41 struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
  42         VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
  43         VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
  44         VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
  45         VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
  46         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
  47 };
  48
  49 #define OMAP4430_VDD_IVA_OPP50_UV                950000
  50 #define OMAP4430_VDD_IVA_OPP100_UV              1114000
  51 #define OMAP4430_VDD_IVA_OPPTURBO_UV            1291000
  52
  53 struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
  54         VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
  55         VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
  56         VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
  57         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
  58 };
  59
  60 #define OMAP4430_VDD_CORE_OPP50_UV               962000
  61 #define OMAP4430_VDD_CORE_OPP100_UV             1127000
  62
  63 struct omap_volt_data omap443x_vdd_core_volt_data[] = {
  64         VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, 0, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c, OMAP_ABB_NONE),
  65         VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, 0, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16, OMAP_ABB_NONE),
  66         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
  67 };
  68
  69 /* Dependency of domains are as follows for OMAP4430 (OPP based):
  70  *
  71  *      MPU     IVA     CORE
  72  *      50      50      50+
  73  *      50      100+    100
  74  *      100+    50      100
  75  *      100+    100+    100
  76  */
  77
  78 /* OMAP 4430 MPU Core VDD dependency table */
  79 static struct omap_vdd_dep_volt omap443x_vdd_mpu_core_dep_data[] = {
  80         {.main_vdd_volt = OMAP4430_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP50_UV},
  81         {.main_vdd_volt = OMAP4430_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV},
  82         {.main_vdd_volt = OMAP4430_VDD_MPU_OPPTURBO_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV},
  83         {.main_vdd_volt = OMAP4430_VDD_MPU_OPPNITRO_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV},
  84 };
  85
  86 struct omap_vdd_dep_info omap443x_vddmpu_dep_info[] = {
  87         {
  88                 .name   = "core",
  89                 .dep_table = omap443x_vdd_mpu_core_dep_data,
  90                 .nr_dep_entries = ARRAY_SIZE(omap443x_vdd_mpu_core_dep_data),
  91         },
  92         {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
  93 };
  94
  95 /* OMAP 4430 MPU IVA VDD dependency table */
  96 static struct omap_vdd_dep_volt omap443x_vdd_iva_core_dep_data[] = {
  97         {.main_vdd_volt = OMAP4430_VDD_IVA_OPP50_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP50_UV},
  98         {.main_vdd_volt = OMAP4430_VDD_IVA_OPP100_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV},
  99         {.main_vdd_volt = OMAP4430_VDD_IVA_OPPTURBO_UV, .dep_vdd_volt = OMAP4430_VDD_CORE_OPP100_UV},
 100 };
 101
 102 struct omap_vdd_dep_info omap443x_vddiva_dep_info[] = {
 103         {
 104                 .name   = "core",
 105                 .dep_table = omap443x_vdd_iva_core_dep_data,
 106                 .nr_dep_entries = ARRAY_SIZE(omap443x_vdd_iva_core_dep_data),
 107         },
 108         {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
 109 };
 110
 111 static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
 112         /* MPU OPP1 - OPP50 */
 113         OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
 114         /* MPU OPP2 - OPP100 */
 115         OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
 116         /* MPU OPP3 - OPP-Turbo */
 117         OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
 118         /* MPU OPP4 - OPP-SB */
 119         OPP_INITIALIZER("mpu", "dpll_mpu_ck", "mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
 120         /* L3 OPP1 - OPP50 */
 121         OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
 122         /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
 123         OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
 124         /* IVA OPP1 - OPP50 */
 125         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
 126         /* IVA OPP2 - OPP100 */
 127         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
 128         /* IVA OPP3 - OPP-Turbo */
 129         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
 130         /* SGX OPP1 - OPP50 */
 131         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 153600000, OMAP4430_VDD_CORE_OPP50_UV),
 132         /* SGX OPP2 - OPP100 */
 133         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 307200000, OMAP4430_VDD_CORE_OPP100_UV),
 134         /* FDIF OPP1 - OPP25 */
 135         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 32000000, OMAP4430_VDD_CORE_OPP50_UV),
 136         /* FDIF OPP2 - OPP50 */
 137         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 64000000, OMAP4430_VDD_CORE_OPP50_UV),
 138         /* FDIF OPP3 - OPP100 */
 139         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4430_VDD_CORE_OPP100_UV),
 140         /* DSP OPP1 - OPP50 */
 141         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4430_VDD_IVA_OPP50_UV),
 142         /* DSP OPP2 - OPP100 */
 143         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4430_VDD_IVA_OPP100_UV),
 144         /* DSP OPP3 - OPPTB */
 145         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
 146         /* HSI OPP1 - OPP50 */
 147         OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4430_VDD_CORE_OPP50_UV),
 148         /* HSI OPP2 - OPP100 */
 149         OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4430_VDD_CORE_OPP100_UV),
 150         /* ABE OPP1 - OPP50 */
 151         OPP_INITIALIZER("aess", "abe_clk", "iva", true, 98304000, OMAP4430_VDD_IVA_OPP50_UV),
 152         /* ABE OPP2 - OPP100 */
 153         OPP_INITIALIZER("aess", "abe_clk", "iva", true, 196608000, OMAP4430_VDD_IVA_OPP100_UV),
 154 };
 155
 156 #define OMAP4460_VDD_MPU_OPP25_UV                900000
 157 #define OMAP4460_VDD_MPU_OPP50_UV                975000
 158 #define OMAP4460_VDD_MPU_OPP75_UV               1055000
 159 #define OMAP4460_VDD_MPU_OPP100_UV              1153000
 160 #define OMAP4460_VDD_MPU_OPPTURBO_UV            1267000
 161 #define OMAP4460_VDD_MPU_OPPNITRO_UV            1330000
 162 #define OMAP4460_VDD_MPU_OPPOVERCLOCK_UV        1340000
 163 #define OMAP4460_VDD_MPU_OPPOVERCLOCK2_UV       1350000
 164
 165 struct omap_volt_data omap446x_vdd_mpu_volt_data[] = {
 166         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP25_UV, 10000, OMAP44XX_CONTROL_FUSE_MPU_OPP25, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
 167         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, 10000, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
 168         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP75_UV, 10000, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
 169         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
 170         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
 171         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
 172         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPOVERCLOCK_UV, 0, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27, OMAP_ABB_FAST_OPP),
 173         VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPOVERCLOCK2_UV, 40000, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x30, OMAP_ABB_FAST_OPP),
 174         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
 175 };
 176
 177 #define OMAP4460_VDD_IVA_OPP50_UV                900000
 178 #define OMAP4460_VDD_IVA_OPP100_UV              1090000
 179 #define OMAP4460_VDD_IVA_OPPTURBO_UV            1241000
 180 #define OMAP4460_VDD_IVA_OPPNITRO_UV            1325000
 181
 182 struct omap_volt_data omap446x_vdd_iva_volt_data[] = {
 183         VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP50_UV, 13000, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c, OMAP_ABB_NOMINAL_OPP),
 184         VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16, OMAP_ABB_NOMINAL_OPP),
 185         VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPTURBO_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23, OMAP_ABB_NOMINAL_OPP),
 186         VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPNITRO_UV, 0, OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO, 0xfa, 0x23, OMAP_ABB_FAST_OPP),
 187         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
 188 };
 189
 190 #define OMAP4460_VDD_CORE_OPP25_UV              875000
 191 #define OMAP4460_VDD_CORE_OPP50_UV              912000
 192 #define OMAP4460_VDD_CORE_OPP75_UV              962000
 193 #define OMAP4460_VDD_CORE_OPP100_UV             1077000
 194 #define OMAP4460_VDD_CORE_OPP100_OV_UV          1250000
 195
 196 struct omap_volt_data omap446x_vdd_core_volt_data[] = {
 197         VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP25_UV, 38000, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c, OMAP_ABB_NONE),
 198         VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP50_UV, 38000, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c, OMAP_ABB_NONE),
 199         VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP75_UV, 13000, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16, OMAP_ABB_NONE),
 200         VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, 13000, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16, OMAP_ABB_NONE),
 201         VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, 13000, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16, OMAP_ABB_NONE),
 202         VOLT_DATA_DEFINE(0, 0, 0, 0, 0, 0),
 203 };
 204
 205 /* OMAP 4460 MPU Core VDD dependency table */
 206 static struct omap_vdd_dep_volt omap446x_vdd_mpu_core_dep_data[] = {
 207         {.main_vdd_volt = OMAP4460_VDD_MPU_OPP25_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP25_UV},
 208         {.main_vdd_volt = OMAP4460_VDD_MPU_OPP50_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP50_UV},
 209         {.main_vdd_volt = OMAP4460_VDD_MPU_OPP75_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP75_UV},
 210         {.main_vdd_volt = OMAP4460_VDD_MPU_OPP100_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 211         {.main_vdd_volt = OMAP4460_VDD_MPU_OPPTURBO_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 212         {.main_vdd_volt = OMAP4460_VDD_MPU_OPPNITRO_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 213         {.main_vdd_volt = OMAP4460_VDD_MPU_OPPOVERCLOCK_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 214         {.main_vdd_volt = OMAP4460_VDD_MPU_OPPOVERCLOCK2_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_OV_UV},
 215 };
 216
 217 struct omap_vdd_dep_info omap446x_vddmpu_dep_info[] = {
 218         {
 219                 .name   = "core",
 220                 .dep_table = omap446x_vdd_mpu_core_dep_data,
 221                 .nr_dep_entries = ARRAY_SIZE(omap446x_vdd_mpu_core_dep_data),
 222         },
 223         {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
 224 };
 225
 226 /* OMAP 4460 MPU IVA VDD dependency table */
 227 static struct omap_vdd_dep_volt omap446x_vdd_iva_core_dep_data[] = {
 228         {.main_vdd_volt = OMAP4460_VDD_IVA_OPP50_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP50_UV},
 229         {.main_vdd_volt = OMAP4460_VDD_IVA_OPP100_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 230         {.main_vdd_volt = OMAP4460_VDD_IVA_OPPTURBO_UV, .dep_vdd_volt = OMAP4460_VDD_CORE_OPP100_UV},
 231 };
 232
 233 struct omap_vdd_dep_info omap446x_vddiva_dep_info[] = {
 234         {
 235                 .name   = "core",
 236                 .dep_table = omap446x_vdd_iva_core_dep_data,
 237                 .nr_dep_entries = ARRAY_SIZE(omap446x_vdd_iva_core_dep_data),
 238         },
 239         {.name = NULL, .dep_table = NULL, .nr_dep_entries = 0},
 240 };
 241
 242 static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
 243         /* MPU OPP1 - OPP25 */
 244         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 200000000, OMAP4460_VDD_MPU_OPP25_UV),
 245         /* MPU OPP1 - OPP50 */
 246         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
 247         /* MPU OPP1 - OPP75 */
 248         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 528000000, OMAP4460_VDD_MPU_OPP75_UV),
 249         /* MPU OPP2 - OPP100 */
 250         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
 251         /* MPU OPP3 - OPP-Turbo */
 252         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
 253         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", true, 1072000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
 254         /* MPU OPP4 - OPP-Nitro */
 255         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
 256         /* MPU OPP4 - OPP-Overclock */
 257         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", false, 1350000000, OMAP4460_VDD_MPU_OPPOVERCLOCK_UV),
 258         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", false, 1420000000, OMAP4460_VDD_MPU_OPPOVERCLOCK_UV),
 259         OPP_INITIALIZER("mpu", "virt_dpll_mpu_ck", "mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPOVERCLOCK2_UV),
 260         /* L3 OPP1 - OPP50 */
 261         OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV),
 262         /* L3 OPP2 - OPP100 */
 263         OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
 264         OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4460_VDD_CORE_OPP100_OV_UV),
 265         /* IVA OPP1 - OPP50 */
 266         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
 267         /* IVA OPP2 - OPP100 */
 268         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
 269         /*
 270          * IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
 271          * recommends Phoenix VCORE2 which can supply only 600mA - so the ones
 272          * above this OPP frequency, even though OMAP is capable, should be
 273          * enabled by board file which is sure of the chip power capability
 274          */
 275         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
 276         /* IVA OPP4 - OPP-Nitro */
 277         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
 278         /* IVA OPP5 - OPP-Nitro SpeedBin*/
 279         OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
 280
 281         /* SGX OPP1 - OPP50 */
 282         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 153600000, OMAP4460_VDD_CORE_OPP50_UV),
 283         /* SGX OPP2 - OPP100 */
 284         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", false, 307200000, OMAP4460_VDD_CORE_OPP100_UV),
 285         /* SGX OPP3 - OPPOV */
 286         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 384000000, OMAP4460_VDD_CORE_OPP100_UV),
 287         OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", false, 512000000, OMAP4460_VDD_CORE_OPP100_OV_UV),
 288         /* FDIF OPP1 - OPP25 */
 289         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 32000000, OMAP4460_VDD_CORE_OPP50_UV),
 290         /* FDIF OPP2 - OPP50 */
 291         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 64000000, OMAP4460_VDD_CORE_OPP50_UV),
 292         /* FDIF OPP3 - OPP100 */
 293         OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4460_VDD_CORE_OPP100_UV),
 294         /* DSP OPP1 - OPP50 */
 295         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4460_VDD_IVA_OPP50_UV),
 296         /* DSP OPP2 - OPP100 */
 297         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4460_VDD_IVA_OPP100_UV),
 298         /* DSP OPP3 - OPPTB */
 299         OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
 300         /* HSI OPP1 - OPP50 */
 301         OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4460_VDD_CORE_OPP50_UV),
 302         /* HSI OPP2 - OPP100 */
 303         OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4460_VDD_CORE_OPP100_UV),
 304         /* ABE OPP1 - OPP50 */
 305         OPP_INITIALIZER("aess", "abe_clk", "iva", true, 98304000, OMAP4460_VDD_IVA_OPP50_UV),
 306         /* ABE OPP2 - OPP100 */
 307         OPP_INITIALIZER("aess", "abe_clk", "iva", true, 196608000, OMAP4460_VDD_IVA_OPP100_UV),
 308 };
 309
 310 /**
 311  * omap4_mpu_opp_enable() - helper to enable the OPP
 312  * @freq:       frequency to enable
 313  */
 314 static void __init omap4_mpu_opp_enable(unsigned long freq)
 315 {
 316         struct device *mpu_dev;
 317         int r;
 318
 319         mpu_dev = omap2_get_mpuss_device();
 320         if (!mpu_dev) {
 321                 pr_err("%s: no mpu_dev, did not enable f=%ld\n", __func__,
 322                         freq);
 323                 return;
 324         }
 325
 326         r = opp_enable(mpu_dev, freq);
 327         if (r < 0)
 328                 dev_err(mpu_dev, "%s: opp_enable failed(%d) f=%ld\n", __func__,
 329                         r, freq);
 330 }
 331
 332 /**
 333  * omap4_opp_init() - initialize omap4 opp table
 334  */
 335 int __init omap4_opp_init(void)
 336 {
 337         int r = -ENODEV;
 338
 339         if (!cpu_is_omap44xx())
 340                 return r;
 341         if (cpu_is_omap443x())
 342                 r = omap_init_opp_table(omap443x_opp_def_list,
 343                         ARRAY_SIZE(omap443x_opp_def_list));
 344         else if (cpu_is_omap446x())
 345                 r = omap_init_opp_table(omap446x_opp_def_list,
 346                         ARRAY_SIZE(omap446x_opp_def_list));
 347
 348         if (!r) {
 349                 if (omap4_has_mpu_1_2ghz())
 350                         omap4_mpu_opp_enable(1200000000);
 351                 /* The tuna supports 1.35GHz & 1.42GHz */
 352                 if (omap4_has_mpu_1_5ghz())
 353                         omap4_mpu_opp_enable(1350000000);
 354                         omap4_mpu_opp_enable(1420000000);
 355                         omap4_mpu_opp_enable(1500000000);
 356         }
 357
 358         return r;
 359 }
 360 device_initcall(omap4_opp_init);