arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33 #include <linux/console.h>
  34
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <mach/irqs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sram.h>
  42 #include <plat/dma.h>
  43 #include <plat/board.h>
  44
  45 #include "prm2xxx_3xxx.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52
  53 #include "powerdomain.h"
  54 #include "clockdomain.h"
  55
  56 #ifdef CONFIG_SUSPEND
  57 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  58 static inline bool is_suspending(void)
  59 {
  60         return (suspend_state != PM_SUSPEND_ON);
  61 }
  62 #else
  63 static inline bool is_suspending(void)
  64 {
  65         return false;
  66 }
  67 #endif
  68
  69 static void (*omap2_sram_idle)(void);
  70 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  71                                   void __iomem *sdrc_power);
  72
  73 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  74 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  75
  76 static struct clk *osc_ck, *emul_ck;
  77
  78 static int omap2_fclks_active(void)
  79 {
  80         u32 f1, f2;
  81
  82         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  83         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  84
  85         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  86         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  87         f2 &= ~OMAP24XX_EN_UART3_MASK;
  88
  89         if (f1 | f2)
  90                 return 1;
  91         return 0;
  92 }
  93
  94 static void omap2_enter_full_retention(void)
  95 {
  96         u32 l;
  97         struct timespec ts_preidle, ts_postidle, ts_idle;
  98
  99         /* There is 1 reference hold for all children of the oscillator
 100          * clock, the following will remove it. If no one else uses the
 101          * oscillator itself it will be disabled if/when we enter retention
 102          * mode.
 103          */
 104         clk_disable(osc_ck);
 105
 106         /* Clear old wake-up events */
 107         /* REVISIT: These write to reserved bits? */
 108         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 109         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 110         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 111
 112         /*
 113          * Set MPU powerdomain's next power state to RETENTION;
 114          * preserve logic state during retention
 115          */
 116         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 117         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 118
 119         /* Workaround to kill USB */
 120         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 121         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 122
 123         omap2_gpio_prepare_for_idle(0);
 124
 125         if (omap2_pm_debug) {
 126                 omap2_pm_dump(0, 0, 0);
 127                 getnstimeofday(&ts_preidle);
 128         }
 129
 130         /* One last check for pending IRQs to avoid extra latency due
 131          * to sleeping unnecessarily. */
 132         if (omap_irq_pending())
 133                 goto no_sleep;
 134
 135         /* Jump to SRAM suspend code */
 136         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 137                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 138                            OMAP_SDRC_REGADDR(SDRC_POWER));
 139
 140         omap_uart_resume_idle();
 141
 142 no_sleep:
 143         if (omap2_pm_debug) {
 144                 unsigned long long tmp;
 145
 146                 getnstimeofday(&ts_postidle);
 147                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 148                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 149                 omap2_pm_dump(0, 1, tmp);
 150         }
 151         omap2_gpio_resume_after_idle(0);
 152
 153         clk_enable(osc_ck);
 154
 155         /* clear CORE wake-up events */
 156         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 157         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 158
 159         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 160         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 161
 162         /* MPU domain wake events */
 163         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 164         if (l & 0x01)
 165                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 166                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 167         if (l & 0x20)
 168                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 169                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 170
 171         /* Mask future PRCM-to-MPU interrupts */
 172         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 173 }
 174
 175 static int omap2_i2c_active(void)
 176 {
 177         u32 l;
 178
 179         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 180         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 181 }
 182
 183 static int sti_console_enabled;
 184
 185 static int omap2_allow_mpu_retention(void)
 186 {
 187         u32 l;
 188
 189         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 190         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 191         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 192                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 193                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 194                 return 0;
 195         /* Check for UART3. */
 196         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 197         if (l & OMAP24XX_EN_UART3_MASK)
 198                 return 0;
 199         if (sti_console_enabled)
 200                 return 0;
 201
 202         return 1;
 203 }
 204
 205 static void omap2_enter_mpu_retention(void)
 206 {
 207         int only_idle = 0;
 208         struct timespec ts_preidle, ts_postidle, ts_idle;
 209
 210         /* Putting MPU into the WFI state while a transfer is active
 211          * seems to cause the I2C block to timeout. Why? Good question. */
 212         if (omap2_i2c_active())
 213                 return;
 214
 215         /* The peripherals seem not to be able to wake up the MPU when
 216          * it is in retention mode. */
 217         if (omap2_allow_mpu_retention()) {
 218                 /* REVISIT: These write to reserved bits? */
 219                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 220                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 221                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 222
 223                 /* Try to enter MPU retention */
 224                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 225                                   OMAP_LOGICRETSTATE_MASK,
 226                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 227         } else {
 228                 /* Block MPU retention */
 229
 230                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 231                                                  OMAP2_PM_PWSTCTRL);
 232                 only_idle = 1;
 233         }
 234
 235         if (omap2_pm_debug) {
 236                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 237                 getnstimeofday(&ts_preidle);
 238         }
 239
 240         omap2_sram_idle();
 241
 242         if (omap2_pm_debug) {
 243                 unsigned long long tmp;
 244
 245                 getnstimeofday(&ts_postidle);
 246                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 247                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 248                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
 249         }
 250 }
 251
 252 static int omap2_can_sleep(void)
 253 {
 254         if (omap2_fclks_active())
 255                 return 0;
 256         if (osc_ck->usecount > 1)
 257                 return 0;
 258         if (omap_dma_running())
 259                 return 0;
 260
 261         return 1;
 262 }
 263
 264 static void omap2_pm_idle(void)
 265 {
 266         local_irq_disable();
 267         local_fiq_disable();
 268
 269         if (!omap2_can_sleep()) {
 270                 if (omap_irq_pending())
 271                         goto out;
 272                 omap2_enter_mpu_retention();
 273                 goto out;
 274         }
 275
 276         if (omap_irq_pending())
 277                 goto out;
 278
 279         omap2_enter_full_retention();
 280
 281 out:
 282         local_fiq_enable();
 283         local_irq_enable();
 284 }
 285
 286 #ifdef CONFIG_SUSPEND
 287 static int omap2_pm_begin(suspend_state_t state)
 288 {
 289         disable_hlt();
 290         suspend_state = state;
 291         return 0;
 292 }
 293
 294 static int omap2_pm_suspend(void)
 295 {
 296         u32 wken_wkup, mir1;
 297
 298         wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 299         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 300         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 301
 302         /* Mask GPT1 */
 303         mir1 = omap_readl(0x480fe0a4);
 304         omap_writel(1 << 5, 0x480fe0ac);
 305
 306         omap2_enter_full_retention();
 307
 308         omap_writel(mir1, 0x480fe0a4);
 309         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 310
 311         return 0;
 312 }
 313
 314 static int omap2_pm_enter(suspend_state_t state)
 315 {
 316         int ret = 0;
 317
 318         switch (state) {
 319         case PM_SUSPEND_STANDBY:
 320         case PM_SUSPEND_MEM:
 321                 ret = omap2_pm_suspend();
 322                 break;
 323         default:
 324                 ret = -EINVAL;
 325         }
 326
 327         return ret;
 328 }
 329
 330 static void omap2_pm_end(void)
 331 {
 332         suspend_state = PM_SUSPEND_ON;
 333         enable_hlt();
 334 }
 335
 336 static const struct platform_suspend_ops omap_pm_ops = {
 337         .begin          = omap2_pm_begin,
 338         .enter          = omap2_pm_enter,
 339         .end            = omap2_pm_end,
 340         .valid          = suspend_valid_only_mem,
 341 };
 342 #else
 343 static const struct platform_suspend_ops __initdata omap_pm_ops;
 344 #endif /* CONFIG_SUSPEND */
 345
 346 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 347 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 348 {
 349         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 350                 clkdm_allow_idle(clkdm);
 351         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 352                  atomic_read(&clkdm->usecount) == 0)
 353                 clkdm_sleep(clkdm);
 354         return 0;
 355 }
 356
 357 static void __init prcm_setup_regs(void)
 358 {
 359         int i, num_mem_banks;
 360         struct powerdomain *pwrdm;
 361
 362         /*
 363          * Enable autoidle
 364          * XXX This should be handled by hwmod code or PRCM init code
 365          */
 366         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 367                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 368
 369         /*
 370          * Set CORE powerdomain memory banks to retain their contents
 371          * during RETENTION
 372          */
 373         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 374         for (i = 0; i < num_mem_banks; i++)
 375                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 376
 377         /* Set CORE powerdomain's next power state to RETENTION */
 378         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 379
 380         /*
 381          * Set MPU powerdomain's next power state to RETENTION;
 382          * preserve logic state during retention
 383          */
 384         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 385         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 386
 387         /* Force-power down DSP, GFX powerdomains */
 388
 389         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 390         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 391         clkdm_sleep(dsp_clkdm);
 392
 393         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 394         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 395         clkdm_sleep(gfx_clkdm);
 396
 397         /* Enable hardware-supervised idle for all clkdms */
 398         clkdm_for_each(clkdms_setup, NULL);
 399         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 400
 401         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 402          * stabilisation */
 403         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 404                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 405
 406         /* Configure automatic voltage transition */
 407         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 408                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 409         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 410                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 411                                 OMAP24XX_MEMRETCTRL_MASK |
 412                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 413                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 414                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 415
 416         /* Enable wake-up events */
 417         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 418                                 WKUP_MOD, PM_WKEN);
 419 }
 420
 421 static int __init omap2_pm_init(void)
 422 {
 423         u32 l;
 424
 425         if (!cpu_is_omap24xx())
 426                 return -ENODEV;
 427
 428         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 429         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 430         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 431
 432         /* Look up important powerdomains */
 433
 434         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 435         if (!mpu_pwrdm)
 436                 pr_err("PM: mpu_pwrdm not found\n");
 437
 438         core_pwrdm = pwrdm_lookup("core_pwrdm");
 439         if (!core_pwrdm)
 440                 pr_err("PM: core_pwrdm not found\n");
 441
 442         /* Look up important clockdomains */
 443
 444         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 445         if (!mpu_clkdm)
 446                 pr_err("PM: mpu_clkdm not found\n");
 447
 448         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 449         if (!wkup_clkdm)
 450                 pr_err("PM: wkup_clkdm not found\n");
 451
 452         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 453         if (!dsp_clkdm)
 454                 pr_err("PM: dsp_clkdm not found\n");
 455
 456         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 457         if (!gfx_clkdm)
 458                 pr_err("PM: gfx_clkdm not found\n");
 459
 460
 461         osc_ck = clk_get(NULL, "osc_ck");
 462         if (IS_ERR(osc_ck)) {
 463                 printk(KERN_ERR "could not get osc_ck\n");
 464                 return -ENODEV;
 465         }
 466
 467         if (cpu_is_omap242x()) {
 468                 emul_ck = clk_get(NULL, "emul_ck");
 469                 if (IS_ERR(emul_ck)) {
 470                         printk(KERN_ERR "could not get emul_ck\n");
 471                         clk_put(osc_ck);
 472                         return -ENODEV;
 473                 }
 474         }
 475
 476         prcm_setup_regs();
 477
 478         /* Hack to prevent MPU retention when STI console is enabled. */
 479         {
 480                 const struct omap_sti_console_config *sti;
 481
 482                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 483                                       struct omap_sti_console_config);
 484                 if (sti != NULL && sti->enable)
 485                         sti_console_enabled = 1;
 486         }
 487
 488         /*
 489          * We copy the assembler sleep/wakeup routines to SRAM.
 490          * These routines need to be in SRAM as that's the only
 491          * memory the MPU can see when it wakes up.
 492          */
 493         if (cpu_is_omap24xx()) {
 494                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 495                                                  omap24xx_idle_loop_suspend_sz);
 496
 497                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 498                                                     omap24xx_cpu_suspend_sz);
 499         }
 500
 501         suspend_set_ops(&omap_pm_ops);
 502         pm_idle = omap2_pm_idle;
 503
 504         omap_pm_is_ready_status = true;
 505
 506         return 0;
 507 }
 508
 509 late_initcall(omap2_pm_init);