arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/common.h>
  21 #include <plat/cpu.h>
  22 #include <plat/prcm.h>
  23
  24 #include "voltage.h"
  25 #include "vp.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28 #include "prcm44xx.h"
  29 #include "prminst44xx.h"
  30
  31 /*
  32  * Address offset (in bytes) between the reset control and the reset
  33  * status registers: 4 bytes on OMAP4
  34  */
  35 #define OMAP4_RST_CTRL_ST_OFFSET                4
  36
  37 /* PRM low-level functions */
  38
  39 /* Read a register in a CM/PRM instance in the PRM module */
  40 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  41 {
  42         return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
  43 }
  44
  45 /* Write into a register in a CM/PRM instance in the PRM module */
  46 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  47 {
  48         __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
  49 }
  50
  51 /* Read-modify-write a register in a PRM module. Caller must lock */
  52 u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
  53 {
  54         u32 v;
  55
  56         v = omap4_prm_read_inst_reg(inst, reg);
  57         v &= ~mask;
  58         v |= bits;
  59         omap4_prm_write_inst_reg(v, inst, reg);
  60
  61         return v;
  62 }
  63
  64 /* Read a PRM register, AND it, and shift the result down to bit 0 */
  65 /* XXX deprecated */
  66 u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
  67 {
  68         u32 v;
  69
  70         v = __raw_readl(reg);
  71         v &= mask;
  72         v >>= __ffs(mask);
  73
  74         return v;
  75 }
  76
  77 /* Read-modify-write a register in a PRM module. Caller must lock */
  78 /* XXX deprecated */
  79 u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
  80 {
  81         u32 v;
  82
  83         v = __raw_readl(reg);
  84         v &= ~mask;
  85         v |= bits;
  86         __raw_writel(v, reg);
  87
  88         return v;
  89 }
  90
  91 u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
  92 {
  93         return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
  94 }
  95
  96 u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
  97 {
  98         return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
  99 }
 100
 101 /**
 102  * omap4_prm_is_hardreset_asserted - read the HW reset line state of
 103  * submodules contained in the hwmod module
 104  * @rstctrl_reg: RM_RSTCTRL register address for this module
 105  * @shift: register bit shift corresponding to the reset line to check
 106  *
 107  * Returns 1 if the (sub)module hardreset line is currently asserted,
 108  * 0 if the (sub)module hardreset line is not currently asserted, or
 109  * -EINVAL upon parameter error.
 110  */
 111 int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
 112 {
 113         if (!cpu_is_omap44xx() || !rstctrl_reg)
 114                 return -EINVAL;
 115
 116         return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
 117 }
 118
 119 /**
 120  * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
 121  * @rstctrl_reg: RM_RSTCTRL register address for this module
 122  * @shift: register bit shift corresponding to the reset line to assert
 123  *
 124  * Some IPs like dsp, ipu or iva contain processors that require an HW
 125  * reset line to be asserted / deasserted in order to fully enable the
 126  * IP.  These modules may have multiple hard-reset lines that reset
 127  * different 'submodules' inside the IP block.  This function will
 128  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 129  * upon an argument error.
 130  */
 131 int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
 132 {
 133         u32 mask;
 134
 135         if (!cpu_is_omap44xx() || !rstctrl_reg)
 136                 return -EINVAL;
 137
 138         mask = 1 << shift;
 139         omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
 140
 141         return 0;
 142 }
 143
 144 /**
 145  * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
 146  * @rstctrl_reg: RM_RSTCTRL register address for this module
 147  * @shift: register bit shift corresponding to the reset line to deassert
 148  *
 149  * Some IPs like dsp, ipu or iva contain processors that require an HW
 150  * reset line to be asserted / deasserted in order to fully enable the
 151  * IP.  These modules may have multiple hard-reset lines that reset
 152  * different 'submodules' inside the IP block.  This function will
 153  * take the submodule out of reset and wait until the PRCM indicates
 154  * that the reset has completed before returning.  Returns 0 upon success or
 155  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 156  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 157  */
 158 int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
 159 {
 160         u32 mask;
 161         void __iomem *rstst_reg;
 162         int c;
 163
 164         if (!cpu_is_omap44xx() || !rstctrl_reg)
 165                 return -EINVAL;
 166
 167         rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
 168
 169         mask = 1 << shift;
 170
 171         /* Check the current status to avoid de-asserting the line twice */
 172         if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
 173                 return -EEXIST;
 174
 175         /* Clear the reset status by writing 1 to the status bit */
 176         omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
 177         /* de-assert the reset control line */
 178         omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
 179         /* wait the status to be set */
 180         omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
 181                           MAX_MODULE_HARDRESET_WAIT, c);
 182
 183         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 184 }
 185
 186 void omap4_prm_global_warm_sw_reset(void)
 187 {
 188         u32 v;
 189
 190         v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
 191                                     OMAP4_RM_RSTCTRL);
 192         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 193         omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
 194                                  OMAP4_RM_RSTCTRL);
 195
 196         /* OCP barrier */
 197         v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
 198                                     OMAP4_RM_RSTCTRL);
 199 }
 200
 201 void omap4_prm_global_cold_sw_reset(void)
 202 {
 203         u32 v;
 204
 205         v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
 206                                     OMAP4_RM_RSTCTRL);
 207         v |= OMAP4430_RST_GLOBAL_COLD_SW_MASK;
 208         omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
 209                                  OMAP4_RM_RSTCTRL);
 210
 211         /* OCP barrier */
 212         v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
 213                                     OMAP4_RM_RSTCTRL);
 214 }
 215
 216 /* PRM VP */
 217
 218 /*
 219  * struct omap4_prm_irq - OMAP4 VP register access description.
 220  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
 221  * @vp_tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 222  * @abb_tranxdone_status: ABB_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 223  */
 224 struct omap4_prm_irq {
 225         u32 irqstatus_mpu;
 226         u32 vp_tranxdone_status;
 227         u32 abb_tranxdone_status;
 228 };
 229
 230 static struct omap4_prm_irq omap4_prm_irqs[] = {
 231         [OMAP4_PRM_IRQ_VDD_MPU_ID] = {
 232                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
 233                 .vp_tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
 234                 .abb_tranxdone_status = OMAP4430_ABB_MPU_DONE_ST_MASK
 235         },
 236         [OMAP4_PRM_IRQ_VDD_IVA_ID] = {
 237                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 238                 .vp_tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
 239                 .abb_tranxdone_status = OMAP4430_ABB_IVA_DONE_ST_MASK,
 240         },
 241         [OMAP4_PRM_IRQ_VDD_CORE_ID] = {
 242                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 243                 .vp_tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 244                 /* Core has no ABB */
 245         },
 246 };
 247
 248 u32 omap4_prm_vp_check_txdone(u8 irq_id)
 249 {
 250         struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
 251         u32 irqstatus;
 252
 253         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 254                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 255                                                 irq->irqstatus_mpu);
 256         return irqstatus & irq->vp_tranxdone_status;
 257 }
 258
 259 void omap4_prm_vp_clear_txdone(u8 irq_id)
 260 {
 261         struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
 262
 263         omap4_prminst_write_inst_reg(irq->vp_tranxdone_status,
 264                                      OMAP4430_PRM_PARTITION,
 265                                      OMAP4430_PRM_OCP_SOCKET_INST,
 266                                      irq->irqstatus_mpu);
 267 };
 268
 269 u32 omap4_prm_abb_check_txdone(u8 irq_id)
 270 {
 271         struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
 272         u32 irqstatus;
 273
 274         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 275                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 276                                                 irq->irqstatus_mpu);
 277         return irqstatus & irq->abb_tranxdone_status;
 278 }
 279
 280 void omap4_prm_abb_clear_txdone(u8 irq_id)
 281 {
 282         struct omap4_prm_irq *irq = &omap4_prm_irqs[irq_id];
 283
 284         omap4_prminst_write_inst_reg(irq->abb_tranxdone_status,
 285                                      OMAP4430_PRM_PARTITION,
 286                                      OMAP4430_PRM_OCP_SOCKET_INST,
 287                                      irq->irqstatus_mpu);
 288 }
 289
 290 u32 omap4_prm_vcvp_read(u8 offset)
 291 {
 292         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 293                                            OMAP4430_PRM_DEVICE_INST, offset);
 294 }
 295
 296 void omap4_prm_vcvp_write(u32 val, u8 offset)
 297 {
 298         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 299                                      OMAP4430_PRM_DEVICE_INST, offset);
 300 }
 301
 302 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 303 {
 304         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 305                                                OMAP4430_PRM_PARTITION,
 306                                                OMAP4430_PRM_DEVICE_INST,
 307                                                offset);
 308 }