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ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / mach-versatile / core.c
blob0c99cf076c63a2a24c824d61c1fd1912065f0cd5
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
31 #include <linux/amba/pl022.h>
32 #include <linux/io.h>
33 #include <linux/gfp.h>
34 #include <linux/clkdev.h>
35 #include <linux/mtd/physmap.h>
36
37 #include <asm/system.h>
38 #include <asm/irq.h>
39 #include <asm/leds.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
42 #include <asm/hardware/vic.h>
43 #include <asm/mach-types.h>
44
45 #include <asm/mach/arch.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <mach/hardware.h>
50 #include <mach/platform.h>
51 #include <asm/hardware/timer-sp.h>
52
53 #include <plat/clcd.h>
54 #include <plat/fpga-irq.h>
55 #include <plat/sched_clock.h>
56
57 #include "core.h"
58
59 /*
60 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
61 * is the (PA >> 12).
62 *
63 * Setup a VA for the Versatile Vectored Interrupt Controller.
64 */
65 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
66 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
67
68 static struct fpga_irq_data sic_irq = {
69 .base = VA_SIC_BASE,
70 .irq_start = IRQ_SIC_START,
71 .chip.name = "SIC",
72 };
73
74 #if 1
75 #define IRQ_MMCI0A IRQ_VICSOURCE22
76 #define IRQ_AACI IRQ_VICSOURCE24
77 #define IRQ_ETH IRQ_VICSOURCE25
78 #define PIC_MASK 0xFFD00000
79 #else
80 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
81 #define IRQ_AACI IRQ_SIC_AACI
82 #define IRQ_ETH IRQ_SIC_ETH
83 #define PIC_MASK 0
84 #endif
85
86 void __init versatile_init_irq(void)
87 {
88 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
89
90 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
91
92 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
93
94 /*
95 * Interrupts on secondary controller from 0 to 8 are routed to
96 * source 31 on PIC.
97 * Interrupts from 21 to 31 are routed directly to the VIC on
98 * the corresponding number on primary controller. This is controlled
99 * by setting PIC_ENABLEx.
100 */
101 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
102 }
103
104 static struct map_desc versatile_io_desc[] __initdata = {
105 {
106 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
107 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
108 .length = SZ_4K,
109 .type = MT_DEVICE
110 }, {
111 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
112 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
113 .length = SZ_4K,
114 .type = MT_DEVICE
115 }, {
116 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
117 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
118 .length = SZ_4K,
119 .type = MT_DEVICE
120 }, {
121 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
122 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
123 .length = SZ_4K * 9,
124 .type = MT_DEVICE
125 },
126 #ifdef CONFIG_MACH_VERSATILE_AB
127 {
128 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
129 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
130 .length = SZ_4K,
131 .type = MT_DEVICE
132 }, {
133 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
134 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
135 .length = SZ_64M,
136 .type = MT_DEVICE
137 },
138 #endif
139 #ifdef CONFIG_DEBUG_LL
140 {
141 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
142 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
143 .length = SZ_4K,
144 .type = MT_DEVICE
145 },
146 #endif
147 #ifdef CONFIG_PCI
148 {
149 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
150 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
151 .length = SZ_4K,
152 .type = MT_DEVICE
153 }, {
154 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
155 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
156 .length = VERSATILE_PCI_BASE_SIZE,
157 .type = MT_DEVICE
158 }, {
159 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
160 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
161 .length = VERSATILE_PCI_CFG_BASE_SIZE,
162 .type = MT_DEVICE
163 },
164 #if 0
165 {
166 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
167 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
168 .length = SZ_16M,
169 .type = MT_DEVICE
170 }, {
171 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
172 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
173 .length = SZ_16M,
174 .type = MT_DEVICE
175 }, {
176 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
177 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
178 .length = SZ_16M,
179 .type = MT_DEVICE
180 },
181 #endif
182 #endif
183 };
184
185 void __init versatile_map_io(void)
186 {
187 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
188 }
189
190
191 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
192
193 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
194 {
195 u32 val;
196
197 val = __raw_readl(VERSATILE_FLASHCTRL);
198 if (on)
199 val |= VERSATILE_FLASHPROG_FLVPPEN;
200 else
201 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
202 __raw_writel(val, VERSATILE_FLASHCTRL);
203 }
204
205 static struct physmap_flash_data versatile_flash_data = {
206 .width = 4,
207 .set_vpp = versatile_flash_set_vpp,
208 };
209
210 static struct resource versatile_flash_resource = {
211 .start = VERSATILE_FLASH_BASE,
212 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
213 .flags = IORESOURCE_MEM,
214 };
215
216 static struct platform_device versatile_flash_device = {
217 .name = "physmap-flash",
218 .id = 0,
219 .dev = {
220 .platform_data = &versatile_flash_data,
221 },
222 .num_resources = 1,
223 .resource = &versatile_flash_resource,
224 };
225
226 static struct resource smc91x_resources[] = {
227 [0] = {
228 .start = VERSATILE_ETH_BASE,
229 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
230 .flags = IORESOURCE_MEM,
231 },
232 [1] = {
233 .start = IRQ_ETH,
234 .end = IRQ_ETH,
235 .flags = IORESOURCE_IRQ,
236 },
237 };
238
239 static struct platform_device smc91x_device = {
240 .name = "smc91x",
241 .id = 0,
242 .num_resources = ARRAY_SIZE(smc91x_resources),
243 .resource = smc91x_resources,
244 };
245
246 static struct resource versatile_i2c_resource = {
247 .start = VERSATILE_I2C_BASE,
248 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
249 .flags = IORESOURCE_MEM,
250 };
251
252 static struct platform_device versatile_i2c_device = {
253 .name = "versatile-i2c",
254 .id = 0,
255 .num_resources = 1,
256 .resource = &versatile_i2c_resource,
257 };
258
259 static struct i2c_board_info versatile_i2c_board_info[] = {
260 {
261 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
262 },
263 };
264
265 static int __init versatile_i2c_init(void)
266 {
267 return i2c_register_board_info(0, versatile_i2c_board_info,
268 ARRAY_SIZE(versatile_i2c_board_info));
269 }
270 arch_initcall(versatile_i2c_init);
271
272 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
273
274 unsigned int mmc_status(struct device *dev)
275 {
276 struct amba_device *adev = container_of(dev, struct amba_device, dev);
277 u32 mask;
278
279 if (adev->res.start == VERSATILE_MMCI0_BASE)
280 mask = 1;
281 else
282 mask = 2;
283
284 return readl(VERSATILE_SYSMCI) & mask;
285 }
286
287 static struct mmci_platform_data mmc0_plat_data = {
288 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
289 .status = mmc_status,
290 .gpio_wp = -1,
291 .gpio_cd = -1,
292 };
293
294 static struct resource char_lcd_resources[] = {
295 {
296 .start = VERSATILE_CHAR_LCD_BASE,
297 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
298 .flags = IORESOURCE_MEM,
299 },
300 };
301
302 static struct platform_device char_lcd_device = {
303 .name = "arm-charlcd",
304 .id = -1,
305 .num_resources = ARRAY_SIZE(char_lcd_resources),
306 .resource = char_lcd_resources,
307 };
308
309 /*
310 * Clock handling
311 */
312 static const struct icst_params versatile_oscvco_params = {
313 .ref = 24000000,
314 .vco_max = ICST307_VCO_MAX,
315 .vco_min = ICST307_VCO_MIN,
316 .vd_min = 4 + 8,
317 .vd_max = 511 + 8,
318 .rd_min = 1 + 2,
319 .rd_max = 127 + 2,
320 .s2div = icst307_s2div,
321 .idx2s = icst307_idx2s,
322 };
323
324 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
325 {
326 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
327 u32 val;
328
329 val = readl(clk->vcoreg) & ~0x7ffff;
330 val |= vco.v | (vco.r << 9) | (vco.s << 16);
331
332 writel(0xa05f, sys_lock);
333 writel(val, clk->vcoreg);
334 writel(0, sys_lock);
335 }
336
337 static const struct clk_ops osc4_clk_ops = {
338 .round = icst_clk_round,
339 .set = icst_clk_set,
340 .setvco = versatile_oscvco_set,
341 };
342
343 static struct clk osc4_clk = {
344 .ops = &osc4_clk_ops,
345 .params = &versatile_oscvco_params,
346 };
347
348 /*
349 * These are fixed clocks.
350 */
351 static struct clk ref24_clk = {
352 .rate = 24000000,
353 };
354
355 static struct clk sp804_clk = {
356 .rate = 1000000,
357 };
358
359 static struct clk dummy_apb_pclk;
360
361 static struct clk_lookup lookups[] = {
362 { /* AMBA bus clock */
363 .con_id = "apb_pclk",
364 .clk = &dummy_apb_pclk,
365 }, { /* UART0 */
366 .dev_id = "dev:f1",
367 .clk = &ref24_clk,
368 }, { /* UART1 */
369 .dev_id = "dev:f2",
370 .clk = &ref24_clk,
371 }, { /* UART2 */
372 .dev_id = "dev:f3",
373 .clk = &ref24_clk,
374 }, { /* UART3 */
375 .dev_id = "fpga:09",
376 .clk = &ref24_clk,
377 }, { /* KMI0 */
378 .dev_id = "fpga:06",
379 .clk = &ref24_clk,
380 }, { /* KMI1 */
381 .dev_id = "fpga:07",
382 .clk = &ref24_clk,
383 }, { /* MMC0 */
384 .dev_id = "fpga:05",
385 .clk = &ref24_clk,
386 }, { /* MMC1 */
387 .dev_id = "fpga:0b",
388 .clk = &ref24_clk,
389 }, { /* SSP */
390 .dev_id = "dev:f4",
391 .clk = &ref24_clk,
392 }, { /* CLCD */
393 .dev_id = "dev:20",
394 .clk = &osc4_clk,
395 }, { /* SP804 timers */
396 .dev_id = "sp804",
397 .clk = &sp804_clk,
398 },
399 };
400
401 /*
402 * CLCD support.
403 */
404 #define SYS_CLCD_MODE_MASK (3 << 0)
405 #define SYS_CLCD_MODE_888 (0 << 0)
406 #define SYS_CLCD_MODE_5551 (1 << 0)
407 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
408 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
409 #define SYS_CLCD_NLCDIOON (1 << 2)
410 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
411 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
412 #define SYS_CLCD_ID_MASK (0x1f << 8)
413 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
414 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
415 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
416 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
417 #define SYS_CLCD_ID_VGA (0x1f << 8)
418
419 static bool is_sanyo_2_5_lcd;
420
421 /*
422 * Disable all display connectors on the interface module.
423 */
424 static void versatile_clcd_disable(struct clcd_fb *fb)
425 {
426 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
427 u32 val;
428
429 val = readl(sys_clcd);
430 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
431 writel(val, sys_clcd);
432
433 #ifdef CONFIG_MACH_VERSATILE_AB
434 /*
435 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
436 */
437 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
438 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
439 unsigned long ctrl;
440
441 ctrl = readl(versatile_ib2_ctrl);
442 ctrl &= ~0x01;
443 writel(ctrl, versatile_ib2_ctrl);
444 }
445 #endif
446 }
447
448 /*
449 * Enable the relevant connector on the interface module.
450 */
451 static void versatile_clcd_enable(struct clcd_fb *fb)
452 {
453 struct fb_var_screeninfo *var = &fb->fb.var;
454 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
455 u32 val;
456
457 val = readl(sys_clcd);
458 val &= ~SYS_CLCD_MODE_MASK;
459
460 switch (var->green.length) {
461 case 5:
462 val |= SYS_CLCD_MODE_5551;
463 break;
464 case 6:
465 if (var->red.offset == 0)
466 val |= SYS_CLCD_MODE_565_RLSB;
467 else
468 val |= SYS_CLCD_MODE_565_BLSB;
469 break;
470 case 8:
471 val |= SYS_CLCD_MODE_888;
472 break;
473 }
474
475 /*
476 * Set the MUX
477 */
478 writel(val, sys_clcd);
479
480 /*
481 * And now enable the PSUs
482 */
483 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
484 writel(val, sys_clcd);
485
486 #ifdef CONFIG_MACH_VERSATILE_AB
487 /*
488 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
489 */
490 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
491 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
492 unsigned long ctrl;
493
494 ctrl = readl(versatile_ib2_ctrl);
495 ctrl |= 0x01;
496 writel(ctrl, versatile_ib2_ctrl);
497 }
498 #endif
499 }
500
501 /*
502 * Detect which LCD panel is connected, and return the appropriate
503 * clcd_panel structure. Note: we do not have any information on
504 * the required timings for the 8.4in panel, so we presently assume
505 * VGA timings.
506 */
507 static int versatile_clcd_setup(struct clcd_fb *fb)
508 {
509 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
510 const char *panel_name;
511 u32 val;
512
513 is_sanyo_2_5_lcd = false;
514
515 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
516 if (val == SYS_CLCD_ID_SANYO_3_8)
517 panel_name = "Sanyo TM38QV67A02A";
518 else if (val == SYS_CLCD_ID_SANYO_2_5) {
519 panel_name = "Sanyo QVGA Portrait";
520 is_sanyo_2_5_lcd = true;
521 } else if (val == SYS_CLCD_ID_EPSON_2_2)
522 panel_name = "Epson L2F50113T00";
523 else if (val == SYS_CLCD_ID_VGA)
524 panel_name = "VGA";
525 else {
526 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
527 val);
528 panel_name = "VGA";
529 }
530
531 fb->panel = versatile_clcd_get_panel(panel_name);
532 if (!fb->panel)
533 return -EINVAL;
534
535 return versatile_clcd_setup_dma(fb, SZ_1M);
536 }
537
538 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
539 {
540 clcdfb_decode(fb, regs);
541
542 /* Always clear BGR for RGB565: we do the routing externally */
543 if (fb->fb.var.green.length == 6)
544 regs->cntl &= ~CNTL_BGR;
545 }
546
547 static struct clcd_board clcd_plat_data = {
548 .name = "Versatile",
549 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
550 .check = clcdfb_check,
551 .decode = versatile_clcd_decode,
552 .disable = versatile_clcd_disable,
553 .enable = versatile_clcd_enable,
554 .setup = versatile_clcd_setup,
555 .mmap = versatile_clcd_mmap_dma,
556 .remove = versatile_clcd_remove_dma,
557 };
558
559 static struct pl061_platform_data gpio0_plat_data = {
560 .gpio_base = 0,
561 .irq_base = IRQ_GPIO0_START,
562 };
563
564 static struct pl061_platform_data gpio1_plat_data = {
565 .gpio_base = 8,
566 .irq_base = IRQ_GPIO1_START,
567 };
568
569 static struct pl022_ssp_controller ssp0_plat_data = {
570 .bus_id = 0,
571 .enable_dma = 0,
572 .num_chipselect = 1,
573 };
574
575 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
576 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
577 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
578 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
579
580 /*
581 * These devices are connected directly to the multi-layer AHB switch
582 */
583 #define SMC_IRQ { NO_IRQ, NO_IRQ }
584 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
585 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
586 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
587
588 /*
589 * These devices are connected via the core APB bridge
590 */
591 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
592 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
593 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
594 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
595 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
596
597 /*
598 * These devices are connected via the DMA APB bridge
599 */
600 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
601 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
602 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
603 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
604 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
605
606 /* FPGA Primecells */
607 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
608 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
609 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
610 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
611
612 /* DevChip Primecells */
613 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
614 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
615 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
616 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
617 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
618 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
619 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
620 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
621 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
622 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
623 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
624 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
625 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
626 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
627
628 static struct amba_device *amba_devs[] __initdata = {
629 &dmac_device,
630 &uart0_device,
631 &uart1_device,
632 &uart2_device,
633 &smc_device,
634 &mpmc_device,
635 &clcd_device,
636 &sctl_device,
637 &wdog_device,
638 &gpio0_device,
639 &gpio1_device,
640 &rtc_device,
641 &sci0_device,
642 &ssp0_device,
643 &aaci_device,
644 &mmc0_device,
645 &kmi0_device,
646 &kmi1_device,
647 };
648
649 #ifdef CONFIG_LEDS
650 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
651
652 static void versatile_leds_event(led_event_t ledevt)
653 {
654 unsigned long flags;
655 u32 val;
656
657 local_irq_save(flags);
658 val = readl(VA_LEDS_BASE);
659
660 switch (ledevt) {
661 case led_idle_start:
662 val = val & ~VERSATILE_SYS_LED0;
663 break;
664
665 case led_idle_end:
666 val = val | VERSATILE_SYS_LED0;
667 break;
668
669 case led_timer:
670 val = val ^ VERSATILE_SYS_LED1;
671 break;
672
673 case led_halted:
674 val = 0;
675 break;
676
677 default:
678 break;
679 }
680
681 writel(val, VA_LEDS_BASE);
682 local_irq_restore(flags);
683 }
684 #endif /* CONFIG_LEDS */
685
686 /* Early initializations */
687 void __init versatile_init_early(void)
688 {
689 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
690
691 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
692 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
693
694 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
695 }
696
697 void __init versatile_init(void)
698 {
699 int i;
700
701 platform_device_register(&versatile_flash_device);
702 platform_device_register(&versatile_i2c_device);
703 platform_device_register(&smc91x_device);
704 platform_device_register(&char_lcd_device);
705
706 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
707 struct amba_device *d = amba_devs[i];
708 amba_device_register(d, &iomem_resource);
709 }
710
711 #ifdef CONFIG_LEDS
712 leds_event = versatile_leds_event;
713 #endif
714 }
715
716 /*
717 * Where is the timer (VA)?
718 */
719 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
720 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
721 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
722 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
723
724 /*
725 * Set up timer interrupt, and return the current time in seconds.
726 */
727 static void __init versatile_timer_init(void)
728 {
729 u32 val;
730
731 /*
732 * set clock frequency:
733 * VERSATILE_REFCLK is 32KHz
734 * VERSATILE_TIMCLK is 1MHz
735 */
736 val = readl(__io_address(VERSATILE_SCTL_BASE));
737 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
738 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
739 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
740 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
741 __io_address(VERSATILE_SCTL_BASE));
742
743 /*
744 * Initialise to a known state (all timers off)
745 */
746 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
747 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
748 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
749 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
750
751 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
752 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
753 }
754
755 struct sys_timer versatile_timer = {
756 .init = versatile_timer_init,
757 };
758