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ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / plat-omap / dmtimer.c
blobedf3978421a4b2cce1b645b7b26ff408a88dd2a5
1 /*
2 * linux/arch/arm/plat-omap/dmtimer.c
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * dmtimer adaptation to platform_driver.
11 *
12 * Copyright (C) 2005 Nokia Corporation
13 * OMAP2 support by Juha Yrjola
14 * API improvements and OMAP2 clock framework support by Timo Teras
15 *
16 * Copyright (C) 2009 Texas Instruments
17 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38 #include <linux/clk.h>
39 #include <linux/delay.h>
40 #include <linux/io.h>
41 #include <linux/slab.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/err.h>
44 #include <linux/platform_device.h>
45
46 #include <plat/dmtimer.h>
47 #include <plat/common.h>
48 #include <plat/omap-pm.h>
49
50 /* register offsets */
51 #define _OMAP_TIMER_ID_OFFSET 0x00
52 #define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
53 #define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
54 #define _OMAP_TIMER_STAT_OFFSET 0x18
55 #define _OMAP_TIMER_INT_EN_OFFSET 0x1c
56 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
57 #define _OMAP_TIMER_CTRL_OFFSET 0x24
58 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
59 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
60 #define OMAP_TIMER_CTRL_PT (1 << 12)
61 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
62 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
63 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
64 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
65 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
66 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
67 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
68 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
69 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
70 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
71 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
72 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
73 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
74 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
75 #define WP_NONE 0 /* no write pending bit */
76 #define WP_TCLR (1 << 0)
77 #define WP_TCRR (1 << 1)
78 #define WP_TLDR (1 << 2)
79 #define WP_TTGR (1 << 3)
80 #define WP_TMAR (1 << 4)
81 #define WP_TPIR (1 << 5)
82 #define WP_TNIR (1 << 6)
83 #define WP_TCVR (1 << 7)
84 #define WP_TOCR (1 << 8)
85 #define WP_TOWR (1 << 9)
86 #define _OMAP_TIMER_MATCH_OFFSET 0x38
87 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
88 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
89 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
90 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
91 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
92 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
93 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
94 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
95
96 /* register offsets with the write pending bit encoded */
97 #define WPSHIFT 16
98
99 #define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102 #define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105 #define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108 #define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
109 | (WP_NONE << WPSHIFT))
110
111 #define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
112 | (WP_NONE << WPSHIFT))
113
114 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
115 | (WP_NONE << WPSHIFT))
116
117 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
118 | (WP_TCLR << WPSHIFT))
119
120 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
121 | (WP_TCRR << WPSHIFT))
122
123 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
124 | (WP_TLDR << WPSHIFT))
125
126 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
127 | (WP_TTGR << WPSHIFT))
128
129 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
133 | (WP_TMAR << WPSHIFT))
134
135 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
136 | (WP_NONE << WPSHIFT))
137
138 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
139 | (WP_NONE << WPSHIFT))
140
141 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
142 | (WP_NONE << WPSHIFT))
143
144 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
145 | (WP_TPIR << WPSHIFT))
146
147 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
148 | (WP_TNIR << WPSHIFT))
149
150 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
151 | (WP_TCVR << WPSHIFT))
152
153 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
154 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
155
156 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
157 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
158
159 /*
160 * OMAP4 IP revision has different register offsets
161 * for interrupt registers and functional registers.
162 */
163 #define VERSION2_TIMER_WAKEUP_EN_REG_OFFSET 0x14
164 #define VERSION2_TIMER_STAT_REG_OFFSET 0x10
165
166 #define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */
167
168 static LIST_HEAD(omap_timer_list);
169 static DEFINE_MUTEX(dm_timer_mutex);
170
171 /**
172 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
173 * @timer: timer pointer over which read operation to perform
174 * @reg: lowest byte holds the register offset
175 *
176 * The posted mode bit is encoded in reg. Note that in posted mode write
177 * pending bit must be checked. Otherwise a read of a non completed write
178 * will produce an error.
179 */
180 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
181 {
182 int i = 0;
183
184 if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
185 reg += timer->func_offset;
186 else if (reg >= OMAP_TIMER_STAT_REG)
187 reg += timer->intr_offset;
188
189 if (timer->posted) {
190 omap_test_timeout(!(readl(timer->io_base +
191 ((OMAP_TIMER_WRITE_PEND_REG +
192 timer->func_offset) & 0xff)) & (reg >> WPSHIFT)),
193 MAX_WRITE_PEND_WAIT, i);
194
195 if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT))
196 dev_err(&timer->pdev->dev, "read timeout.\n");
197 }
198
199 return readl(timer->io_base + (reg & 0xff));
200 }
201
202 /**
203 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
204 * @timer: timer pointer over which write operation is to perform
205 * @reg: lowest byte holds the register offset
206 * @value: data to write into the register
207 *
208 * The posted mode bit is encoded in reg. Note that in posted mode the write
209 * pending bit must be checked. Otherwise a write on a register which has a
210 * pending write will be lost.
211 */
212 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
213 u32 value)
214 {
215 int i = 0;
216
217 if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
218 reg += timer->func_offset;
219 else if (reg >= OMAP_TIMER_STAT_REG)
220 reg += timer->intr_offset;
221
222 if (timer->posted) {
223 omap_test_timeout(!(readl(timer->io_base +
224 ((OMAP_TIMER_WRITE_PEND_REG +
225 timer->func_offset) & 0xff)) & (reg >> WPSHIFT)),
226 MAX_WRITE_PEND_WAIT, i);
227
228 if (WARN_ON(i == MAX_WRITE_PEND_WAIT))
229 dev_err(&timer->pdev->dev, "write timeout.\n");
230 }
231
232 writel(value, timer->io_base + (reg & 0xff));
233 }
234
235 static void omap_timer_save_context(struct omap_dm_timer *timer)
236 {
237 timer->context.tiocp_cfg =
238 omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
239 timer->context.tistat =
240 omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG);
241 timer->context.tisr =
242 omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
243 timer->context.tier =
244 omap_dm_timer_read_reg(timer, OMAP_TIMER_INT_EN_REG);
245 timer->context.twer =
246 omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
247 timer->context.tclr =
248 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
249 timer->context.tcrr =
250 omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
251 timer->context.tldr =
252 omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
253 timer->context.tmar =
254 omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
255 timer->context.tsicr =
256 omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
257 }
258
259 static void omap_timer_restore_context(struct omap_dm_timer *timer)
260 {
261 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG,
262 timer->context.tiocp_cfg);
263 omap_dm_timer_write_reg(timer, OMAP_TIMER_SYS_STAT_REG,
264 timer->context.tistat);
265 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
266 timer->context.tisr);
267 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG,
268 timer->context.tier);
269 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
270 timer->context.twer);
271 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
272 timer->context.tclr);
273 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
274 timer->context.tcrr);
275 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
276 timer->context.tldr);
277 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
278 timer->context.tmar);
279 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
280 timer->context.tsicr);
281 }
282
283 static void __timer_enable(struct omap_dm_timer *timer)
284 {
285 if (!timer->enabled) {
286 if (timer->loses_context)
287 pm_runtime_get_sync(&timer->pdev->dev);
288 timer->enabled = 1;
289 }
290 }
291
292 static void __timer_disable(struct omap_dm_timer *timer)
293 {
294 if (timer->enabled) {
295 if (timer->loses_context)
296 pm_runtime_put_sync_suspend(&timer->pdev->dev);
297 timer->enabled = 0;
298 }
299 }
300
301 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
302 {
303 int c;
304
305 c = 0;
306 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
307 c++;
308 if (c > 100000) {
309 printk(KERN_ERR "Timer failed to reset\n");
310 return;
311 }
312 }
313 }
314
315 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
316 {
317 u32 l;
318
319 if (!timer->is_early_init)
320 __timer_enable(timer);
321
322 if (timer->pdev->id != 1) {
323 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
324 omap_dm_timer_wait_for_reset(timer);
325 }
326
327 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
328 l |= 0x02 << 3; /* Set to smart-idle mode */
329 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
330 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
331
332 if (!timer->is_early_init)
333 __timer_disable(timer);
334 }
335
336 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
337 {
338 int ret;
339
340 timer->fclk = clk_get(&timer->pdev->dev, "fck");
341 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
342 timer->fclk = NULL;
343 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
344 return -EINVAL;
345 }
346
347 if (unlikely(timer->is_early_init)) {
348 ret = clk_enable(timer->fclk);
349 if (ret) {
350 clk_put(timer->fclk);
351 return -EINVAL;
352 }
353 goto end;
354 }
355
356 if (timer->needs_manual_reset)
357 omap_dm_timer_reset(timer);
358
359 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
360
361 end:
362 if (!timer->is_early_init)
363 __timer_enable(timer);
364
365 /* Match hardware reset default of posted mode */
366 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
367 OMAP_TIMER_CTRL_POSTED);
368
369 if (!timer->is_early_init)
370 __timer_disable(timer);
371
372 timer->posted = 1;
373 return 0;
374 }
375
376 struct omap_dm_timer *omap_dm_timer_request(void)
377 {
378 struct omap_dm_timer *timer = NULL, *t;
379 int ret;
380
381 mutex_lock(&dm_timer_mutex);
382 list_for_each_entry(t, &omap_timer_list, node) {
383 if (t->reserved)
384 continue;
385
386 timer = t;
387 timer->reserved = 1;
388 timer->enabled = 0;
389 break;
390 }
391 mutex_unlock(&dm_timer_mutex);
392
393 if (!timer) {
394 pr_debug("%s: free timer not available.\n", __func__);
395 return NULL;
396 }
397 ret = omap_dm_timer_prepare(timer);
398 if (ret) {
399 timer->reserved = 0;
400 return NULL;
401 }
402
403 return timer;
404 }
405 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
406
407 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
408 {
409 struct omap_dm_timer *timer = NULL, *t;
410 int ret;
411
412 mutex_lock(&dm_timer_mutex);
413 list_for_each_entry(t, &omap_timer_list, node) {
414 if (t->pdev->id == id && !t->reserved) {
415 timer = t;
416 timer->reserved = 1;
417 timer->enabled = 0;
418 break;
419 }
420 }
421 mutex_unlock(&dm_timer_mutex);
422
423 if (!timer) {
424 pr_debug("%s: timer%d not available.\n", __func__, id);
425 return NULL;
426 }
427 ret = omap_dm_timer_prepare(timer);
428 if (ret) {
429 timer->reserved = 0;
430 return NULL;
431 }
432
433 return timer;
434 }
435 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
436
437 int omap_dm_timer_free(struct omap_dm_timer *timer)
438 {
439 unsigned long flags;
440 if (!timer)
441 return -EINVAL;
442
443 spin_lock_irqsave(&timer->lock, flags);
444 if (!timer->reserved) {
445 spin_unlock_irqrestore(&timer->lock, flags);
446 return -EINVAL;
447 }
448
449 __timer_disable(timer);
450 clk_put(timer->fclk);
451
452 timer->reserved = 0;
453 timer->context_saved = false;
454
455 spin_unlock_irqrestore(&timer->lock, flags);
456 return 0;
457 }
458 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
459
460 int omap_dm_timer_enable(struct omap_dm_timer *timer)
461 {
462 unsigned long flags;
463 if (!timer)
464 return -EINVAL;
465
466 spin_lock_irqsave(&timer->lock, flags);
467 __timer_enable(timer);
468 spin_unlock_irqrestore(&timer->lock, flags);
469 return 0;
470 }
471 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
472
473 int omap_dm_timer_disable(struct omap_dm_timer *timer)
474 {
475 unsigned long flags;
476 if (!timer)
477 return -EINVAL;
478
479 spin_lock_irqsave(&timer->lock, flags);
480 __timer_disable(timer);
481 spin_unlock_irqrestore(&timer->lock, flags);
482 return 0;
483 }
484 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
485
486 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
487 {
488 if (timer)
489 return timer->irq;
490 return -EINVAL;
491 }
492 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
493
494 #if defined(CONFIG_ARCH_OMAP1)
495
496 /**
497 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
498 * @inputmask: current value of idlect mask
499 */
500 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
501 {
502 int i = 0;
503 struct omap_dm_timer *timer = NULL;
504
505 /* If ARMXOR cannot be idled this function call is unnecessary */
506 if (!(inputmask & (1 << 1)))
507 return inputmask;
508
509 /* If any active timer is using ARMXOR return modified mask */
510 mutex_lock(&dm_timer_mutex);
511 list_for_each_entry(timer, &omap_timer_list, node) {
512
513 u32 l;
514
515 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
516 if (l & OMAP_TIMER_CTRL_ST) {
517 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
518 inputmask &= ~(1 << 1);
519 else
520 inputmask &= ~(1 << 2);
521 }
522 i++;
523 }
524 mutex_unlock(&dm_timer_mutex);
525
526 return inputmask;
527 }
528 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
529
530 #else
531
532 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
533 {
534 if (timer)
535 return timer->fclk;
536 return NULL;
537 }
538 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
539
540 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
541 {
542 BUG();
543
544 return 0;
545 }
546 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
547
548 #endif
549
550 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
551 {
552 unsigned long flags;
553
554 if (!timer)
555 return -EINVAL;
556
557 spin_lock_irqsave(&timer->lock, flags);
558 if (timer->enabled) {
559 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
560 spin_unlock_irqrestore(&timer->lock, flags);
561 return 0;
562 }
563 spin_unlock_irqrestore(&timer->lock, flags);
564 return -EINVAL;
565 }
566 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
567
568 int omap_dm_timer_start(struct omap_dm_timer *timer)
569 {
570 u32 l;
571 unsigned long flags;
572
573 if (!timer)
574 return -EINVAL;
575
576 spin_lock_irqsave(&timer->lock, flags);
577 __timer_enable(timer);
578 if (timer->loses_context) {
579 if (omap_pm_was_context_lost(&timer->pdev->dev) &&
580 timer->context_saved) {
581 omap_timer_restore_context(timer);
582 timer->context_saved = false;
583 }
584 }
585
586 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
587 if (!(l & OMAP_TIMER_CTRL_ST)) {
588 l |= OMAP_TIMER_CTRL_ST;
589 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
590 }
591 spin_unlock_irqrestore(&timer->lock, flags);
592 return 0;
593 }
594 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
595
596 int omap_dm_timer_stop(struct omap_dm_timer *timer)
597 {
598 u32 l;
599 struct dmtimer_platform_data *pdata;
600 unsigned long flags;
601
602 if (!timer)
603 return -EINVAL;
604
605 spin_lock_irqsave(&timer->lock, flags);
606 if (!timer->enabled) {
607 spin_unlock_irqrestore(&timer->lock, flags);
608 return -EINVAL;
609 }
610
611 pdata = timer->pdev->dev.platform_data;
612 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
613 if (l & OMAP_TIMER_CTRL_ST) {
614 l &= ~0x1;
615 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
616
617 if (!pdata->needs_manual_reset) {
618 /* Readback to make sure write has completed */
619 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
620 /*
621 * Wait for functional clock period x 3.5 to make
622 * sure that timer is stopped
623 */
624 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
625 }
626 }
627 /* Ack possibly pending interrupt */
628 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
629 OMAP_TIMER_INT_OVERFLOW);
630
631 if (timer->loses_context) {
632 omap_timer_save_context(timer);
633 timer->context_saved = true;
634 }
635 __timer_disable(timer);
636 spin_unlock_irqrestore(&timer->lock, flags);
637 return 0;
638 }
639 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
640
641 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
642 {
643 int ret;
644 struct dmtimer_platform_data *pdata;
645 unsigned long flags;
646
647 if (!timer)
648 return -EINVAL;
649
650 if (source < 0 || source >= 3)
651 return -EINVAL;
652
653 spin_lock_irqsave(&timer->lock, flags);
654 pdata = timer->pdev->dev.platform_data;
655 __timer_disable(timer);
656 spin_unlock_irqrestore(&timer->lock, flags);
657
658 /* change the timer clock source */
659 ret = pdata->set_timer_src(timer->pdev, source);
660
661 /*
662 * When the functional clock disappears, too quick writes seem
663 * to cause an abort. XXX Is this still necessary?
664 */
665 __delay(300000);
666
667 return ret;
668 }
669 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
670
671 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
672 unsigned int load)
673 {
674 u32 l;
675
676 unsigned long flags;
677 if (!timer)
678 return -EINVAL;
679
680 spin_lock_irqsave(&timer->lock, flags);
681 __timer_enable(timer);
682 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
683 if (autoreload)
684 l |= OMAP_TIMER_CTRL_AR;
685 else
686 l &= ~OMAP_TIMER_CTRL_AR;
687 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
688 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
689
690 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
691 __timer_disable(timer);
692 spin_unlock_irqrestore(&timer->lock, flags);
693 return 0;
694 }
695 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
696
697 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
698 unsigned int load)
699 {
700 u32 l;
701 unsigned long flags;
702
703 if (!timer)
704 return -EINVAL;
705
706 spin_lock_irqsave(&timer->lock, flags);
707 __timer_enable(timer);
708 if (timer->loses_context) {
709 if (omap_pm_was_context_lost(&timer->pdev->dev) &&
710 timer->context_saved) {
711 omap_timer_restore_context(timer);
712 timer->context_saved = false;
713 }
714 }
715
716 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
717 if (autoreload) {
718 l |= OMAP_TIMER_CTRL_AR;
719 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
720 } else {
721 l &= ~OMAP_TIMER_CTRL_AR;
722 }
723 l |= OMAP_TIMER_CTRL_ST;
724
725 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
726 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
727 spin_unlock_irqrestore(&timer->lock, flags);
728 return 0;
729 }
730 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
731
732 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
733 unsigned int match)
734 {
735 u32 l;
736 unsigned long flags;
737
738 if (!timer)
739 return -EINVAL;
740
741 spin_lock_irqsave(&timer->lock, flags);
742 __timer_enable(timer);
743 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
744 if (enable)
745 l |= OMAP_TIMER_CTRL_CE;
746 else
747 l &= ~OMAP_TIMER_CTRL_CE;
748 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
749 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
750 __timer_disable(timer);
751 spin_unlock_irqrestore(&timer->lock, flags);
752 return 0;
753 }
754 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
755
756 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
757 int toggle, int trigger)
758 {
759 u32 l;
760 unsigned long flags;
761
762 if (!timer)
763 return -EINVAL;
764
765 spin_lock_irqsave(&timer->lock, flags);
766 __timer_enable(timer);
767 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
768 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
769 OMAP_TIMER_CTRL_PT | (0x03 << 10));
770 if (def_on)
771 l |= OMAP_TIMER_CTRL_SCPWM;
772 if (toggle)
773 l |= OMAP_TIMER_CTRL_PT;
774 l |= trigger << 10;
775 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
776 __timer_disable(timer);
777 spin_unlock_irqrestore(&timer->lock, flags);
778 return 0;
779 }
780 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
781
782 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
783 {
784 u32 l;
785 unsigned long flags;
786
787 if (!timer)
788 return -EINVAL;
789
790 spin_lock_irqsave(&timer->lock, flags);
791 __timer_enable(timer);
792 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
793 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
794 if (prescaler >= 0x00 && prescaler <= 0x07) {
795 l |= OMAP_TIMER_CTRL_PRE;
796 l |= prescaler << 2;
797 }
798 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
799 __timer_disable(timer);
800 spin_unlock_irqrestore(&timer->lock, flags);
801 return 0;
802 }
803 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
804
805 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
806 unsigned int value)
807 {
808 unsigned long flags;
809 if (!timer)
810 return -EINVAL;
811
812 spin_lock_irqsave(&timer->lock, flags);
813 if (!timer->is_early_init)
814 __timer_enable(timer);
815
816 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
817 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
818
819 if (!timer->is_early_init)
820 __timer_disable(timer);
821 spin_unlock_irqrestore(&timer->lock, flags);
822 return 0;
823 }
824 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
825
826 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
827 {
828 unsigned long flags;
829 unsigned int ret;
830
831 if (WARN_ON(!timer))
832 return -EINVAL;
833
834 spin_lock_irqsave(&timer->lock, flags);
835 if (timer->is_early_init || timer->enabled) {
836 ret = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
837 spin_unlock_irqrestore(&timer->lock, flags);
838 return ret;
839 }
840 spin_unlock_irqrestore(&timer->lock, flags);
841 WARN_ON(!timer->enabled);
842 return -EINVAL;
843 }
844 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
845
846 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
847 {
848 unsigned long flags;
849
850 if (!timer)
851 return -EINVAL;
852
853 spin_lock_irqsave(&timer->lock, flags);
854 if (timer->is_early_init || timer->enabled) {
855 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
856 spin_unlock_irqrestore(&timer->lock, flags);
857 return 0;
858 }
859 spin_unlock_irqrestore(&timer->lock, flags);
860 return -EINVAL;
861 }
862 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
863
864 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
865 {
866 unsigned long flags;
867 unsigned int ret;
868
869 if (WARN_ON(!timer))
870 return -EINVAL;
871
872 spin_lock_irqsave(&timer->lock, flags);
873 if (timer->is_early_init || timer->enabled) {
874 ret = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
875 spin_unlock_irqrestore(&timer->lock, flags);
876 return ret;
877 }
878
879 spin_unlock_irqrestore(&timer->lock, flags);
880 WARN_ON(!timer->enabled);
881 return -EINVAL;
882 }
883 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
884
885 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
886 {
887 unsigned long flags;
888
889 if (!timer)
890 return -EINVAL;
891
892 spin_lock_irqsave(&timer->lock, flags);
893 if (timer->is_early_init || timer->enabled) {
894 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
895 spin_unlock_irqrestore(&timer->lock, flags);
896 return 0;
897 }
898 spin_unlock_irqrestore(&timer->lock, flags);
899 return -EINVAL;
900 }
901 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
902
903 int omap_dm_timers_active(void)
904 {
905 struct omap_dm_timer *timer;
906
907 list_for_each_entry(timer, &omap_timer_list, node) {
908 if (!timer->enabled)
909 continue;
910
911 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
912 OMAP_TIMER_CTRL_ST) {
913 return 1;
914 }
915 }
916 return 0;
917 }
918 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
919
920 void omap_dm_timer_save_context(struct omap_dm_timer *timer)
921 {
922 omap_timer_save_context(timer);
923 }
924 EXPORT_SYMBOL_GPL(omap_dm_timer_save_context);
925
926 /**
927 * omap_dm_timer_probe - probe function called for every registered device
928 * @pdev: pointer to current timer platform device
929 *
930 * Called by driver framework at the end of device registration for all
931 * timer devices.
932 */
933 static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
934 {
935 int ret;
936 struct omap_dm_timer *timer;
937 struct resource *mem, *irq, *ioarea;
938 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
939
940 if (!pdata) {
941 dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
942 return -ENODEV;
943 }
944
945 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
946 if (unlikely(!irq)) {
947 dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
948 return -ENODEV;
949 }
950
951 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
952 if (unlikely(!mem)) {
953 dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
954 return -ENODEV;
955 }
956
957 ioarea = request_mem_region(mem->start, resource_size(mem),
958 pdev->name);
959 if (!ioarea) {
960 dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
961 return -EBUSY;
962 }
963
964 timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
965 if (!timer) {
966 dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
967 __func__);
968 ret = -ENOMEM;
969 goto err_release_ioregion;
970 }
971
972 timer->io_base = ioremap(mem->start, resource_size(mem));
973 if (!timer->io_base) {
974 dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
975 ret = -ENOMEM;
976 goto err_free_mem;
977 }
978
979 if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) {
980 timer->func_offset = VERSION2_TIMER_WAKEUP_EN_REG_OFFSET;
981 timer->intr_offset = VERSION2_TIMER_STAT_REG_OFFSET;
982 }
983
984 timer->irq = irq->start;
985 timer->pdev = pdev;
986 timer->is_early_init = pdata->is_early_init;
987 timer->needs_manual_reset = pdata->needs_manual_reset;
988 timer->loses_context = pdata->loses_context;
989
990 spin_lock_init(&timer->lock);
991 /* Skip pm_runtime_enable during early boot and for OMAP1 */
992 if (!pdata->is_early_init && !pdata->needs_manual_reset) {
993 pm_runtime_enable(&pdev->dev);
994 pm_runtime_irq_safe(&pdev->dev);
995 }
996
997 /* add the timer element to the list */
998 mutex_lock(&dm_timer_mutex);
999 list_add_tail(&timer->node, &omap_timer_list);
1000 mutex_unlock(&dm_timer_mutex);
1001
1002 dev_dbg(&pdev->dev, "Device Probed.\n");
1003
1004 return 0;
1005
1006 err_free_mem:
1007 kfree(timer);
1008
1009 err_release_ioregion:
1010 release_mem_region(mem->start, resource_size(mem));
1011
1012 return ret;
1013 }
1014
1015 /**
1016 * omap_dm_timer_remove - cleanup a registered timer device
1017 * @pdev: pointer to current timer platform device
1018 *
1019 * Called by driver framework whenever a timer device is unregistered.
1020 * In addition to freeing platform resources it also deletes the timer
1021 * entry from the local list.
1022 */
1023 static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
1024 {
1025 struct omap_dm_timer *timer;
1026 int ret = -EINVAL;
1027
1028 mutex_lock(&dm_timer_mutex);
1029 list_for_each_entry(timer, &omap_timer_list, node) {
1030 if (timer->pdev->id == pdev->id) {
1031 list_del(&timer->node);
1032 kfree(timer);
1033 ret = 0;
1034 break;
1035 }
1036 }
1037 mutex_unlock(&dm_timer_mutex);
1038 pm_runtime_disable(&pdev->dev);
1039
1040 return ret;
1041 }
1042
1043 static struct platform_driver omap_dm_timer_driver = {
1044 .probe = omap_dm_timer_probe,
1045 .remove = omap_dm_timer_remove,
1046 .driver = {
1047 .name = "omap_timer",
1048 },
1049 };
1050
1051 static int __init omap_dm_timer_driver_init(void)
1052 {
1053 return platform_driver_register(&omap_dm_timer_driver);
1054 }
1055
1056 static void __exit omap_dm_timer_driver_exit(void)
1057 {
1058 platform_driver_unregister(&omap_dm_timer_driver);
1059 }
1060
1061 early_platform_init("earlytimer", &omap_dm_timer_driver);
1062 module_init(omap_dm_timer_driver_init);
1063 module_exit(omap_dm_timer_driver_exit);
1064
1065 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
1066 MODULE_LICENSE("GPL");
1067 MODULE_ALIAS("platform:" DRIVER_NAME);
1068 MODULE_AUTHOR("Texas Instruments Inc");