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ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / plat-omap / mcbsp.c
blobe02baa43de00f44cff47835826d309c633585f7f
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <plat/dma.h>
29 #include <plat/mcbsp.h>
30 #include <plat/omap_device.h>
31 #include <linux/pm_runtime.h>
32
33 /* XXX These "sideways" includes are a sign that something is wrong */
34 #include "../mach-omap2/cm2xxx_3xxx.h"
35 #include "../mach-omap2/cm-regbits-34xx.h"
36
37 struct omap_mcbsp **mcbsp_ptr;
38 int omap_mcbsp_count, omap_mcbsp_cache_size;
39
40 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
41 {
42 if (cpu_class_is_omap1()) {
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
44 __raw_writew((u16)val, mcbsp->io_base + reg);
45 } else if (cpu_is_omap2420()) {
46 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
47 __raw_writew((u16)val, mcbsp->io_base + reg);
48 } else {
49 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
50 __raw_writel(val, mcbsp->io_base + reg);
51 }
52 }
53
54 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
55 {
56 if (cpu_class_is_omap1()) {
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
59 } else if (cpu_is_omap2420()) {
60 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
61 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
62 } else {
63 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
64 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
65 }
66 }
67
68 #ifdef CONFIG_ARCH_OMAP3
69 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
70 {
71 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
72 }
73
74 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
75 {
76 return __raw_readl(mcbsp->st_data->io_base_st + reg);
77 }
78
79 #define MCBSP_ST_READ(mcbsp, reg) \
80 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
81 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
82 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
83 #endif
84
85 #define MCBSP_READ(mcbsp, reg) \
86 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
87 #define MCBSP_WRITE(mcbsp, reg, val) \
88 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
89 #define MCBSP_READ_CACHE(mcbsp, reg) \
90 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
91
92 static void omap_mcbsp_dump_reg(u8 id)
93 {
94 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
95
96 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
97 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
98 MCBSP_READ(mcbsp, DRR2));
99 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
100 MCBSP_READ(mcbsp, DRR1));
101 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
102 MCBSP_READ(mcbsp, DXR2));
103 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
104 MCBSP_READ(mcbsp, DXR1));
105 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
106 MCBSP_READ(mcbsp, SPCR2));
107 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
108 MCBSP_READ(mcbsp, SPCR1));
109 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
110 MCBSP_READ(mcbsp, RCR2));
111 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
112 MCBSP_READ(mcbsp, RCR1));
113 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
114 MCBSP_READ(mcbsp, XCR2));
115 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
116 MCBSP_READ(mcbsp, XCR1));
117 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
118 MCBSP_READ(mcbsp, SRGR2));
119 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
120 MCBSP_READ(mcbsp, SRGR1));
121 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
122 MCBSP_READ(mcbsp, PCR0));
123 dev_dbg(mcbsp->dev, "***********************\n");
124 }
125
126 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
127 {
128 struct omap_mcbsp *mcbsp_tx = dev_id;
129 u16 irqst_spcr2;
130
131 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
132 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
133
134 if (irqst_spcr2 & XSYNC_ERR) {
135 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
136 irqst_spcr2);
137 /* Writing zero to XSYNC_ERR clears the IRQ */
138 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
139 } else {
140 complete(&mcbsp_tx->tx_irq_completion);
141 }
142
143 return IRQ_HANDLED;
144 }
145
146 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
147 {
148 struct omap_mcbsp *mcbsp_rx = dev_id;
149 u16 irqst_spcr1;
150
151 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
152 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
153
154 if (irqst_spcr1 & RSYNC_ERR) {
155 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
156 irqst_spcr1);
157 /* Writing zero to RSYNC_ERR clears the IRQ */
158 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
159 } else {
160 complete(&mcbsp_rx->rx_irq_completion);
161 }
162
163 return IRQ_HANDLED;
164 }
165
166 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
167 {
168 struct omap_mcbsp *mcbsp_dma_tx = data;
169
170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
172
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
176
177 complete(&mcbsp_dma_tx->tx_dma_completion);
178 }
179
180 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
181 {
182 struct omap_mcbsp *mcbsp_dma_rx = data;
183
184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
186
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
190
191 complete(&mcbsp_dma_rx->rx_dma_completion);
192 }
193
194 /*
195 * omap_mcbsp_config simply write a config to the
196 * appropriate McBSP.
197 * You either call this function or set the McBSP registers
198 * by yourself before calling omap_mcbsp_start().
199 */
200 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
201 {
202 struct omap_mcbsp *mcbsp;
203
204 if (!omap_mcbsp_check_valid_id(id)) {
205 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
206 return;
207 }
208 mcbsp = id_to_mcbsp_ptr(id);
209
210 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
211 mcbsp->id, mcbsp->phys_base);
212
213 /* We write the given config */
214 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
215 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
216 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
217 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
218 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
219 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
220 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
221 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
222 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
223 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
224 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
225 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
226 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
227 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
228 }
229 }
230 EXPORT_SYMBOL(omap_mcbsp_config);
231
232 /**
233 * omap_mcbsp_dma_params - returns the dma channel number
234 * @id - mcbsp id
235 * @stream - indicates the direction of data flow (rx or tx)
236 *
237 * Returns the dma channel number for the rx channel or tx channel
238 * based on the value of @stream for the requested mcbsp given by @id
239 */
240 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
241 {
242 struct omap_mcbsp *mcbsp;
243
244 if (!omap_mcbsp_check_valid_id(id)) {
245 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
246 return -ENODEV;
247 }
248 mcbsp = id_to_mcbsp_ptr(id);
249
250 if (stream)
251 return mcbsp->dma_rx_sync;
252 else
253 return mcbsp->dma_tx_sync;
254 }
255 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
256
257 /**
258 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
259 * @id - mcbsp id
260 * @stream - indicates the direction of data flow (rx or tx)
261 *
262 * Returns the address of mcbsp data transmit register or data receive register
263 * to be used by DMA for transferring/receiving data based on the value of
264 * @stream for the requested mcbsp given by @id
265 */
266 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
267 {
268 struct omap_mcbsp *mcbsp;
269 int data_reg;
270
271 if (!omap_mcbsp_check_valid_id(id)) {
272 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
273 return -ENODEV;
274 }
275 mcbsp = id_to_mcbsp_ptr(id);
276
277 data_reg = mcbsp->phys_dma_base;
278
279 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
280 if (stream)
281 data_reg += OMAP_MCBSP_REG_DRR1;
282 else
283 data_reg += OMAP_MCBSP_REG_DXR1;
284 } else {
285 if (stream)
286 data_reg += OMAP_MCBSP_REG_DRR;
287 else
288 data_reg += OMAP_MCBSP_REG_DXR;
289 }
290
291 return data_reg;
292 }
293 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
294
295 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
296 static struct omap_device *find_omap_device_by_dev(struct device *dev)
297 {
298 struct platform_device *pdev = container_of(dev,
299 struct platform_device, dev);
300 return container_of(pdev, struct omap_device, pdev);
301 }
302 #endif
303
304 #ifdef CONFIG_ARCH_OMAP3
305 static void omap_st_on(struct omap_mcbsp *mcbsp)
306 {
307 unsigned int w;
308 struct omap_device *od;
309
310 od = find_omap_device_by_dev(mcbsp->dev);
311
312 /*
313 * Sidetone uses McBSP ICLK - which must not idle when sidetones
314 * are enabled or sidetones start sounding ugly.
315 */
316 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
317 w &= ~(1 << (mcbsp->id - 2));
318 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
319
320 /* Enable McBSP Sidetone */
321 w = MCBSP_READ(mcbsp, SSELCR);
322 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
323
324 /* Enable Sidetone from Sidetone Core */
325 w = MCBSP_ST_READ(mcbsp, SSELCR);
326 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
327 }
328
329 static void omap_st_off(struct omap_mcbsp *mcbsp)
330 {
331 unsigned int w;
332 struct omap_device *od;
333
334 od = find_omap_device_by_dev(mcbsp->dev);
335
336 w = MCBSP_ST_READ(mcbsp, SSELCR);
337 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
338
339 w = MCBSP_READ(mcbsp, SSELCR);
340 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
341
342 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
343 w |= 1 << (mcbsp->id - 2);
344 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
345 }
346
347 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
348 {
349 u16 val, i;
350 struct omap_device *od;
351
352 od = find_omap_device_by_dev(mcbsp->dev);
353
354 val = MCBSP_ST_READ(mcbsp, SSELCR);
355
356 if (val & ST_COEFFWREN)
357 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
358
359 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
360
361 for (i = 0; i < 128; i++)
362 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
363
364 i = 0;
365
366 val = MCBSP_ST_READ(mcbsp, SSELCR);
367 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
368 val = MCBSP_ST_READ(mcbsp, SSELCR);
369
370 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
371
372 if (i == 1000)
373 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
374 }
375
376 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
377 {
378 u16 w;
379 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
380 struct omap_device *od;
381
382 od = find_omap_device_by_dev(mcbsp->dev);
383
384 w = MCBSP_ST_READ(mcbsp, SSELCR);
385
386 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
387 ST_CH1GAIN(st_data->ch1gain));
388 }
389
390 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
391 {
392 struct omap_mcbsp *mcbsp;
393 struct omap_mcbsp_st_data *st_data;
394 int ret = 0;
395
396 if (!omap_mcbsp_check_valid_id(id)) {
397 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
398 return -ENODEV;
399 }
400
401 mcbsp = id_to_mcbsp_ptr(id);
402 st_data = mcbsp->st_data;
403
404 if (!st_data)
405 return -ENOENT;
406
407 spin_lock_irq(&mcbsp->lock);
408 if (channel == 0)
409 st_data->ch0gain = chgain;
410 else if (channel == 1)
411 st_data->ch1gain = chgain;
412 else
413 ret = -EINVAL;
414
415 if (st_data->enabled)
416 omap_st_chgain(mcbsp);
417 spin_unlock_irq(&mcbsp->lock);
418
419 return ret;
420 }
421 EXPORT_SYMBOL(omap_st_set_chgain);
422
423 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
424 {
425 struct omap_mcbsp *mcbsp;
426 struct omap_mcbsp_st_data *st_data;
427 int ret = 0;
428
429 if (!omap_mcbsp_check_valid_id(id)) {
430 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
431 return -ENODEV;
432 }
433
434 mcbsp = id_to_mcbsp_ptr(id);
435 st_data = mcbsp->st_data;
436
437 if (!st_data)
438 return -ENOENT;
439
440 spin_lock_irq(&mcbsp->lock);
441 if (channel == 0)
442 *chgain = st_data->ch0gain;
443 else if (channel == 1)
444 *chgain = st_data->ch1gain;
445 else
446 ret = -EINVAL;
447 spin_unlock_irq(&mcbsp->lock);
448
449 return ret;
450 }
451 EXPORT_SYMBOL(omap_st_get_chgain);
452
453 static int omap_st_start(struct omap_mcbsp *mcbsp)
454 {
455 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
456
457 if (st_data && st_data->enabled && !st_data->running) {
458 omap_st_fir_write(mcbsp, st_data->taps);
459 omap_st_chgain(mcbsp);
460
461 if (!mcbsp->free) {
462 omap_st_on(mcbsp);
463 st_data->running = 1;
464 }
465 }
466
467 return 0;
468 }
469
470 int omap_st_enable(unsigned int id)
471 {
472 struct omap_mcbsp *mcbsp;
473 struct omap_mcbsp_st_data *st_data;
474
475 if (!omap_mcbsp_check_valid_id(id)) {
476 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
477 return -ENODEV;
478 }
479
480 mcbsp = id_to_mcbsp_ptr(id);
481 st_data = mcbsp->st_data;
482
483 if (!st_data)
484 return -ENODEV;
485
486 spin_lock_irq(&mcbsp->lock);
487 st_data->enabled = 1;
488 omap_st_start(mcbsp);
489 spin_unlock_irq(&mcbsp->lock);
490
491 return 0;
492 }
493 EXPORT_SYMBOL(omap_st_enable);
494
495 static int omap_st_stop(struct omap_mcbsp *mcbsp)
496 {
497 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
498
499 if (st_data && st_data->running) {
500 if (!mcbsp->free) {
501 omap_st_off(mcbsp);
502 st_data->running = 0;
503 }
504 }
505
506 return 0;
507 }
508
509 int omap_st_disable(unsigned int id)
510 {
511 struct omap_mcbsp *mcbsp;
512 struct omap_mcbsp_st_data *st_data;
513 int ret = 0;
514
515 if (!omap_mcbsp_check_valid_id(id)) {
516 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
517 return -ENODEV;
518 }
519
520 mcbsp = id_to_mcbsp_ptr(id);
521 st_data = mcbsp->st_data;
522
523 if (!st_data)
524 return -ENODEV;
525
526 spin_lock_irq(&mcbsp->lock);
527 omap_st_stop(mcbsp);
528 st_data->enabled = 0;
529 spin_unlock_irq(&mcbsp->lock);
530
531 return ret;
532 }
533 EXPORT_SYMBOL(omap_st_disable);
534
535 int omap_st_is_enabled(unsigned int id)
536 {
537 struct omap_mcbsp *mcbsp;
538 struct omap_mcbsp_st_data *st_data;
539
540 if (!omap_mcbsp_check_valid_id(id)) {
541 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
542 return -ENODEV;
543 }
544
545 mcbsp = id_to_mcbsp_ptr(id);
546 st_data = mcbsp->st_data;
547
548 if (!st_data)
549 return -ENODEV;
550
551
552 return st_data->enabled;
553 }
554 EXPORT_SYMBOL(omap_st_is_enabled);
555 #else
556 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
557 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
558 #endif
559
560 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
561 /*
562 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
563 * The threshold parameter is 1 based, and it is converted (threshold - 1)
564 * for the THRSH2 register.
565 */
566 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
567 {
568 struct omap_mcbsp *mcbsp;
569
570 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
571 return;
572
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
575 return;
576 }
577 mcbsp = id_to_mcbsp_ptr(id);
578
579 if (threshold && threshold <= mcbsp->max_tx_thres)
580 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
581 }
582 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
583
584 /*
585 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
586 * The threshold parameter is 1 based, and it is converted (threshold - 1)
587 * for the THRSH1 register.
588 */
589 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
590 {
591 struct omap_mcbsp *mcbsp;
592
593 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
594 return;
595
596 if (!omap_mcbsp_check_valid_id(id)) {
597 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
598 return;
599 }
600 mcbsp = id_to_mcbsp_ptr(id);
601
602 if (threshold && threshold <= mcbsp->max_rx_thres)
603 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
604 }
605 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
606
607 /*
608 * omap_mcbsp_get_max_tx_thres just return the current configured
609 * maximum threshold for transmission
610 */
611 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
612 {
613 struct omap_mcbsp *mcbsp;
614
615 if (!omap_mcbsp_check_valid_id(id)) {
616 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
617 return -ENODEV;
618 }
619 mcbsp = id_to_mcbsp_ptr(id);
620
621 return mcbsp->max_tx_thres;
622 }
623 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
624
625 /*
626 * omap_mcbsp_get_max_rx_thres just return the current configured
627 * maximum threshold for reception
628 */
629 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
630 {
631 struct omap_mcbsp *mcbsp;
632
633 if (!omap_mcbsp_check_valid_id(id)) {
634 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
635 return -ENODEV;
636 }
637 mcbsp = id_to_mcbsp_ptr(id);
638
639 return mcbsp->max_rx_thres;
640 }
641 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
642
643 u16 omap_mcbsp_get_fifo_size(unsigned int id)
644 {
645 struct omap_mcbsp *mcbsp;
646
647 if (!omap_mcbsp_check_valid_id(id)) {
648 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
649 return -ENODEV;
650 }
651 mcbsp = id_to_mcbsp_ptr(id);
652
653 return mcbsp->pdata->buffer_size;
654 }
655 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
656
657 /*
658 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
659 */
660 u16 omap_mcbsp_get_tx_delay(unsigned int id)
661 {
662 struct omap_mcbsp *mcbsp;
663 u16 buffstat;
664
665 if (!omap_mcbsp_check_valid_id(id)) {
666 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
667 return -ENODEV;
668 }
669 mcbsp = id_to_mcbsp_ptr(id);
670
671 /* Returns the number of free locations in the buffer */
672 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
673
674 /* Number of slots are different in McBSP ports */
675 return mcbsp->pdata->buffer_size - buffstat;
676 }
677 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
678
679 /*
680 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
681 * to reach the threshold value (when the DMA will be triggered to read it)
682 */
683 u16 omap_mcbsp_get_rx_delay(unsigned int id)
684 {
685 struct omap_mcbsp *mcbsp;
686 u16 buffstat, threshold;
687
688 if (!omap_mcbsp_check_valid_id(id)) {
689 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
690 return -ENODEV;
691 }
692 mcbsp = id_to_mcbsp_ptr(id);
693
694 /* Returns the number of used locations in the buffer */
695 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
696 /* RX threshold */
697 threshold = MCBSP_READ(mcbsp, THRSH1);
698
699 /* Return the number of location till we reach the threshold limit */
700 if (threshold <= buffstat)
701 return 0;
702 else
703 return threshold - buffstat;
704 }
705 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
706
707 /*
708 * omap_mcbsp_get_dma_op_mode just return the current configured
709 * operating mode for the mcbsp channel
710 */
711 int omap_mcbsp_get_dma_op_mode(unsigned int id)
712 {
713 struct omap_mcbsp *mcbsp;
714 int dma_op_mode;
715
716 if (!omap_mcbsp_check_valid_id(id)) {
717 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
718 return -ENODEV;
719 }
720 mcbsp = id_to_mcbsp_ptr(id);
721
722 dma_op_mode = mcbsp->dma_op_mode;
723
724 return dma_op_mode;
725 }
726 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
727
728 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
729 {
730 struct omap_device *od;
731
732 od = find_omap_device_by_dev(mcbsp->dev);
733 /*
734 * Enable wakup behavior, smart idle and all wakeups
735 * REVISIT: some wakeups may be unnecessary
736 */
737 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
738 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
739 }
740 }
741
742 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
743 {
744 struct omap_device *od;
745
746 od = find_omap_device_by_dev(mcbsp->dev);
747
748 /*
749 * Disable wakup behavior, smart idle and all wakeups
750 */
751 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
752 /*
753 * HW bug workaround - If no_idle mode is taken, we need to
754 * go to smart_idle before going to always_idle, or the
755 * device will not hit retention anymore.
756 */
757
758 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
759 }
760 }
761 #else
762 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
763 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
764 #endif
765
766 /*
767 * We can choose between IRQ based or polled IO.
768 * This needs to be called before omap_mcbsp_request().
769 */
770 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
771 {
772 struct omap_mcbsp *mcbsp;
773
774 if (!omap_mcbsp_check_valid_id(id)) {
775 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
776 return -ENODEV;
777 }
778 mcbsp = id_to_mcbsp_ptr(id);
779
780 spin_lock(&mcbsp->lock);
781
782 if (!mcbsp->free) {
783 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
784 mcbsp->id);
785 spin_unlock(&mcbsp->lock);
786 return -EINVAL;
787 }
788
789 mcbsp->io_type = io_type;
790
791 spin_unlock(&mcbsp->lock);
792
793 return 0;
794 }
795 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
796
797 int omap_mcbsp_request(unsigned int id)
798 {
799 struct omap_mcbsp *mcbsp;
800 void *reg_cache;
801 int err;
802
803 if (!omap_mcbsp_check_valid_id(id)) {
804 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
805 return -ENODEV;
806 }
807 mcbsp = id_to_mcbsp_ptr(id);
808
809 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
810 if (!reg_cache) {
811 return -ENOMEM;
812 }
813
814 spin_lock(&mcbsp->lock);
815 if (!mcbsp->free) {
816 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
817 mcbsp->id);
818 err = -EBUSY;
819 goto err_kfree;
820 }
821
822 mcbsp->free = false;
823 mcbsp->reg_cache = reg_cache;
824 spin_unlock(&mcbsp->lock);
825
826 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
827 mcbsp->pdata->ops->request(id);
828
829 pm_runtime_get_sync(mcbsp->dev);
830
831 /* Do procedure specific to omap34xx arch, if applicable */
832 omap34xx_mcbsp_request(mcbsp);
833
834 /*
835 * Make sure that transmitter, receiver and sample-rate generator are
836 * not running before activating IRQs.
837 */
838 MCBSP_WRITE(mcbsp, SPCR1, 0);
839 MCBSP_WRITE(mcbsp, SPCR2, 0);
840
841 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
842 /* We need to get IRQs here */
843 init_completion(&mcbsp->tx_irq_completion);
844 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
845 0, "McBSP", (void *)mcbsp);
846 if (err != 0) {
847 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
848 "for McBSP%d\n", mcbsp->tx_irq,
849 mcbsp->id);
850 goto err_clk_disable;
851 }
852
853 if (mcbsp->rx_irq) {
854 init_completion(&mcbsp->rx_irq_completion);
855 err = request_irq(mcbsp->rx_irq,
856 omap_mcbsp_rx_irq_handler,
857 0, "McBSP", (void *)mcbsp);
858 if (err != 0) {
859 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
860 "for McBSP%d\n", mcbsp->rx_irq,
861 mcbsp->id);
862 goto err_free_irq;
863 }
864 }
865 }
866
867 return 0;
868 err_free_irq:
869 free_irq(mcbsp->tx_irq, (void *)mcbsp);
870 err_clk_disable:
871 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
872 mcbsp->pdata->ops->free(id);
873
874 /* Do procedure specific to omap34xx arch, if applicable */
875 omap34xx_mcbsp_free(mcbsp);
876
877 pm_runtime_put_sync(mcbsp->dev);
878
879 spin_lock(&mcbsp->lock);
880 mcbsp->free = true;
881 mcbsp->reg_cache = NULL;
882 err_kfree:
883 spin_unlock(&mcbsp->lock);
884 kfree(reg_cache);
885
886 return err;
887 }
888 EXPORT_SYMBOL(omap_mcbsp_request);
889
890 void omap_mcbsp_free(unsigned int id)
891 {
892 struct omap_mcbsp *mcbsp;
893 void *reg_cache;
894
895 if (!omap_mcbsp_check_valid_id(id)) {
896 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
897 return;
898 }
899 mcbsp = id_to_mcbsp_ptr(id);
900
901 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
902 mcbsp->pdata->ops->free(id);
903
904 /* Do procedure specific to omap34xx arch, if applicable */
905 omap34xx_mcbsp_free(mcbsp);
906
907 pm_runtime_put_sync(mcbsp->dev);
908
909 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
910 /* Free IRQs */
911 if (mcbsp->rx_irq)
912 free_irq(mcbsp->rx_irq, (void *)mcbsp);
913 free_irq(mcbsp->tx_irq, (void *)mcbsp);
914 }
915
916 reg_cache = mcbsp->reg_cache;
917
918 spin_lock(&mcbsp->lock);
919 if (mcbsp->free)
920 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
921 else
922 mcbsp->free = true;
923 mcbsp->reg_cache = NULL;
924 spin_unlock(&mcbsp->lock);
925
926 if (reg_cache)
927 kfree(reg_cache);
928 }
929 EXPORT_SYMBOL(omap_mcbsp_free);
930
931 /*
932 * Here we start the McBSP, by enabling transmitter, receiver or both.
933 * If no transmitter or receiver is active prior calling, then sample-rate
934 * generator and frame sync are started.
935 */
936 void omap_mcbsp_start(unsigned int id, int tx, int rx)
937 {
938 struct omap_mcbsp *mcbsp;
939 int enable_srg = 0;
940 u16 w;
941
942 if (!omap_mcbsp_check_valid_id(id)) {
943 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
944 return;
945 }
946 mcbsp = id_to_mcbsp_ptr(id);
947
948 if (cpu_is_omap34xx())
949 omap_st_start(mcbsp);
950
951 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
952 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
953
954 /* Only enable SRG, if McBSP is master */
955 w = MCBSP_READ_CACHE(mcbsp, PCR0);
956 if (w & (FSXM | FSRM | CLKXM | CLKRM))
957 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
958 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
959
960 if (enable_srg) {
961 /* Start the sample generator */
962 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
963 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
964 }
965
966 /* Enable transmitter and receiver */
967 tx &= 1;
968 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
969 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
970
971 rx &= 1;
972 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
973 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
974
975 /*
976 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
977 * REVISIT: 100us may give enough time for two CLKSRG, however
978 * due to some unknown PM related, clock gating etc. reason it
979 * is now at 500us.
980 */
981 udelay(500);
982
983 if (enable_srg) {
984 /* Start frame sync */
985 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
986 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
987 }
988
989 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
990 /* Release the transmitter and receiver */
991 w = MCBSP_READ_CACHE(mcbsp, XCCR);
992 w &= ~(tx ? XDISABLE : 0);
993 MCBSP_WRITE(mcbsp, XCCR, w);
994 w = MCBSP_READ_CACHE(mcbsp, RCCR);
995 w &= ~(rx ? RDISABLE : 0);
996 MCBSP_WRITE(mcbsp, RCCR, w);
997 }
998
999 /*Disable and Re-enable transmitter if ready */
1000 if (tx && (MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1001 MCBSP_WRITE(mcbsp, SPCR2,
1002 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1003 (~XRST));
1004 MCBSP_WRITE(mcbsp, SPCR2,
1005 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1006 (XRST));
1007 }
1008 /*Disable and Re-enable receiver if ready */
1009 if (rx && (MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1010 MCBSP_WRITE(mcbsp, SPCR1,
1011 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1012 (~RRST));
1013 MCBSP_WRITE(mcbsp, SPCR1,
1014 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1015 (RRST));
1016 }
1017
1018 /* Dump McBSP Regs */
1019 omap_mcbsp_dump_reg(id);
1020 }
1021 EXPORT_SYMBOL(omap_mcbsp_start);
1022
1023 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
1024 {
1025 struct omap_mcbsp *mcbsp;
1026 int idle;
1027 u16 w;
1028
1029 if (!omap_mcbsp_check_valid_id(id)) {
1030 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1031 return;
1032 }
1033
1034 mcbsp = id_to_mcbsp_ptr(id);
1035
1036 /* Reset transmitter */
1037 tx &= 1;
1038 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
1039 w = MCBSP_READ_CACHE(mcbsp, XCCR);
1040 w |= (tx ? XDISABLE : 0);
1041 MCBSP_WRITE(mcbsp, XCCR, w);
1042 }
1043 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
1044 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
1045
1046 /* Reset receiver */
1047 rx &= 1;
1048 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
1049 w = MCBSP_READ_CACHE(mcbsp, RCCR);
1050 w |= (rx ? RDISABLE : 0);
1051 MCBSP_WRITE(mcbsp, RCCR, w);
1052 }
1053 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
1054 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
1055
1056 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
1057 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
1058
1059 if (idle) {
1060 /* Reset the sample rate generator */
1061 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
1062 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
1063 }
1064
1065 if (cpu_is_omap34xx())
1066 omap_st_stop(mcbsp);
1067 }
1068 EXPORT_SYMBOL(omap_mcbsp_stop);
1069
1070 /* polled mcbsp i/o operations */
1071 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
1072 {
1073 struct omap_mcbsp *mcbsp;
1074
1075 if (!omap_mcbsp_check_valid_id(id)) {
1076 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1077 return -ENODEV;
1078 }
1079
1080 mcbsp = id_to_mcbsp_ptr(id);
1081
1082 MCBSP_WRITE(mcbsp, DXR1, buf);
1083 /* if frame sync error - clear the error */
1084 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1085 /* clear error */
1086 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1087 /* resend */
1088 return -1;
1089 } else {
1090 /* wait for transmit confirmation */
1091 int attemps = 0;
1092 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1093 if (attemps++ > 1000) {
1094 MCBSP_WRITE(mcbsp, SPCR2,
1095 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1096 (~XRST));
1097 udelay(10);
1098 MCBSP_WRITE(mcbsp, SPCR2,
1099 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1100 (XRST));
1101 udelay(10);
1102 dev_err(mcbsp->dev, "Could not write to"
1103 " McBSP%d Register\n", mcbsp->id);
1104 return -2;
1105 }
1106 }
1107 }
1108
1109 return 0;
1110 }
1111 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1112
1113 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1114 {
1115 struct omap_mcbsp *mcbsp;
1116
1117 if (!omap_mcbsp_check_valid_id(id)) {
1118 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1119 return -ENODEV;
1120 }
1121 mcbsp = id_to_mcbsp_ptr(id);
1122
1123 /* if frame sync error - clear the error */
1124 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1125 /* clear error */
1126 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1127 /* resend */
1128 return -1;
1129 } else {
1130 /* wait for receive confirmation */
1131 int attemps = 0;
1132 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1133 if (attemps++ > 1000) {
1134 MCBSP_WRITE(mcbsp, SPCR1,
1135 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1136 (~RRST));
1137 udelay(10);
1138 MCBSP_WRITE(mcbsp, SPCR1,
1139 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1140 (RRST));
1141 udelay(10);
1142 dev_err(mcbsp->dev, "Could not read from"
1143 " McBSP%d Register\n", mcbsp->id);
1144 return -2;
1145 }
1146 }
1147 }
1148 *buf = MCBSP_READ(mcbsp, DRR1);
1149
1150 return 0;
1151 }
1152 EXPORT_SYMBOL(omap_mcbsp_pollread);
1153
1154 /*
1155 * IRQ based word transmission.
1156 */
1157 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1158 {
1159 struct omap_mcbsp *mcbsp;
1160 omap_mcbsp_word_length word_length;
1161
1162 if (!omap_mcbsp_check_valid_id(id)) {
1163 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1164 return;
1165 }
1166
1167 mcbsp = id_to_mcbsp_ptr(id);
1168 word_length = mcbsp->tx_word_length;
1169
1170 wait_for_completion(&mcbsp->tx_irq_completion);
1171
1172 if (word_length > OMAP_MCBSP_WORD_16)
1173 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1174 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1175 }
1176 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1177
1178 u32 omap_mcbsp_recv_word(unsigned int id)
1179 {
1180 struct omap_mcbsp *mcbsp;
1181 u16 word_lsb, word_msb = 0;
1182 omap_mcbsp_word_length word_length;
1183
1184 if (!omap_mcbsp_check_valid_id(id)) {
1185 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1186 return -ENODEV;
1187 }
1188 mcbsp = id_to_mcbsp_ptr(id);
1189
1190 word_length = mcbsp->rx_word_length;
1191
1192 wait_for_completion(&mcbsp->rx_irq_completion);
1193
1194 if (word_length > OMAP_MCBSP_WORD_16)
1195 word_msb = MCBSP_READ(mcbsp, DRR2);
1196 word_lsb = MCBSP_READ(mcbsp, DRR1);
1197
1198 return (word_lsb | (word_msb << 16));
1199 }
1200 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1201
1202 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1203 {
1204 struct omap_mcbsp *mcbsp;
1205 omap_mcbsp_word_length tx_word_length;
1206 omap_mcbsp_word_length rx_word_length;
1207 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1208
1209 if (!omap_mcbsp_check_valid_id(id)) {
1210 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1211 return -ENODEV;
1212 }
1213 mcbsp = id_to_mcbsp_ptr(id);
1214 tx_word_length = mcbsp->tx_word_length;
1215 rx_word_length = mcbsp->rx_word_length;
1216
1217 if (tx_word_length != rx_word_length)
1218 return -EINVAL;
1219
1220 /* First we wait for the transmitter to be ready */
1221 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1222 while (!(spcr2 & XRDY)) {
1223 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1224 if (attempts++ > 1000) {
1225 /* We must reset the transmitter */
1226 MCBSP_WRITE(mcbsp, SPCR2,
1227 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1228 udelay(10);
1229 MCBSP_WRITE(mcbsp, SPCR2,
1230 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1231 udelay(10);
1232 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1233 "ready\n", mcbsp->id);
1234 return -EAGAIN;
1235 }
1236 }
1237
1238 /* Now we can push the data */
1239 if (tx_word_length > OMAP_MCBSP_WORD_16)
1240 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1241 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1242
1243 /* We wait for the receiver to be ready */
1244 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1245 while (!(spcr1 & RRDY)) {
1246 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1247 if (attempts++ > 1000) {
1248 /* We must reset the receiver */
1249 MCBSP_WRITE(mcbsp, SPCR1,
1250 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1251 udelay(10);
1252 MCBSP_WRITE(mcbsp, SPCR1,
1253 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1254 udelay(10);
1255 dev_err(mcbsp->dev, "McBSP%d receiver not "
1256 "ready\n", mcbsp->id);
1257 return -EAGAIN;
1258 }
1259 }
1260
1261 /* Receiver is ready, let's read the dummy data */
1262 if (rx_word_length > OMAP_MCBSP_WORD_16)
1263 word_msb = MCBSP_READ(mcbsp, DRR2);
1264 word_lsb = MCBSP_READ(mcbsp, DRR1);
1265
1266 return 0;
1267 }
1268 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1269
1270 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1271 {
1272 struct omap_mcbsp *mcbsp;
1273 u32 clock_word = 0;
1274 omap_mcbsp_word_length tx_word_length;
1275 omap_mcbsp_word_length rx_word_length;
1276 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1277
1278 if (!omap_mcbsp_check_valid_id(id)) {
1279 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1280 return -ENODEV;
1281 }
1282
1283 mcbsp = id_to_mcbsp_ptr(id);
1284
1285 tx_word_length = mcbsp->tx_word_length;
1286 rx_word_length = mcbsp->rx_word_length;
1287
1288 if (tx_word_length != rx_word_length)
1289 return -EINVAL;
1290
1291 /* First we wait for the transmitter to be ready */
1292 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1293 while (!(spcr2 & XRDY)) {
1294 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1295 if (attempts++ > 1000) {
1296 /* We must reset the transmitter */
1297 MCBSP_WRITE(mcbsp, SPCR2,
1298 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1299 udelay(10);
1300 MCBSP_WRITE(mcbsp, SPCR2,
1301 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1302 udelay(10);
1303 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1304 "ready\n", mcbsp->id);
1305 return -EAGAIN;
1306 }
1307 }
1308
1309 /* We first need to enable the bus clock */
1310 if (tx_word_length > OMAP_MCBSP_WORD_16)
1311 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1312 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1313
1314 /* We wait for the receiver to be ready */
1315 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1316 while (!(spcr1 & RRDY)) {
1317 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1318 if (attempts++ > 1000) {
1319 /* We must reset the receiver */
1320 MCBSP_WRITE(mcbsp, SPCR1,
1321 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1322 udelay(10);
1323 MCBSP_WRITE(mcbsp, SPCR1,
1324 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1325 udelay(10);
1326 dev_err(mcbsp->dev, "McBSP%d receiver not "
1327 "ready\n", mcbsp->id);
1328 return -EAGAIN;
1329 }
1330 }
1331
1332 /* Receiver is ready, there is something for us */
1333 if (rx_word_length > OMAP_MCBSP_WORD_16)
1334 word_msb = MCBSP_READ(mcbsp, DRR2);
1335 word_lsb = MCBSP_READ(mcbsp, DRR1);
1336
1337 word[0] = (word_lsb | (word_msb << 16));
1338
1339 return 0;
1340 }
1341 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1342
1343 /*
1344 * Simple DMA based buffer rx/tx routines.
1345 * Nothing fancy, just a single buffer tx/rx through DMA.
1346 * The DMA resources are released once the transfer is done.
1347 * For anything fancier, you should use your own customized DMA
1348 * routines and callbacks.
1349 */
1350 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1351 unsigned int length)
1352 {
1353 struct omap_mcbsp *mcbsp;
1354 int dma_tx_ch;
1355 int src_port = 0;
1356 int dest_port = 0;
1357 int sync_dev = 0;
1358
1359 if (!omap_mcbsp_check_valid_id(id)) {
1360 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1361 return -ENODEV;
1362 }
1363 mcbsp = id_to_mcbsp_ptr(id);
1364
1365 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1366 omap_mcbsp_tx_dma_callback,
1367 mcbsp,
1368 &dma_tx_ch)) {
1369 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1370 "McBSP%d TX. Trying IRQ based TX\n",
1371 mcbsp->id);
1372 return -EAGAIN;
1373 }
1374 mcbsp->dma_tx_lch = dma_tx_ch;
1375
1376 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1377 dma_tx_ch);
1378
1379 init_completion(&mcbsp->tx_dma_completion);
1380
1381 if (cpu_class_is_omap1()) {
1382 src_port = OMAP_DMA_PORT_TIPB;
1383 dest_port = OMAP_DMA_PORT_EMIFF;
1384 }
1385 if (cpu_class_is_omap2())
1386 sync_dev = mcbsp->dma_tx_sync;
1387
1388 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1389 OMAP_DMA_DATA_TYPE_S16,
1390 length >> 1, 1,
1391 OMAP_DMA_SYNC_ELEMENT,
1392 sync_dev, 0);
1393
1394 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1395 src_port,
1396 OMAP_DMA_AMODE_CONSTANT,
1397 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1398 0, 0);
1399
1400 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1401 dest_port,
1402 OMAP_DMA_AMODE_POST_INC,
1403 buffer,
1404 0, 0);
1405
1406 omap_start_dma(mcbsp->dma_tx_lch);
1407 wait_for_completion(&mcbsp->tx_dma_completion);
1408
1409 return 0;
1410 }
1411 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1412
1413 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1414 unsigned int length)
1415 {
1416 struct omap_mcbsp *mcbsp;
1417 int dma_rx_ch;
1418 int src_port = 0;
1419 int dest_port = 0;
1420 int sync_dev = 0;
1421
1422 if (!omap_mcbsp_check_valid_id(id)) {
1423 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1424 return -ENODEV;
1425 }
1426 mcbsp = id_to_mcbsp_ptr(id);
1427
1428 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1429 omap_mcbsp_rx_dma_callback,
1430 mcbsp,
1431 &dma_rx_ch)) {
1432 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1433 "McBSP%d RX. Trying IRQ based RX\n",
1434 mcbsp->id);
1435 return -EAGAIN;
1436 }
1437 mcbsp->dma_rx_lch = dma_rx_ch;
1438
1439 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1440 dma_rx_ch);
1441
1442 init_completion(&mcbsp->rx_dma_completion);
1443
1444 if (cpu_class_is_omap1()) {
1445 src_port = OMAP_DMA_PORT_TIPB;
1446 dest_port = OMAP_DMA_PORT_EMIFF;
1447 }
1448 if (cpu_class_is_omap2())
1449 sync_dev = mcbsp->dma_rx_sync;
1450
1451 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1452 OMAP_DMA_DATA_TYPE_S16,
1453 length >> 1, 1,
1454 OMAP_DMA_SYNC_ELEMENT,
1455 sync_dev, 0);
1456
1457 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1458 src_port,
1459 OMAP_DMA_AMODE_CONSTANT,
1460 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1461 0, 0);
1462
1463 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1464 dest_port,
1465 OMAP_DMA_AMODE_POST_INC,
1466 buffer,
1467 0, 0);
1468
1469 omap_start_dma(mcbsp->dma_rx_lch);
1470 wait_for_completion(&mcbsp->rx_dma_completion);
1471
1472 return 0;
1473 }
1474 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1475
1476 /*
1477 * SPI wrapper.
1478 * Since SPI setup is much simpler than the generic McBSP one,
1479 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1480 * Once this is done, you can call omap_mcbsp_start().
1481 */
1482 void omap_mcbsp_set_spi_mode(unsigned int id,
1483 const struct omap_mcbsp_spi_cfg *spi_cfg)
1484 {
1485 struct omap_mcbsp *mcbsp;
1486 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1487
1488 if (!omap_mcbsp_check_valid_id(id)) {
1489 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1490 return;
1491 }
1492 mcbsp = id_to_mcbsp_ptr(id);
1493
1494 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1495
1496 /* SPI has only one frame */
1497 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1498 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1499
1500 /* Clock stop mode */
1501 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1502 mcbsp_cfg.spcr1 |= (1 << 12);
1503 else
1504 mcbsp_cfg.spcr1 |= (3 << 11);
1505
1506 /* Set clock parities */
1507 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1508 mcbsp_cfg.pcr0 |= CLKRP;
1509 else
1510 mcbsp_cfg.pcr0 &= ~CLKRP;
1511
1512 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1513 mcbsp_cfg.pcr0 &= ~CLKXP;
1514 else
1515 mcbsp_cfg.pcr0 |= CLKXP;
1516
1517 /* Set SCLKME to 0 and CLKSM to 1 */
1518 mcbsp_cfg.pcr0 &= ~SCLKME;
1519 mcbsp_cfg.srgr2 |= CLKSM;
1520
1521 /* Set FSXP */
1522 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1523 mcbsp_cfg.pcr0 &= ~FSXP;
1524 else
1525 mcbsp_cfg.pcr0 |= FSXP;
1526
1527 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1528 mcbsp_cfg.pcr0 |= CLKXM;
1529 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1530 mcbsp_cfg.pcr0 |= FSXM;
1531 mcbsp_cfg.srgr2 &= ~FSGM;
1532 mcbsp_cfg.xcr2 |= XDATDLY(1);
1533 mcbsp_cfg.rcr2 |= RDATDLY(1);
1534 } else {
1535 mcbsp_cfg.pcr0 &= ~CLKXM;
1536 mcbsp_cfg.srgr1 |= CLKGDV(1);
1537 mcbsp_cfg.pcr0 &= ~FSXM;
1538 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1539 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1540 }
1541
1542 mcbsp_cfg.xcr2 &= ~XPHASE;
1543 mcbsp_cfg.rcr2 &= ~RPHASE;
1544
1545 omap_mcbsp_config(id, &mcbsp_cfg);
1546 }
1547 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1548
1549 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1550 #define max_thres(m) (mcbsp->pdata->buffer_size)
1551 #define valid_threshold(m, val) ((val) <= max_thres(m))
1552 #define THRESHOLD_PROP_BUILDER(prop) \
1553 static ssize_t prop##_show(struct device *dev, \
1554 struct device_attribute *attr, char *buf) \
1555 { \
1556 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1557 \
1558 return sprintf(buf, "%u\n", mcbsp->prop); \
1559 } \
1560 \
1561 static ssize_t prop##_store(struct device *dev, \
1562 struct device_attribute *attr, \
1563 const char *buf, size_t size) \
1564 { \
1565 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1566 unsigned long val; \
1567 int status; \
1568 \
1569 status = strict_strtoul(buf, 0, &val); \
1570 if (status) \
1571 return status; \
1572 \
1573 if (!valid_threshold(mcbsp, val)) \
1574 return -EDOM; \
1575 \
1576 mcbsp->prop = val; \
1577 return size; \
1578 } \
1579 \
1580 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1581
1582 THRESHOLD_PROP_BUILDER(max_tx_thres);
1583 THRESHOLD_PROP_BUILDER(max_rx_thres);
1584
1585 static const char *dma_op_modes[] = {
1586 "element", "threshold", "frame",
1587 };
1588
1589 static ssize_t dma_op_mode_show(struct device *dev,
1590 struct device_attribute *attr, char *buf)
1591 {
1592 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1593 int dma_op_mode, i = 0;
1594 ssize_t len = 0;
1595 const char * const *s;
1596
1597 dma_op_mode = mcbsp->dma_op_mode;
1598
1599 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1600 if (dma_op_mode == i)
1601 len += sprintf(buf + len, "[%s] ", *s);
1602 else
1603 len += sprintf(buf + len, "%s ", *s);
1604 }
1605 len += sprintf(buf + len, "\n");
1606
1607 return len;
1608 }
1609
1610 static ssize_t dma_op_mode_store(struct device *dev,
1611 struct device_attribute *attr,
1612 const char *buf, size_t size)
1613 {
1614 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1615 const char * const *s;
1616 int i = 0;
1617
1618 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1619 if (sysfs_streq(buf, *s))
1620 break;
1621
1622 if (i == ARRAY_SIZE(dma_op_modes))
1623 return -EINVAL;
1624
1625 spin_lock_irq(&mcbsp->lock);
1626 if (!mcbsp->free) {
1627 size = -EBUSY;
1628 goto unlock;
1629 }
1630 mcbsp->dma_op_mode = i;
1631
1632 unlock:
1633 spin_unlock_irq(&mcbsp->lock);
1634
1635 return size;
1636 }
1637
1638 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1639
1640 static const struct attribute *additional_attrs[] = {
1641 &dev_attr_max_tx_thres.attr,
1642 &dev_attr_max_rx_thres.attr,
1643 &dev_attr_dma_op_mode.attr,
1644 NULL,
1645 };
1646
1647 static const struct attribute_group additional_attr_group = {
1648 .attrs = (struct attribute **)additional_attrs,
1649 };
1650
1651 static inline int __devinit omap_additional_add(struct device *dev)
1652 {
1653 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1654 }
1655
1656 static inline void __devexit omap_additional_remove(struct device *dev)
1657 {
1658 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1659 }
1660 #endif
1661
1662 #ifdef CONFIG_ARCH_OMAP3
1663 static ssize_t st_taps_show(struct device *dev,
1664 struct device_attribute *attr, char *buf)
1665 {
1666 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1667 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1668 ssize_t status = 0;
1669 int i;
1670
1671 spin_lock_irq(&mcbsp->lock);
1672 for (i = 0; i < st_data->nr_taps; i++)
1673 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1674 st_data->taps[i]);
1675 if (i)
1676 status += sprintf(&buf[status], "\n");
1677 spin_unlock_irq(&mcbsp->lock);
1678
1679 return status;
1680 }
1681
1682 static ssize_t st_taps_store(struct device *dev,
1683 struct device_attribute *attr,
1684 const char *buf, size_t size)
1685 {
1686 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1687 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1688 int val, tmp, status, i = 0;
1689
1690 spin_lock_irq(&mcbsp->lock);
1691 memset(st_data->taps, 0, sizeof(st_data->taps));
1692 st_data->nr_taps = 0;
1693
1694 do {
1695 status = sscanf(buf, "%d%n", &val, &tmp);
1696 if (status < 0 || status == 0) {
1697 size = -EINVAL;
1698 goto out;
1699 }
1700 if (val < -32768 || val > 32767) {
1701 size = -EINVAL;
1702 goto out;
1703 }
1704 st_data->taps[i++] = val;
1705 buf += tmp;
1706 if (*buf != ',')
1707 break;
1708 buf++;
1709 } while (1);
1710
1711 st_data->nr_taps = i;
1712
1713 out:
1714 spin_unlock_irq(&mcbsp->lock);
1715
1716 return size;
1717 }
1718
1719 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1720
1721 static const struct attribute *sidetone_attrs[] = {
1722 &dev_attr_st_taps.attr,
1723 NULL,
1724 };
1725
1726 static const struct attribute_group sidetone_attr_group = {
1727 .attrs = (struct attribute **)sidetone_attrs,
1728 };
1729
1730 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1731 {
1732 struct platform_device *pdev;
1733 struct resource *res;
1734 struct omap_mcbsp_st_data *st_data;
1735 int err;
1736
1737 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1738 if (!st_data) {
1739 err = -ENOMEM;
1740 goto err1;
1741 }
1742
1743 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1744
1745 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1746 st_data->io_base_st = ioremap(res->start, resource_size(res));
1747 if (!st_data->io_base_st) {
1748 err = -ENOMEM;
1749 goto err2;
1750 }
1751
1752 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1753 if (err)
1754 goto err3;
1755
1756 mcbsp->st_data = st_data;
1757 return 0;
1758
1759 err3:
1760 iounmap(st_data->io_base_st);
1761 err2:
1762 kfree(st_data);
1763 err1:
1764 return err;
1765
1766 }
1767
1768 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1769 {
1770 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1771
1772 if (st_data) {
1773 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1774 iounmap(st_data->io_base_st);
1775 kfree(st_data);
1776 }
1777 }
1778 #else
1779 static inline int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { return 0; }
1780 static inline void __devexit omap_st_remove(struct omap_mcbsp *mcbsp) {}
1781 #endif
1782
1783 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1784 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1785 {
1786 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1787 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1788 /*
1789 * Initially configure the maximum thresholds to a safe value.
1790 * The McBSP FIFO usage with these values should not go under
1791 * 16 locations.
1792 * If the whole FIFO without safety buffer is used, than there
1793 * is a possibility that the DMA will be not able to push the
1794 * new data on time, causing channel shifts in runtime.
1795 */
1796 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1797 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1798 /*
1799 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1800 * for mcbsp2 instances.
1801 */
1802 if (omap_additional_add(mcbsp->dev))
1803 dev_warn(mcbsp->dev,
1804 "Unable to create additional controls\n");
1805 } else {
1806 mcbsp->max_tx_thres = -EINVAL;
1807 mcbsp->max_rx_thres = -EINVAL;
1808 }
1809
1810 if (cpu_is_omap34xx()) {
1811 if (mcbsp->id == 2 || mcbsp->id == 3)
1812 if (omap_st_add(mcbsp))
1813 dev_warn(mcbsp->dev,
1814 "Unable to create sidetone controls\n");
1815 }
1816 }
1817
1818 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1819 {
1820 if (cpu_is_omap34xx() || cpu_is_omap44xx())
1821 omap_additional_remove(mcbsp->dev);
1822 if (cpu_is_omap34xx())
1823 if (mcbsp->id == 2 || mcbsp->id == 3)
1824 omap_st_remove(mcbsp);
1825 }
1826 #else
1827 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1828 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1829 #endif /* CONFIG_ARCH_OMAP3 */
1830
1831 /*
1832 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1833 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1834 */
1835 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1836 {
1837 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1838 struct omap_mcbsp *mcbsp;
1839 int id = pdev->id - 1;
1840 struct resource *res;
1841 int ret = 0;
1842
1843 if (!pdata) {
1844 dev_err(&pdev->dev, "McBSP device initialized without"
1845 "platform data\n");
1846 ret = -EINVAL;
1847 goto exit;
1848 }
1849
1850 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1851
1852 if (id >= omap_mcbsp_count) {
1853 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1854 ret = -EINVAL;
1855 goto exit;
1856 }
1857
1858 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1859 if (!mcbsp) {
1860 ret = -ENOMEM;
1861 goto exit;
1862 }
1863
1864 spin_lock_init(&mcbsp->lock);
1865 mcbsp->id = id + 1;
1866 mcbsp->free = true;
1867 mcbsp->dma_tx_lch = -1;
1868 mcbsp->dma_rx_lch = -1;
1869
1870 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1871 if (!res) {
1872 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1873 if (!res) {
1874 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1875 "resource\n", __func__, pdev->id);
1876 ret = -ENOMEM;
1877 goto exit;
1878 }
1879 }
1880 mcbsp->phys_base = res->start;
1881 omap_mcbsp_cache_size = resource_size(res);
1882 mcbsp->io_base = ioremap(res->start, resource_size(res));
1883 if (!mcbsp->io_base) {
1884 ret = -ENOMEM;
1885 goto err_ioremap;
1886 }
1887
1888 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1889 if (!res)
1890 mcbsp->phys_dma_base = mcbsp->phys_base;
1891 else
1892 mcbsp->phys_dma_base = res->start;
1893
1894 /* Default I/O is IRQ based */
1895 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1896
1897 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1898 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1899
1900 /* From OMAP4 there will be a single irq line */
1901 if (mcbsp->tx_irq == -ENXIO)
1902 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1903
1904 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1905 if (!res) {
1906 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1907 __func__, pdev->id);
1908 ret = -ENODEV;
1909 goto err_res;
1910 }
1911 mcbsp->dma_rx_sync = res->start;
1912
1913 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1914 if (!res) {
1915 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1916 __func__, pdev->id);
1917 ret = -ENODEV;
1918 goto err_res;
1919 }
1920 mcbsp->dma_tx_sync = res->start;
1921
1922 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1923 if (IS_ERR(mcbsp->fclk)) {
1924 ret = PTR_ERR(mcbsp->fclk);
1925 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1926 goto err_res;
1927 }
1928
1929 mcbsp->pdata = pdata;
1930 mcbsp->dev = &pdev->dev;
1931 mcbsp_ptr[id] = mcbsp;
1932 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1933 platform_set_drvdata(pdev, mcbsp);
1934 pm_runtime_enable(mcbsp->dev);
1935
1936 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1937 omap34xx_device_init(mcbsp);
1938
1939 return 0;
1940
1941 err_res:
1942 iounmap(mcbsp->io_base);
1943 err_ioremap:
1944 kfree(mcbsp);
1945 exit:
1946 return ret;
1947 }
1948
1949 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1950 {
1951 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1952
1953 platform_set_drvdata(pdev, NULL);
1954 if (mcbsp) {
1955
1956 if (mcbsp->pdata && mcbsp->pdata->ops &&
1957 mcbsp->pdata->ops->free)
1958 mcbsp->pdata->ops->free(mcbsp->id);
1959
1960 omap34xx_device_exit(mcbsp);
1961
1962 clk_put(mcbsp->fclk);
1963
1964 iounmap(mcbsp->io_base);
1965 kfree(mcbsp);
1966 }
1967
1968 return 0;
1969 }
1970
1971 static struct platform_driver omap_mcbsp_driver = {
1972 .probe = omap_mcbsp_probe,
1973 .remove = __devexit_p(omap_mcbsp_remove),
1974 .driver = {
1975 .name = "omap-mcbsp",
1976 },
1977 };
1978
1979 int __init omap_mcbsp_init(void)
1980 {
1981 /* Register the McBSP driver */
1982 return platform_driver_register(&omap_mcbsp_driver);
1983 }