include/linux/mfd/twl6040-codec.h

   1 /*
   2  * MFD driver for twl6040 codec submodule
   3  *
   4  * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
   5  *              Misael Lopez Cruz <misael.lopez@ti.com>
   6  *
   7  * Copyright:   (C) 2011 Texas Instruments, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __TWL6040_CODEC_H__
  26 #define __TWL6040_CODEC_H__
  27
  28 #include <linux/interrupt.h>
  29 #include <linux/mfd/core.h>
  30
  31 #define TWL6040_NO_SUPPLY               0
  32 #define TWL6040_VIO_SUPPLY              1
  33 #define TWL6040_VDD_SUPPLY              2
  34
  35
  36 #define TWL6040_REG_ASICID              0x01
  37 #define TWL6040_REG_ASICREV             0x02
  38 #define TWL6040_REG_INTID               0x03
  39 #define TWL6040_REG_INTMR               0x04
  40 #define TWL6040_REG_NCPCTL              0x05
  41 #define TWL6040_REG_LDOCTL              0x06
  42 #define TWL6040_REG_HPPLLCTL            0x07
  43 #define TWL6040_REG_LPPLLCTL            0x08
  44 #define TWL6040_REG_LPPLLDIV            0x09
  45 #define TWL6040_REG_AMICBCTL            0x0A
  46 #define TWL6040_REG_DMICBCTL            0x0B
  47 #define TWL6040_REG_MICLCTL             0x0C
  48 #define TWL6040_REG_MICRCTL             0x0D
  49 #define TWL6040_REG_MICGAIN             0x0E
  50 #define TWL6040_REG_LINEGAIN            0x0F
  51 #define TWL6040_REG_HSLCTL              0x10
  52 #define TWL6040_REG_HSRCTL              0x11
  53 #define TWL6040_REG_HSGAIN              0x12
  54 #define TWL6040_REG_EARCTL              0x13
  55 #define TWL6040_REG_HFLCTL              0x14
  56 #define TWL6040_REG_HFLGAIN             0x15
  57 #define TWL6040_REG_HFRCTL              0x16
  58 #define TWL6040_REG_HFRGAIN             0x17
  59 #define TWL6040_REG_VIBCTLL             0x18
  60 #define TWL6040_REG_VIBDATL             0x19
  61 #define TWL6040_REG_VIBCTLR             0x1A
  62 #define TWL6040_REG_VIBDATR             0x1B
  63 #define TWL6040_REG_HKCTL1              0x1C
  64 #define TWL6040_REG_HKCTL2              0x1D
  65 #define TWL6040_REG_GPOCTL              0x1E
  66 #define TWL6040_REG_ALB                 0x1F
  67 #define TWL6040_REG_DLB                 0x20
  68 #define TWL6040_REG_TRIM1               0x28
  69 #define TWL6040_REG_TRIM2               0x29
  70 #define TWL6040_REG_TRIM3               0x2A
  71 #define TWL6040_REG_HSOTRIM             0x2B
  72 #define TWL6040_REG_HFOTRIM             0x2C
  73 #define TWL6040_REG_ACCCTL              0x2D
  74 #define TWL6040_REG_STATUS              0x2E
  75
  76 #define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
  77
  78 #define TWL6040_VIOREGNUM               18
  79 #define TWL6040_VDDREGNUM               21
  80
  81 /* ASICREV (0x02) values */
  82
  83 #define TWL6040_REV_1_0                 0x00
  84 #define TWL6040_REV_1_1                 0x01
  85 #define TWL6040_REV_1_3                 0x02
  86
  87 /* INTID (0x03) fields */
  88
  89 #define TWL6040_THINT                   0x01
  90 #define TWL6040_PLUGINT                 0x02
  91 #define TWL6040_UNPLUGINT               0x04
  92 #define TWL6040_HOOKINT                 0x08
  93 #define TWL6040_HFINT                   0x10
  94 #define TWL6040_VIBINT                  0x20
  95 #define TWL6040_READYINT                0x40
  96
  97 /* INTMR (0x04) fields */
  98
  99 #define TWL6040_THMSK                   0x01
 100 #define TWL6040_PLUGMSK                 0x02
 101 #define TWL6040_HOOKMSK                 0x08
 102 #define TWL6040_HFMSK                   0x10
 103 #define TWL6040_VIBMSK                  0x20
 104 #define TWL6040_READYMSK                0x40
 105 #define TWL6040_ALLINT_MSK              0x7B
 106
 107 /* NCPCTL (0x05) fields */
 108
 109 #define TWL6040_NCPENA                  0x01
 110 #define TWL6040_NCPOPEN                 0x40
 111 #define TWL6040_TSHUTENA                0x80
 112
 113 /* LDOCTL (0x06) fields */
 114
 115 #define TWL6040_LSLDOENA                0x01
 116 #define TWL6040_HSLDOENA                0x04
 117 #define TWL6040_REFENA                  0x40
 118 #define TWL6040_OSCENA                  0x80
 119
 120 /* HPPLLCTL (0x07) fields */
 121
 122 #define TWL6040_HPLLENA                 0x01
 123 #define TWL6040_HPLLRST                 0x02
 124 #define TWL6040_HPLLBP                  0x04
 125 #define TWL6040_HPLLSQRENA              0x08
 126 #define TWL6040_HPLLSQRBP               0x10
 127 #define TWL6040_MCLK_12000KHZ           (0 << 5)
 128 #define TWL6040_MCLK_19200KHZ           (1 << 5)
 129 #define TWL6040_MCLK_26000KHZ           (2 << 5)
 130 #define TWL6040_MCLK_38400KHZ           (3 << 5)
 131 #define TWL6040_MCLK_MSK                0x60
 132
 133 /* LPPLLCTL (0x08) fields */
 134
 135 #define TWL6040_LPLLENA                 0x01
 136 #define TWL6040_LPLLRST                 0x02
 137 #define TWL6040_LPLLSEL                 0x04
 138 #define TWL6040_LPLLFIN                 0x08
 139 #define TWL6040_HPLLSEL                 0x10
 140
 141 /* HSLCTL (0x10) fields */
 142
 143 #define TWL6040_HSDACMODEL              0x02
 144 #define TWL6040_HSDRVMODEL              0x08
 145
 146 /* HSRCTL (0x11) fields */
 147
 148 #define TWL6040_HSDACMODER              0x02
 149 #define TWL6040_HSDRVMODER              0x08
 150
 151 /* VIBCTLL (0x18) fields */
 152
 153 #define TWL6040_VIBCTRLLN               0x10
 154 #define TWL6040_VIBCTRLLP               0x04
 155 #define TWL6040_VIBENAL                 0x01
 156
 157 /* VIBCTLL (0x19) fields */
 158
 159 #define TWL6040_VIBCTRLRN               0x10
 160 #define TWL6040_VIBCTRLRP               0x04
 161 #define TWL6040_VIBENAR                 0x01
 162
 163 /* GPOCTL (0x1E) fields */
 164
 165 #define TWL6040_GPO1                    0x01
 166 #define TWL6040_GPO2                    0x02
 167 #define TWL6040_GPO3                    0x03
 168
 169 /* HSOTRIM (0x2B) fields */
 170
 171 #define TWL6040_HSLO                    0x0F
 172 #define TWL6040_HSRO                    0xF0
 173 #define TWL6040_HSLO_OFFSET             0
 174 #define TWL6040_HSRO_OFFSET             4
 175
 176 /* HFOTRIM (0x2C) fields */
 177
 178 #define TWL6040_HFLO                    0x0F
 179 #define TWL6040_HFRO                    0xF0
 180 #define TWL6040_HFLO_OFFSET             0
 181 #define TWL6040_HFRO_OFFSET             4
 182
 183 /* ACCCTL (0x2D) fields */
 184
 185 #define TWL6040_I2CSEL                  0x01
 186 #define TWL6040_RESETSPLIT              0x04
 187 #define TWL6040_INTCLRMODE              0x08
 188 #define TWL6040_CLK32KSEL               0x40
 189
 190 /* STATUS (0x2E) fields */
 191
 192 #define TWL6040_PLUGCOMP                0x02
 193
 194 #define TWL6040_CELLS                   2
 195
 196 #define TWL6040_IRQ_TH                  0
 197 #define TWL6040_IRQ_PLUG                1
 198 #define TWL6040_IRQ_HOOK                2
 199 #define TWL6040_IRQ_HF                  3
 200 #define TWL6040_IRQ_VIB                 4
 201 #define TWL6040_IRQ_READY               5
 202
 203 enum twl6040_pll_id {
 204         TWL6040_NOPLL_ID,
 205         TWL6040_LPPLL_ID,
 206         TWL6040_HPPLL_ID,
 207 };
 208
 209 struct twl6040 {
 210         struct device *dev;
 211         struct mutex mutex;
 212         struct mutex io_mutex;
 213         struct mutex irq_mutex;
 214         struct mfd_cell cells[TWL6040_CELLS];
 215         struct completion ready;
 216
 217         int audpwron;
 218         int powered;
 219         int power_count;
 220
 221         enum twl6040_pll_id pll;
 222         unsigned int sysclk;
 223         int icrev;
 224
 225         unsigned int irq;
 226         unsigned int irq_base;
 227         u8 irq_masks_cur;
 228         u8 irq_masks_cache;
 229 };
 230
 231 static inline int twl6040_request_irq(struct twl6040 *twl6040, int irq,
 232                                       irq_handler_t handler, const char *name,
 233                                       void *data)
 234 {
 235         if (!twl6040->irq_base)
 236                 return -EINVAL;
 237
 238         return request_threaded_irq(twl6040->irq_base + irq, NULL, handler,
 239                                     0, name, data);
 240 }
 241
 242 static inline void twl6040_free_irq(struct twl6040 *twl6040, int irq,
 243                                     void *data)
 244 {
 245         if (!twl6040->irq_base)
 246                 return;
 247
 248         free_irq(twl6040->irq_base + irq, data);
 249 }
 250
 251 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
 252 int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
 253                       u8 val);
 254 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
 255                      u8 mask);
 256 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
 257                        u8 mask);
 258 int twl6040_enable(struct twl6040 *twl6040);
 259 int twl6040_disable(struct twl6040 *twl6040);
 260 int twl6040_is_enabled(struct twl6040 *twl6040);
 261 int twl6040_set_pll(struct twl6040 *twl6040, enum twl6040_pll_id id,
 262                     unsigned int freq_in, unsigned int freq_out);
 263 enum twl6040_pll_id twl6040_get_pll(struct twl6040 *twl6040);
 264 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
 265 int twl6040_get_icrev(struct twl6040 *twl6040);
 266 int twl6040_irq_init(struct twl6040 *twl6040);
 267 void twl6040_irq_exit(struct twl6040 *twl6040);
 268
 269 #endif  /* End of __TWL6040_CODEC_H__ */