| blob | 9e4ce99e1613643f60430f001813f2da0977a6e1 |
1 /*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 ethernet5 = &enet5;
28 ethernet7 = &enet7;
29 pci1 = &pci1;
30 rapidio0 = &rio0;
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>;
45 bus-frequency = <0>;
46 clock-frequency = <0>;
47 next-level-cache = <&L2>;
48 };
49 };
51 memory {
52 device_type = "memory";
53 };
55 localbus@e0005000 {
56 #address-cells = <2>;
57 #size-cells = <1>;
58 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
59 reg = <0xe0005000 0x1000>;
60 interrupts = <19 2>;
61 interrupt-parent = <&mpic>;
63 ranges = <0x0 0x0 0xfe000000 0x02000000
64 0x1 0x0 0xf8000000 0x00008000
65 0x2 0x0 0xf0000000 0x04000000
66 0x3 0x0 0xfc000000 0x00008000
67 0x4 0x0 0xf8008000 0x00008000
68 0x5 0x0 0xf8010000 0x00008000>;
70 nor@0,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "cfi-flash";
74 reg = <0x0 0x0 0x02000000>;
75 bank-width = <1>;
76 device-width = <1>;
77 partition@0 {
78 label = "ramdisk";
79 reg = <0x00000000 0x01c00000>;
80 };
81 partition@1c00000 {
82 label = "kernel";
83 reg = <0x01c00000 0x002e0000>;
84 };
85 partiton@1ee0000 {
86 label = "dtb";
87 reg = <0x01ee0000 0x00020000>;
88 };
89 partition@1f00000 {
90 label = "firmware";
91 reg = <0x01f00000 0x00080000>;
92 read-only;
93 };
94 partition@1f80000 {
95 label = "u-boot";
96 reg = <0x01f80000 0x00080000>;
97 read-only;
98 };
99 };
101 bcsr@1,0 {
102 compatible = "fsl,mpc8569mds-bcsr";
103 reg = <1 0 0x8000>;
104 };
106 nand@3,0 {
107 compatible = "fsl,mpc8569-fcm-nand",
108 "fsl,elbc-fcm-nand";
109 reg = <3 0 0x8000>;
110 };
112 pib@4,0 {
113 compatible = "fsl,mpc8569mds-pib";
114 reg = <4 0 0x8000>;
115 };
117 pib@5,0 {
118 compatible = "fsl,mpc8569mds-pib";
119 reg = <5 0 0x8000>;
120 };
121 };
123 soc@e0000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "fsl,mpc8569-immr", "simple-bus";
128 ranges = <0x0 0xe0000000 0x100000>;
129 bus-frequency = <0>;
131 ecm-law@0 {
132 compatible = "fsl,ecm-law";
133 reg = <0x0 0x1000>;
134 fsl,num-laws = <10>;
135 };
137 ecm@1000 {
138 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
139 reg = <0x1000 0x1000>;
140 interrupts = <17 2>;
141 interrupt-parent = <&mpic>;
142 };
144 memory-controller@2000 {
145 compatible = "fsl,mpc8569-memory-controller";
146 reg = <0x2000 0x1000>;
147 interrupt-parent = <&mpic>;
148 interrupts = <18 2>;
149 };
151 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
161 rtc@68 {
162 compatible = "dallas,ds1374";
163 reg = <0x68>;
164 };
165 };
167 i2c@3100 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 cell-index = <1>;
171 compatible = "fsl-i2c";
172 reg = <0x3100 0x100>;
173 interrupts = <43 2>;
174 interrupt-parent = <&mpic>;
175 dfsrr;
176 };
178 serial0: serial@4500 {
179 cell-index = <0>;
180 device_type = "serial";
181 compatible = "ns16550";
182 reg = <0x4500 0x100>;
183 clock-frequency = <0>;
184 interrupts = <42 2>;
185 interrupt-parent = <&mpic>;
186 };
188 serial1: serial@4600 {
189 cell-index = <1>;
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <0x4600 0x100>;
193 clock-frequency = <0>;
194 interrupts = <42 2>;
195 interrupt-parent = <&mpic>;
196 };
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,mpc8569-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x80000>; // L2, 512K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,mpc8569-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x0 0x80>;
218 cell-index = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <20 2>;
221 };
222 dma-channel@80 {
223 compatible = "fsl,mpc8569-dma-channel",
224 "fsl,eloplus-dma-channel";
225 reg = <0x80 0x80>;
226 cell-index = <1>;
227 interrupt-parent = <&mpic>;
228 interrupts = <21 2>;
229 };
230 dma-channel@100 {
231 compatible = "fsl,mpc8569-dma-channel",
232 "fsl,eloplus-dma-channel";
233 reg = <0x100 0x80>;
234 cell-index = <2>;
235 interrupt-parent = <&mpic>;
236 interrupts = <22 2>;
237 };
238 dma-channel@180 {
239 compatible = "fsl,mpc8569-dma-channel",
240 "fsl,eloplus-dma-channel";
241 reg = <0x180 0x80>;
242 cell-index = <3>;
243 interrupt-parent = <&mpic>;
244 interrupts = <23 2>;
245 };
246 };
248 sdhci@2e000 {
249 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
250 reg = <0x2e000 0x1000>;
251 interrupts = <72 0x8>;
252 interrupt-parent = <&mpic>;
253 /* Filled in by U-Boot */
254 clock-frequency = <0>;
255 status = "disabled";
256 sdhci,1-bit-only;
257 };
259 crypto@30000 {
260 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
261 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
262 reg = <0x30000 0x10000>;
263 interrupts = <45 2 58 2>;
264 interrupt-parent = <&mpic>;
265 fsl,num-channels = <4>;
266 fsl,channel-fifo-len = <24>;
267 fsl,exec-units-mask = <0xbfe>;
268 fsl,descriptor-types-mask = <0x3ab0ebf>;
269 };
271 mpic: pic@40000 {
272 interrupt-controller;
273 #address-cells = <0>;
274 #interrupt-cells = <2>;
275 reg = <0x40000 0x40000>;
276 compatible = "chrp,open-pic";
277 device_type = "open-pic";
278 };
280 msi@41600 {
281 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
282 reg = <0x41600 0x80>;
283 msi-available-ranges = <0 0x100>;
284 interrupts = <
285 0xe0 0
286 0xe1 0
287 0xe2 0
288 0xe3 0
289 0xe4 0
290 0xe5 0
291 0xe6 0
292 0xe7 0>;
293 interrupt-parent = <&mpic>;
294 };
296 global-utilities@e0000 {
297 compatible = "fsl,mpc8569-guts";
298 reg = <0xe0000 0x1000>;
299 fsl,has-rstcr;
300 };
302 par_io@e0100 {
303 #address-cells = <1>;
304 #size-cells = <1>;
305 reg = <0xe0100 0x100>;
306 ranges = <0x0 0xe0100 0x100>;
307 device_type = "par_io";
308 num-ports = <7>;
310 qe_pio_e: gpio-controller@80 {
311 #gpio-cells = <2>;
312 compatible = "fsl,mpc8569-qe-pario-bank",
313 "fsl,mpc8323-qe-pario-bank";
314 reg = <0x80 0x18>;
315 gpio-controller;
316 };
318 pio1: ucc_pin@01 {
319 pio-map = <
320 /* port pin dir open_drain assignment has_irq */
321 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
322 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
323 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
324 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
325 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
326 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
327 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
328 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
329 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
330 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
331 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
332 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
333 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
334 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
335 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
336 };
338 pio2: ucc_pin@02 {
339 pio-map = <
340 /* port pin dir open_drain assignment has_irq */
341 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
342 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
343 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
344 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
345 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
346 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
347 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
348 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
349 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
350 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
351 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
352 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
353 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
354 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
355 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
356 };
358 pio3: ucc_pin@03 {
359 pio-map = <
360 /* port pin dir open_drain assignment has_irq */
361 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
362 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
363 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
364 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
365 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
366 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
367 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
368 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
369 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
370 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
371 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
372 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
373 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
374 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
375 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
376 };
378 pio4: ucc_pin@04 {
379 pio-map = <
380 /* port pin dir open_drain assignment has_irq */
381 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
382 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
383 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
384 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
385 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
386 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
387 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
388 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
389 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
390 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
391 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
392 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
393 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
394 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
395 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
396 };
397 };
398 };
400 qe@e0080000 {
401 #address-cells = <1>;
402 #size-cells = <1>;
403 device_type = "qe";
404 compatible = "fsl,qe";
405 ranges = <0x0 0xe0080000 0x40000>;
406 reg = <0xe0080000 0x480>;
407 brg-frequency = <0>;
408 bus-frequency = <0>;
409 fsl,qe-num-riscs = <4>;
410 fsl,qe-num-snums = <46>;
412 qeic: interrupt-controller@80 {
413 interrupt-controller;
414 compatible = "fsl,qe-ic";
415 #address-cells = <0>;
416 #interrupt-cells = <1>;
417 reg = <0x80 0x80>;
418 interrupts = <46 2 46 2>; //high:30 low:30
419 interrupt-parent = <&mpic>;
420 };
422 spi@4c0 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
426 reg = <0x4c0 0x40>;
427 cell-index = <0>;
428 interrupts = <2>;
429 interrupt-parent = <&qeic>;
430 gpios = <&qe_pio_e 30 0>;
431 mode = "cpu-qe";
433 serial-flash@0 {
434 compatible = "stm,m25p40";
435 reg = <0>;
436 spi-max-frequency = <25000000>;
437 };
438 };
440 spi@500 {
441 cell-index = <1>;
442 compatible = "fsl,spi";
443 reg = <0x500 0x40>;
444 interrupts = <1>;
445 interrupt-parent = <&qeic>;
446 mode = "cpu";
447 };
449 enet0: ucc@2000 {
450 device_type = "network";
451 compatible = "ucc_geth";
452 cell-index = <1>;
453 reg = <0x2000 0x200>;
454 interrupts = <32>;
455 interrupt-parent = <&qeic>;
456 local-mac-address = [ 00 00 00 00 00 00 ];
457 rx-clock-name = "none";
458 tx-clock-name = "clk12";
459 pio-handle = <&pio1>;
460 phy-handle = <&qe_phy0>;
461 phy-connection-type = "rgmii-id";
462 };
464 mdio@2120 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 reg = <0x2120 0x18>;
468 compatible = "fsl,ucc-mdio";
470 qe_phy0: ethernet-phy@07 {
471 interrupt-parent = <&mpic>;
472 interrupts = <1 1>;
473 reg = <0x7>;
474 device_type = "ethernet-phy";
475 };
476 qe_phy1: ethernet-phy@01 {
477 interrupt-parent = <&mpic>;
478 interrupts = <2 1>;
479 reg = <0x1>;
480 device_type = "ethernet-phy";
481 };
482 qe_phy2: ethernet-phy@02 {
483 interrupt-parent = <&mpic>;
484 interrupts = <3 1>;
485 reg = <0x2>;
486 device_type = "ethernet-phy";
487 };
488 qe_phy3: ethernet-phy@03 {
489 interrupt-parent = <&mpic>;
490 interrupts = <4 1>;
491 reg = <0x3>;
492 device_type = "ethernet-phy";
493 };
494 qe_phy5: ethernet-phy@04 {
495 interrupt-parent = <&mpic>;
496 reg = <0x04>;
497 device_type = "ethernet-phy";
498 };
499 qe_phy7: ethernet-phy@06 {
500 interrupt-parent = <&mpic>;
501 reg = <0x6>;
502 device_type = "ethernet-phy";
503 };
504 tbi-phy@11 {
505 reg = <0x11>;
506 device_type = "tbi-phy";
507 };
508 };
509 mdio@3520 {
510 #address-cells = <1>;
511 #size-cells = <0>;
512 reg = <0x3520 0x18>;
513 compatible = "fsl,ucc-mdio";
515 tbi0: tbi-phy@15 {
516 reg = <0x15>;
517 device_type = "tbi-phy";
518 };
519 };
520 mdio@3720 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <0x3720 0x38>;
524 compatible = "fsl,ucc-mdio";
525 tbi1: tbi-phy@17 {
526 reg = <0x17>;
527 device_type = "tbi-phy";
528 };
529 };
531 enet2: ucc@2200 {
532 device_type = "network";
533 compatible = "ucc_geth";
534 cell-index = <3>;
535 reg = <0x2200 0x200>;
536 interrupts = <34>;
537 interrupt-parent = <&qeic>;
538 local-mac-address = [ 00 00 00 00 00 00 ];
539 rx-clock-name = "none";
540 tx-clock-name = "clk12";
541 pio-handle = <&pio3>;
542 phy-handle = <&qe_phy2>;
543 phy-connection-type = "rgmii-id";
544 };
546 enet1: ucc@3000 {
547 device_type = "network";
548 compatible = "ucc_geth";
549 cell-index = <2>;
550 reg = <0x3000 0x200>;
551 interrupts = <33>;
552 interrupt-parent = <&qeic>;
553 local-mac-address = [ 00 00 00 00 00 00 ];
554 rx-clock-name = "none";
555 tx-clock-name = "clk17";
556 pio-handle = <&pio2>;
557 phy-handle = <&qe_phy1>;
558 phy-connection-type = "rgmii-id";
559 };
561 enet3: ucc@3200 {
562 device_type = "network";
563 compatible = "ucc_geth";
564 cell-index = <4>;
565 reg = <0x3200 0x200>;
566 interrupts = <35>;
567 interrupt-parent = <&qeic>;
568 local-mac-address = [ 00 00 00 00 00 00 ];
569 rx-clock-name = "none";
570 tx-clock-name = "clk17";
571 pio-handle = <&pio4>;
572 phy-handle = <&qe_phy3>;
573 phy-connection-type = "rgmii-id";
574 };
576 enet5: ucc@3400 {
577 device_type = "network";
578 compatible = "ucc_geth";
579 cell-index = <6>;
580 reg = <0x3400 0x200>;
581 interrupts = <41>;
582 interrupt-parent = <&qeic>;
583 local-mac-address = [ 00 00 00 00 00 00 ];
584 rx-clock-name = "none";
585 tx-clock-name = "none";
586 tbi-handle = <&tbi0>;
587 phy-handle = <&qe_phy5>;
588 phy-connection-type = "sgmii";
589 };
591 enet7: ucc@3600 {
592 device_type = "network";
593 compatible = "ucc_geth";
594 cell-index = <8>;
595 reg = <0x3600 0x200>;
596 interrupts = <43>;
597 interrupt-parent = <&qeic>;
598 local-mac-address = [ 00 00 00 00 00 00 ];
599 rx-clock-name = "none";
600 tx-clock-name = "none";
601 tbi-handle = <&tbi1>;
602 phy-handle = <&qe_phy7>;
603 phy-connection-type = "sgmii";
604 };
606 muram@10000 {
607 #address-cells = <1>;
608 #size-cells = <1>;
609 compatible = "fsl,qe-muram", "fsl,cpm-muram";
610 ranges = <0x0 0x10000 0x20000>;
612 data-only@0 {
613 compatible = "fsl,qe-muram-data",
614 "fsl,cpm-muram-data";
615 reg = <0x0 0x20000>;
616 };
617 };
619 };
621 /* PCI Express */
622 pci1: pcie@e000a000 {
623 compatible = "fsl,mpc8548-pcie";
624 device_type = "pci";
625 #interrupt-cells = <1>;
626 #size-cells = <2>;
627 #address-cells = <3>;
628 reg = <0xe000a000 0x1000>;
629 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
630 interrupt-map = <
631 /* IDSEL 0x0 (PEX) */
632 00000 0x0 0x0 0x1 &mpic 0x0 0x1
633 00000 0x0 0x0 0x2 &mpic 0x1 0x1
634 00000 0x0 0x0 0x3 &mpic 0x2 0x1
635 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
637 interrupt-parent = <&mpic>;
638 interrupts = <26 2>;
639 bus-range = <0 255>;
640 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
641 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
642 clock-frequency = <33333333>;
643 pcie@0 {
644 reg = <0x0 0x0 0x0 0x0 0x0>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 device_type = "pci";
648 ranges = <0x2000000 0x0 0xa0000000
649 0x2000000 0x0 0xa0000000
650 0x0 0x10000000
652 0x1000000 0x0 0x0
653 0x1000000 0x0 0x0
654 0x0 0x800000>;
655 };
656 };
658 rio0: rapidio@e00c00000 {
659 #address-cells = <2>;
660 #size-cells = <2>;
661 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
662 reg = <0xe00c0000 0x20000>;
663 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
664 interrupts = <48 2 /* error */
665 49 2 /* bell_outb */
666 50 2 /* bell_inb */
667 53 2 /* msg1_tx */
668 54 2 /* msg1_rx */
669 55 2 /* msg2_tx */
670 56 2 /* msg2_rx */>;
671 interrupt-parent = <&mpic>;
672 };
673 };