drivers/spi/mpc52xx_psc_spi.c

   1 /*
   2  * MPC52xx PSC in SPI mode driver.
   3  *
   4  * Maintainer: Dragos Carp
   5  *
   6  * Copyright (C) 2006 TOPTICA Photonics AG.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/errno.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/workqueue.h>
  21 #include <linux/completion.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/fsl_devices.h>
  26
  27 #include <asm/mpc52xx.h>
  28 #include <asm/mpc52xx_psc.h>
  29
  30 #define MCLK 20000000 /* PSC port MClk in hz */
  31
  32 struct mpc52xx_psc_spi {
  33         /* fsl_spi_platform data */
  34         void (*cs_control)(struct spi_device *spi, bool on);
  35         u32 sysclk;
  36
  37         /* driver internal data */
  38         struct mpc52xx_psc __iomem *psc;
  39         struct mpc52xx_psc_fifo __iomem *fifo;
  40         unsigned int irq;
  41         u8 bits_per_word;
  42         u8 busy;
  43
  44         struct workqueue_struct *workqueue;
  45         struct work_struct work;
  46
  47         struct list_head queue;
  48         spinlock_t lock;
  49
  50         struct completion done;
  51 };
  52
  53 /* controller state */
  54 struct mpc52xx_psc_spi_cs {
  55         int bits_per_word;
  56         int speed_hz;
  57 };
  58
  59 /* set clock freq, clock ramp, bits per work
  60  * if t is NULL then reset the values to the default values
  61  */
  62 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  63                 struct spi_transfer *t)
  64 {
  65         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  66
  67         cs->speed_hz = (t && t->speed_hz)
  68                         ? t->speed_hz : spi->max_speed_hz;
  69         cs->bits_per_word = (t && t->bits_per_word)
  70                         ? t->bits_per_word : spi->bits_per_word;
  71         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  72         return 0;
  73 }
  74
  75 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  76 {
  77         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  78         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  79         struct mpc52xx_psc __iomem *psc = mps->psc;
  80         u32 sicr;
  81         u16 ccr;
  82
  83         sicr = in_be32(&psc->sicr);
  84
  85         /* Set clock phase and polarity */
  86         if (spi->mode & SPI_CPHA)
  87                 sicr |= 0x00001000;
  88         else
  89                 sicr &= ~0x00001000;
  90         if (spi->mode & SPI_CPOL)
  91                 sicr |= 0x00002000;
  92         else
  93                 sicr &= ~0x00002000;
  94
  95         if (spi->mode & SPI_LSB_FIRST)
  96                 sicr |= 0x10000000;
  97         else
  98                 sicr &= ~0x10000000;
  99         out_be32(&psc->sicr, sicr);
 100
 101         /* Set clock frequency and bits per word
 102          * Because psc->ccr is defined as 16bit register instead of 32bit
 103          * just set the lower byte of BitClkDiv
 104          */
 105         ccr = in_be16((u16 __iomem *)&psc->ccr);
 106         ccr &= 0xFF00;
 107         if (cs->speed_hz)
 108                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
 109         else /* by default SPI Clk 1MHz */
 110                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
 111         out_be16((u16 __iomem *)&psc->ccr, ccr);
 112         mps->bits_per_word = cs->bits_per_word;
 113
 114         if (mps->cs_control)
 115                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 116 }
 117
 118 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
 119 {
 120         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 121
 122         if (mps->cs_control)
 123                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 124 }
 125
 126 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
 127 /* wake up when 80% fifo full */
 128 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
 129
 130 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
 131                                                 struct spi_transfer *t)
 132 {
 133         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 134         struct mpc52xx_psc __iomem *psc = mps->psc;
 135         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 136         unsigned rb = 0;        /* number of bytes receieved */
 137         unsigned sb = 0;        /* number of bytes sent */
 138         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
 139         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
 140         unsigned rfalarm;
 141         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
 142         unsigned recv_at_once;
 143         int last_block = 0;
 144
 145         if (!t->tx_buf && !t->rx_buf && t->len)
 146                 return -EINVAL;
 147
 148         /* enable transmiter/receiver */
 149         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 150         while (rb < t->len) {
 151                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
 152                         rfalarm = MPC52xx_PSC_RFALARM;
 153                         last_block = 0;
 154                 } else {
 155                         send_at_once = t->len - sb;
 156                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
 157                         last_block = 1;
 158                 }
 159
 160                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
 161                 for (; send_at_once; sb++, send_at_once--) {
 162                         /* set EOF flag before the last word is sent */
 163                         if (send_at_once == 1 && last_block)
 164                                 out_8(&psc->ircr2, 0x01);
 165
 166                         if (tx_buf)
 167                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
 168                         else
 169                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
 170                 }
 171
 172
 173                 /* enable interrupts and wait for wake up
 174                  * if just one byte is expected the Rx FIFO genererates no
 175                  * FFULL interrupt, so activate the RxRDY interrupt
 176                  */
 177                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 178                 if (t->len - rb == 1) {
 179                         out_8(&psc->mode, 0);
 180                 } else {
 181                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 182                         out_be16(&fifo->rfalarm, rfalarm);
 183                 }
 184                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
 185                 wait_for_completion(&mps->done);
 186                 recv_at_once = in_be16(&fifo->rfnum);
 187                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
 188
 189                 send_at_once = recv_at_once;
 190                 if (rx_buf) {
 191                         for (; recv_at_once; rb++, recv_at_once--)
 192                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
 193                 } else {
 194                         for (; recv_at_once; rb++, recv_at_once--)
 195                                 in_8(&psc->mpc52xx_psc_buffer_8);
 196                 }
 197         }
 198         /* disable transmiter/receiver */
 199         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 200
 201         return 0;
 202 }
 203
 204 static void mpc52xx_psc_spi_work(struct work_struct *work)
 205 {
 206         struct mpc52xx_psc_spi *mps =
 207                 container_of(work, struct mpc52xx_psc_spi, work);
 208
 209         spin_lock_irq(&mps->lock);
 210         mps->busy = 1;
 211         while (!list_empty(&mps->queue)) {
 212                 struct spi_message *m;
 213                 struct spi_device *spi;
 214                 struct spi_transfer *t = NULL;
 215                 unsigned cs_change;
 216                 int status;
 217
 218                 m = container_of(mps->queue.next, struct spi_message, queue);
 219                 list_del_init(&m->queue);
 220                 spin_unlock_irq(&mps->lock);
 221
 222                 spi = m->spi;
 223                 cs_change = 1;
 224                 status = 0;
 225                 list_for_each_entry (t, &m->transfers, transfer_list) {
 226                         if (t->bits_per_word || t->speed_hz) {
 227                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
 228                                 if (status < 0)
 229                                         break;
 230                         }
 231
 232                         if (cs_change)
 233                                 mpc52xx_psc_spi_activate_cs(spi);
 234                         cs_change = t->cs_change;
 235
 236                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
 237                         if (status)
 238                                 break;
 239                         m->actual_length += t->len;
 240
 241                         if (t->delay_usecs)
 242                                 udelay(t->delay_usecs);
 243
 244                         if (cs_change)
 245                                 mpc52xx_psc_spi_deactivate_cs(spi);
 246                 }
 247
 248                 m->status = status;
 249                 m->complete(m->context);
 250
 251                 if (status || !cs_change)
 252                         mpc52xx_psc_spi_deactivate_cs(spi);
 253
 254                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
 255
 256                 spin_lock_irq(&mps->lock);
 257         }
 258         mps->busy = 0;
 259         spin_unlock_irq(&mps->lock);
 260 }
 261
 262 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
 263 {
 264         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 265         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
 266         unsigned long flags;
 267
 268         if (spi->bits_per_word%8)
 269                 return -EINVAL;
 270
 271         if (!cs) {
 272                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 273                 if (!cs)
 274                         return -ENOMEM;
 275                 spi->controller_state = cs;
 276         }
 277
 278         cs->bits_per_word = spi->bits_per_word;
 279         cs->speed_hz = spi->max_speed_hz;
 280
 281         spin_lock_irqsave(&mps->lock, flags);
 282         if (!mps->busy)
 283                 mpc52xx_psc_spi_deactivate_cs(spi);
 284         spin_unlock_irqrestore(&mps->lock, flags);
 285
 286         return 0;
 287 }
 288
 289 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
 290                 struct spi_message *m)
 291 {
 292         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 293         unsigned long flags;
 294
 295         m->actual_length = 0;
 296         m->status = -EINPROGRESS;
 297
 298         spin_lock_irqsave(&mps->lock, flags);
 299         list_add_tail(&m->queue, &mps->queue);
 300         queue_work(mps->workqueue, &mps->work);
 301         spin_unlock_irqrestore(&mps->lock, flags);
 302
 303         return 0;
 304 }
 305
 306 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
 307 {
 308         kfree(spi->controller_state);
 309 }
 310
 311 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 312 {
 313         struct mpc52xx_psc __iomem *psc = mps->psc;
 314         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 315         u32 mclken_div;
 316         int ret = 0;
 317
 318         /* default sysclk is 512MHz */
 319         mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
 320         mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
 321
 322         /* Reset the PSC into a known state */
 323         out_8(&psc->command, MPC52xx_PSC_RST_RX);
 324         out_8(&psc->command, MPC52xx_PSC_RST_TX);
 325         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 326
 327         /* Disable interrupts, interrupts are based on alarm level */
 328         out_be16(&psc->mpc52xx_psc_imr, 0);
 329         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 330         out_8(&fifo->rfcntl, 0);
 331         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 332
 333         /* Configure 8bit codec mode as a SPI master and use EOF flags */
 334         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 335         out_be32(&psc->sicr, 0x0180C800);
 336         out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
 337
 338         /* Set 2ms DTL delay */
 339         out_8(&psc->ctur, 0x00);
 340         out_8(&psc->ctlr, 0x84);
 341
 342         mps->bits_per_word = 8;
 343
 344         return ret;
 345 }
 346
 347 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
 348 {
 349         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
 350         struct mpc52xx_psc __iomem *psc = mps->psc;
 351
 352         /* disable interrupt and wake up the work queue */
 353         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
 354                 out_be16(&psc->mpc52xx_psc_imr, 0);
 355                 complete(&mps->done);
 356                 return IRQ_HANDLED;
 357         }
 358         return IRQ_NONE;
 359 }
 360
 361 /* bus_num is used only for the case dev->platform_data == NULL */
 362 static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 363                                 u32 size, unsigned int irq, s16 bus_num)
 364 {
 365         struct fsl_spi_platform_data *pdata = dev->platform_data;
 366         struct mpc52xx_psc_spi *mps;
 367         struct spi_master *master;
 368         int ret;
 369
 370         master = spi_alloc_master(dev, sizeof *mps);
 371         if (master == NULL)
 372                 return -ENOMEM;
 373
 374         dev_set_drvdata(dev, master);
 375         mps = spi_master_get_devdata(master);
 376
 377         /* the spi->mode bits understood by this driver: */
 378         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 379
 380         mps->irq = irq;
 381         if (pdata == NULL) {
 382                 dev_warn(dev, "probe called without platform data, no "
 383                                 "cs_control function will be called\n");
 384                 mps->cs_control = NULL;
 385                 mps->sysclk = 0;
 386                 master->bus_num = bus_num;
 387                 master->num_chipselect = 255;
 388         } else {
 389                 mps->cs_control = pdata->cs_control;
 390                 mps->sysclk = pdata->sysclk;
 391                 master->bus_num = pdata->bus_num;
 392                 master->num_chipselect = pdata->max_chipselect;
 393         }
 394         master->setup = mpc52xx_psc_spi_setup;
 395         master->transfer = mpc52xx_psc_spi_transfer;
 396         master->cleanup = mpc52xx_psc_spi_cleanup;
 397
 398         mps->psc = ioremap(regaddr, size);
 399         if (!mps->psc) {
 400                 dev_err(dev, "could not ioremap I/O port range\n");
 401                 ret = -EFAULT;
 402                 goto free_master;
 403         }
 404         /* On the 5200, fifo regs are immediately ajacent to the psc regs */
 405         mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
 406
 407         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
 408                                 mps);
 409         if (ret)
 410                 goto free_master;
 411
 412         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
 413         if (ret < 0)
 414                 goto free_irq;
 415
 416         spin_lock_init(&mps->lock);
 417         init_completion(&mps->done);
 418         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
 419         INIT_LIST_HEAD(&mps->queue);
 420
 421         mps->workqueue = create_singlethread_workqueue(
 422                 dev_name(master->dev.parent));
 423         if (mps->workqueue == NULL) {
 424                 ret = -EBUSY;
 425                 goto free_irq;
 426         }
 427
 428         ret = spi_register_master(master);
 429         if (ret < 0)
 430                 goto unreg_master;
 431
 432         return ret;
 433
 434 unreg_master:
 435         destroy_workqueue(mps->workqueue);
 436 free_irq:
 437         free_irq(mps->irq, mps);
 438 free_master:
 439         if (mps->psc)
 440                 iounmap(mps->psc);
 441         spi_master_put(master);
 442
 443         return ret;
 444 }
 445
 446 static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
 447 {
 448         struct spi_master *master = dev_get_drvdata(dev);
 449         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
 450
 451         flush_workqueue(mps->workqueue);
 452         destroy_workqueue(mps->workqueue);
 453         spi_unregister_master(master);
 454         free_irq(mps->irq, mps);
 455         if (mps->psc)
 456                 iounmap(mps->psc);
 457
 458         return 0;
 459 }
 460
 461 static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
 462         const struct of_device_id *match)
 463 {
 464         const u32 *regaddr_p;
 465         u64 regaddr64, size64;
 466         s16 id = -1;
 467
 468         regaddr_p = of_get_address(op->node, 0, &size64, NULL);
 469         if (!regaddr_p) {
 470                 printk(KERN_ERR "Invalid PSC address\n");
 471                 return -EINVAL;
 472         }
 473         regaddr64 = of_translate_address(op->node, regaddr_p);
 474
 475         /* get PSC id (1..6, used by port_config) */
 476         if (op->dev.platform_data == NULL) {
 477                 const u32 *psc_nump;
 478
 479                 psc_nump = of_get_property(op->node, "cell-index", NULL);
 480                 if (!psc_nump || *psc_nump > 5) {
 481                         printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid "
 482                                         "cell-index property\n", op->node->full_name);
 483                         return -EINVAL;
 484                 }
 485                 id = *psc_nump + 1;
 486         }
 487
 488         return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
 489                                         irq_of_parse_and_map(op->node, 0), id);
 490 }
 491
 492 static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
 493 {
 494         return mpc52xx_psc_spi_do_remove(&op->dev);
 495 }
 496
 497 static struct of_device_id mpc52xx_psc_spi_of_match[] = {
 498         { .compatible = "fsl,mpc5200-psc-spi", },
 499         { .compatible = "mpc5200-psc-spi", }, /* old */
 500         {}
 501 };
 502
 503 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
 504
 505 static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
 506         .owner = THIS_MODULE,
 507         .name = "mpc52xx-psc-spi",
 508         .match_table = mpc52xx_psc_spi_of_match,
 509         .probe = mpc52xx_psc_spi_of_probe,
 510         .remove = __exit_p(mpc52xx_psc_spi_of_remove),
 511         .driver = {
 512                 .name = "mpc52xx-psc-spi",
 513                 .owner = THIS_MODULE,
 514         },
 515 };
 516
 517 static int __init mpc52xx_psc_spi_init(void)
 518 {
 519         return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
 520 }
 521 module_init(mpc52xx_psc_spi_init);
 522
 523 static void __exit mpc52xx_psc_spi_exit(void)
 524 {
 525         of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
 526 }
 527 module_exit(mpc52xx_psc_spi_exit);
 528
 529 MODULE_AUTHOR("Dragos Carp");
 530 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
 531 MODULE_LICENSE("GPL");