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rcv reorder queue bugfix
[cor_2_6_31.git] / drivers / edac / i5400_edac.c
blobb08b6d8e2dc7c20cb101c7c611c3cd99a483a97b
1 /*
2 * Intel 5400 class Memory Controllers kernel module (Seaburg)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Copyright (c) 2008 by:
8 * Ben Woodard <woodard@redhat.com>
9 * Mauro Carvalho Chehab <mchehab@redhat.com>
10 *
11 * Red Hat Inc. http://www.redhat.com
12 *
13 * Forked and adapted from the i5000_edac driver which was
14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com>
15 *
16 * This module is based on the following document:
17 *
18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
19 * http://developer.intel.com/design/chipsets/datashts/313070.htm
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/slab.h>
28 #include <linux/edac.h>
29 #include <linux/mmzone.h>
30
31 #include "edac_core.h"
32
33 /*
34 * Alter this version for the I5400 module when modifications are made
35 */
36 #define I5400_REVISION " Ver: 1.0.0 " __DATE__
37
38 #define EDAC_MOD_STR "i5400_edac"
39
40 #define i5400_printk(level, fmt, arg...) \
41 edac_printk(level, "i5400", fmt, ##arg)
42
43 #define i5400_mc_printk(mci, level, fmt, arg...) \
44 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)
45
46 /* Limits for i5400 */
47 #define NUM_MTRS_PER_BRANCH 4
48 #define CHANNELS_PER_BRANCH 2
49 #define MAX_CHANNELS 4
50 #define MAX_DIMMS (MAX_CHANNELS * 4) /* Up to 4 DIMM's per channel */
51 #define MAX_CSROWS (MAX_DIMMS * 2) /* max possible csrows per channel */
52
53 /* Device 16,
54 * Function 0: System Address
55 * Function 1: Memory Branch Map, Control, Errors Register
56 * Function 2: FSB Error Registers
57 *
58 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
59 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),
60 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1
61 * for device 21 (0,1).
62 */
63
64 /* OFFSETS for Function 0 */
65 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
66 #define MAXCH 0x56 /* Max Channel Number */
67 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
68
69 /* OFFSETS for Function 1 */
70 #define TOLM 0x6C
71 #define REDMEMB 0x7C
72 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
73 #define MIR0 0x80
74 #define MIR1 0x84
75 #define AMIR0 0x8c
76 #define AMIR1 0x90
77
78 /* Fatal error registers */
79 #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */
80 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
81
82 #define NERR_FAT_FBD 0x9c
83 #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */
84
85 /* Non-fatal error register */
86 #define NERR_NF_FBD 0xa4
87
88 /* Enable error mask */
89 #define EMASK_FBD 0xa8
90
91 #define ERR0_FBD 0xac
92 #define ERR1_FBD 0xb0
93 #define ERR2_FBD 0xb4
94 #define MCERR_FBD 0xb8
95
96 /* No OFFSETS for Device 16 Function 2 */
97
98 /*
99 * Device 21,
100 * Function 0: Memory Map Branch 0
101 *
102 * Device 22,
103 * Function 0: Memory Map Branch 1
104 */
105
106 /* OFFSETS for Function 0 */
107 #define AMBPRESENT_0 0x64
108 #define AMBPRESENT_1 0x66
109 #define MTR0 0x80
110 #define MTR1 0x82
111 #define MTR2 0x84
112 #define MTR3 0x86
113
114 /* OFFSETS for Function 1 */
115 #define NRECFGLOG 0x74
116 #define RECFGLOG 0x78
117 #define NRECMEMA 0xbe
118 #define NRECMEMB 0xc0
119 #define NRECFB_DIMMA 0xc4
120 #define NRECFB_DIMMB 0xc8
121 #define NRECFB_DIMMC 0xcc
122 #define NRECFB_DIMMD 0xd0
123 #define NRECFB_DIMME 0xd4
124 #define NRECFB_DIMMF 0xd8
125 #define REDMEMA 0xdC
126 #define RECMEMA 0xf0
127 #define RECMEMB 0xf4
128 #define RECFB_DIMMA 0xf8
129 #define RECFB_DIMMB 0xec
130 #define RECFB_DIMMC 0xf0
131 #define RECFB_DIMMD 0xf4
132 #define RECFB_DIMME 0xf8
133 #define RECFB_DIMMF 0xfC
134
135 /*
136 * Error indicator bits and masks
137 * Error masks are according with Table 5-17 of i5400 datasheet
138 */
139
140 enum error_mask {
141 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
142 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
143 EMASK_M3 = 1<<2, /* Reserved */
144 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
145 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
146 EMASK_M6 = 1<<5, /* Unsupported on i5400 */
147 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
148 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
149 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M10 = 1<<9, /* Unsupported on i5400 */
151 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
152 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
153 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
154 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
155 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
156 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
157 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
158 EMASK_M18 = 1<<17, /* Unsupported on i5400 */
159 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
160 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
161 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
162 EMASK_M22 = 1<<21, /* SPD protocol Error */
163 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
164 EMASK_M24 = 1<<23, /* Refresh error */
165 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
166 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
167 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
168 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
169 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
170 };
171
172 /*
173 * Names to translate bit error into something useful
174 */
175 static const char *error_name[] = {
176 [0] = "Memory Write error on non-redundant retry",
177 [1] = "Memory or FB-DIMM configuration CRC read error",
178 /* Reserved */
179 [3] = "Uncorrectable Data ECC on Replay",
180 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
181 /* M6 Unsupported on i5400 */
182 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
183 [7] = "Aliased Uncorrectable Patrol Data ECC",
184 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
185 /* M10 Unsupported on i5400 */
186 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
187 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
188 [12] = "Memory Write error on first attempt",
189 [13] = "FB-DIMM Configuration Write error on first attempt",
190 [14] = "Memory or FB-DIMM configuration CRC read error",
191 [15] = "Channel Failed-Over Occurred",
192 [16] = "Correctable Non-Mirrored Demand Data ECC",
193 /* M18 Unsupported on i5400 */
194 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
195 [19] = "Correctable Patrol Data ECC",
196 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
197 [21] = "SPD protocol Error",
198 [22] = "Non-Redundant Fast Reset Timeout",
199 [23] = "Refresh error",
200 [24] = "Memory Write error on redundant retry",
201 [25] = "Redundant Fast Reset Timeout",
202 [26] = "Correctable Counter Threshold Exceeded",
203 [27] = "DIMM-Spare Copy Completed",
204 [28] = "DIMM-Isolation Completed",
205 };
206
207 /* Fatal errors */
208 #define ERROR_FAT_MASK (EMASK_M1 | \
209 EMASK_M2 | \
210 EMASK_M23)
211
212 /* Correctable errors */
213 #define ERROR_NF_CORRECTABLE (EMASK_M27 | \
214 EMASK_M20 | \
215 EMASK_M19 | \
216 EMASK_M18 | \
217 EMASK_M17 | \
218 EMASK_M16)
219 #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
220 EMASK_M28)
221 #define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
222 #define ERROR_NF_NORTH_CRC (EMASK_M21)
223
224 /* Recoverable errors */
225 #define ERROR_NF_RECOVERABLE (EMASK_M26 | \
226 EMASK_M25 | \
227 EMASK_M24 | \
228 EMASK_M15 | \
229 EMASK_M14 | \
230 EMASK_M13 | \
231 EMASK_M12 | \
232 EMASK_M11 | \
233 EMASK_M9 | \
234 EMASK_M8 | \
235 EMASK_M7 | \
236 EMASK_M5)
237
238 /* uncorrectable errors */
239 #define ERROR_NF_UNCORRECTABLE (EMASK_M4)
240
241 /* mask to all non-fatal errors */
242 #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
243 ERROR_NF_UNCORRECTABLE | \
244 ERROR_NF_RECOVERABLE | \
245 ERROR_NF_DIMM_SPARE | \
246 ERROR_NF_SPD_PROTOCOL | \
247 ERROR_NF_NORTH_CRC)
248
249 /*
250 * Define error masks for the several registers
251 */
252
253 /* Enable all fatal and non fatal errors */
254 #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
255
256 /* mask for fatal error registers */
257 #define FERR_FAT_MASK ERROR_FAT_MASK
258
259 /* masks for non-fatal error register */
260 static inline int to_nf_mask(unsigned int mask)
261 {
262 return (mask & EMASK_M29) | (mask >> 3);
263 };
264
265 static inline int from_nf_ferr(unsigned int mask)
266 {
267 return (mask & EMASK_M29) | /* Bit 28 */
268 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
269 };
270
271 #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
272 #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
273 #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
274 #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
275 #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
276 #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
277 #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
278
279 /* Defines to extract the vaious fields from the
280 * MTRx - Memory Technology Registers
281 */
282 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
283 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
284 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
285 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
286 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
287 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
288 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
289 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
290 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
291 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
292 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
293
294 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
295 static inline int extract_fbdchan_indx(u32 x)
296 {
297 return (x>>28) & 0x3;
298 }
299
300 #ifdef CONFIG_EDAC_DEBUG
301 /* MTR NUMROW */
302 static const char *numrow_toString[] = {
303 "8,192 - 13 rows",
304 "16,384 - 14 rows",
305 "32,768 - 15 rows",
306 "65,536 - 16 rows"
307 };
308
309 /* MTR NUMCOL */
310 static const char *numcol_toString[] = {
311 "1,024 - 10 columns",
312 "2,048 - 11 columns",
313 "4,096 - 12 columns",
314 "reserved"
315 };
316 #endif
317
318 /* Device name and register DID (Device ID) */
319 struct i5400_dev_info {
320 const char *ctl_name; /* name for this device */
321 u16 fsb_mapping_errors; /* DID for the branchmap,control */
322 };
323
324 /* Table of devices attributes supported by this driver */
325 static const struct i5400_dev_info i5400_devs[] = {
326 {
327 .ctl_name = "I5400",
328 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR,
329 },
330 };
331
332 struct i5400_dimm_info {
333 int megabytes; /* size, 0 means not present */
334 int dual_rank;
335 };
336
337 /* driver private data structure */
338 struct i5400_pvt {
339 struct pci_dev *system_address; /* 16.0 */
340 struct pci_dev *branchmap_werrors; /* 16.1 */
341 struct pci_dev *fsb_error_regs; /* 16.2 */
342 struct pci_dev *branch_0; /* 21.0 */
343 struct pci_dev *branch_1; /* 22.0 */
344
345 u16 tolm; /* top of low memory */
346 u64 ambase; /* AMB BAR */
347
348 u16 mir0, mir1;
349
350 u16 b0_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
351 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
352 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
353
354 u16 b1_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
355 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
356 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
357
358 /* DIMM information matrix, allocating architecture maximums */
359 struct i5400_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
360
361 /* Actual values for this controller */
362 int maxch; /* Max channels */
363 int maxdimmperch; /* Max DIMMs per channel */
364 };
365
366 /* I5400 MCH error information retrieved from Hardware */
367 struct i5400_error_info {
368 /* These registers are always read from the MC */
369 u32 ferr_fat_fbd; /* First Errors Fatal */
370 u32 nerr_fat_fbd; /* Next Errors Fatal */
371 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
372 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
373
374 /* These registers are input ONLY if there was a Recoverable Error */
375 u32 redmemb; /* Recoverable Mem Data Error log B */
376 u16 recmema; /* Recoverable Mem Error log A */
377 u32 recmemb; /* Recoverable Mem Error log B */
378
379 /* These registers are input ONLY if there was a Non-Rec Error */
380 u16 nrecmema; /* Non-Recoverable Mem log A */
381 u16 nrecmemb; /* Non-Recoverable Mem log B */
382
383 };
384
385 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
386 5400 better to use an inline function than a macro in this case */
387 static inline int nrec_bank(struct i5400_error_info *info)
388 {
389 return ((info->nrecmema) >> 12) & 0x7;
390 }
391 static inline int nrec_rank(struct i5400_error_info *info)
392 {
393 return ((info->nrecmema) >> 8) & 0xf;
394 }
395 static inline int nrec_buf_id(struct i5400_error_info *info)
396 {
397 return ((info->nrecmema)) & 0xff;
398 }
399 static inline int nrec_rdwr(struct i5400_error_info *info)
400 {
401 return (info->nrecmemb) >> 31;
402 }
403 /* This applies to both NREC and REC string so it can be used with nrec_rdwr
404 and rec_rdwr */
405 static inline const char *rdwr_str(int rdwr)
406 {
407 return rdwr ? "Write" : "Read";
408 }
409 static inline int nrec_cas(struct i5400_error_info *info)
410 {
411 return ((info->nrecmemb) >> 16) & 0x1fff;
412 }
413 static inline int nrec_ras(struct i5400_error_info *info)
414 {
415 return (info->nrecmemb) & 0xffff;
416 }
417 static inline int rec_bank(struct i5400_error_info *info)
418 {
419 return ((info->recmema) >> 12) & 0x7;
420 }
421 static inline int rec_rank(struct i5400_error_info *info)
422 {
423 return ((info->recmema) >> 8) & 0xf;
424 }
425 static inline int rec_rdwr(struct i5400_error_info *info)
426 {
427 return (info->recmemb) >> 31;
428 }
429 static inline int rec_cas(struct i5400_error_info *info)
430 {
431 return ((info->recmemb) >> 16) & 0x1fff;
432 }
433 static inline int rec_ras(struct i5400_error_info *info)
434 {
435 return (info->recmemb) & 0xffff;
436 }
437
438 static struct edac_pci_ctl_info *i5400_pci;
439
440 /*
441 * i5400_get_error_info Retrieve the hardware error information from
442 * the hardware and cache it in the 'info'
443 * structure
444 */
445 static void i5400_get_error_info(struct mem_ctl_info *mci,
446 struct i5400_error_info *info)
447 {
448 struct i5400_pvt *pvt;
449 u32 value;
450
451 pvt = mci->pvt_info;
452
453 /* read in the 1st FATAL error register */
454 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
455
456 /* Mask only the bits that the doc says are valid
457 */
458 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
459
460 /* If there is an error, then read in the
461 NEXT FATAL error register and the Memory Error Log Register A
462 */
463 if (value & FERR_FAT_MASK) {
464 info->ferr_fat_fbd = value;
465
466 /* harvest the various error data we need */
467 pci_read_config_dword(pvt->branchmap_werrors,
468 NERR_FAT_FBD, &info->nerr_fat_fbd);
469 pci_read_config_word(pvt->branchmap_werrors,
470 NRECMEMA, &info->nrecmema);
471 pci_read_config_word(pvt->branchmap_werrors,
472 NRECMEMB, &info->nrecmemb);
473
474 /* Clear the error bits, by writing them back */
475 pci_write_config_dword(pvt->branchmap_werrors,
476 FERR_FAT_FBD, value);
477 } else {
478 info->ferr_fat_fbd = 0;
479 info->nerr_fat_fbd = 0;
480 info->nrecmema = 0;
481 info->nrecmemb = 0;
482 }
483
484 /* read in the 1st NON-FATAL error register */
485 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
486
487 /* If there is an error, then read in the 1st NON-FATAL error
488 * register as well */
489 if (value & FERR_NF_MASK) {
490 info->ferr_nf_fbd = value;
491
492 /* harvest the various error data we need */
493 pci_read_config_dword(pvt->branchmap_werrors,
494 NERR_NF_FBD, &info->nerr_nf_fbd);
495 pci_read_config_word(pvt->branchmap_werrors,
496 RECMEMA, &info->recmema);
497 pci_read_config_dword(pvt->branchmap_werrors,
498 RECMEMB, &info->recmemb);
499 pci_read_config_dword(pvt->branchmap_werrors,
500 REDMEMB, &info->redmemb);
501
502 /* Clear the error bits, by writing them back */
503 pci_write_config_dword(pvt->branchmap_werrors,
504 FERR_NF_FBD, value);
505 } else {
506 info->ferr_nf_fbd = 0;
507 info->nerr_nf_fbd = 0;
508 info->recmema = 0;
509 info->recmemb = 0;
510 info->redmemb = 0;
511 }
512 }
513
514 /*
515 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
516 * struct i5400_error_info *info,
517 * int handle_errors);
518 *
519 * handle the Intel FATAL and unrecoverable errors, if any
520 */
521 static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
522 struct i5400_error_info *info,
523 unsigned long allErrors)
524 {
525 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
526 int branch;
527 int channel;
528 int bank;
529 int buf_id;
530 int rank;
531 int rdwr;
532 int ras, cas;
533 int errnum;
534 char *type = NULL;
535
536 if (!allErrors)
537 return; /* if no error, return now */
538
539 if (allErrors & ERROR_FAT_MASK)
540 type = "FATAL";
541 else if (allErrors & FERR_NF_UNCORRECTABLE)
542 type = "NON-FATAL uncorrected";
543 else
544 type = "NON-FATAL recoverable";
545
546 /* ONLY ONE of the possible error bits will be set, as per the docs */
547
548 branch = extract_fbdchan_indx(info->ferr_fat_fbd);
549 channel = branch;
550
551 /* Use the NON-Recoverable macros to extract data */
552 bank = nrec_bank(info);
553 rank = nrec_rank(info);
554 buf_id = nrec_buf_id(info);
555 rdwr = nrec_rdwr(info);
556 ras = nrec_ras(info);
557 cas = nrec_cas(info);
558
559 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
560 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
561 rank, channel, channel + 1, branch >> 1, bank,
562 buf_id, rdwr_str(rdwr), ras, cas);
563
564 /* Only 1 bit will be on */
565 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
566
567 /* Form out message */
568 snprintf(msg, sizeof(msg),
569 "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
570 "RAS=%d CAS=%d %s Err=0x%lx (%s))",
571 type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
572 type, allErrors, error_name[errnum]);
573
574 /* Call the helper to output message */
575 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
576 }
577
578 /*
579 * i5400_process_fatal_error_info(struct mem_ctl_info *mci,
580 * struct i5400_error_info *info,
581 * int handle_errors);
582 *
583 * handle the Intel NON-FATAL errors, if any
584 */
585 static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
586 struct i5400_error_info *info)
587 {
588 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
589 unsigned long allErrors;
590 int branch;
591 int channel;
592 int bank;
593 int rank;
594 int rdwr;
595 int ras, cas;
596 int errnum;
597
598 /* mask off the Error bits that are possible */
599 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
600 if (!allErrors)
601 return; /* if no error, return now */
602
603 /* ONLY ONE of the possible error bits will be set, as per the docs */
604
605 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
606 i5400_proccess_non_recoverable_info(mci, info, allErrors);
607 return;
608 }
609
610 /* Correctable errors */
611 if (allErrors & ERROR_NF_CORRECTABLE) {
612 debugf0("\tCorrected bits= 0x%lx\n", allErrors);
613
614 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
615
616 channel = 0;
617 if (REC_ECC_LOCATOR_ODD(info->redmemb))
618 channel = 1;
619
620 /* Convert channel to be based from zero, instead of
621 * from branch base of 0 */
622 channel += branch;
623
624 bank = rec_bank(info);
625 rank = rec_rank(info);
626 rdwr = rec_rdwr(info);
627 ras = rec_ras(info);
628 cas = rec_cas(info);
629
630 /* Only 1 bit will be on */
631 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
632
633 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
634 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
635 rank, channel, branch >> 1, bank,
636 rdwr_str(rdwr), ras, cas);
637
638 /* Form out message */
639 snprintf(msg, sizeof(msg),
640 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
641 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
642 branch >> 1, bank, rdwr_str(rdwr), ras, cas,
643 allErrors, error_name[errnum]);
644
645 /* Call the helper to output message */
646 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
647
648 return;
649 }
650
651 /* Miscelaneous errors */
652 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
653
654 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
655
656 i5400_mc_printk(mci, KERN_EMERG,
657 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
658 branch >> 1, allErrors, error_name[errnum]);
659 }
660
661 /*
662 * i5400_process_error_info Process the error info that is
663 * in the 'info' structure, previously retrieved from hardware
664 */
665 static void i5400_process_error_info(struct mem_ctl_info *mci,
666 struct i5400_error_info *info)
667 { u32 allErrors;
668
669 /* First handle any fatal errors that occurred */
670 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
671 i5400_proccess_non_recoverable_info(mci, info, allErrors);
672
673 /* now handle any non-fatal errors that occurred */
674 i5400_process_nonfatal_error_info(mci, info);
675 }
676
677 /*
678 * i5400_clear_error Retrieve any error from the hardware
679 * but do NOT process that error.
680 * Used for 'clearing' out of previous errors
681 * Called by the Core module.
682 */
683 static void i5400_clear_error(struct mem_ctl_info *mci)
684 {
685 struct i5400_error_info info;
686
687 i5400_get_error_info(mci, &info);
688 }
689
690 /*
691 * i5400_check_error Retrieve and process errors reported by the
692 * hardware. Called by the Core module.
693 */
694 static void i5400_check_error(struct mem_ctl_info *mci)
695 {
696 struct i5400_error_info info;
697 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
698 i5400_get_error_info(mci, &info);
699 i5400_process_error_info(mci, &info);
700 }
701
702 /*
703 * i5400_put_devices 'put' all the devices that we have
704 * reserved via 'get'
705 */
706 static void i5400_put_devices(struct mem_ctl_info *mci)
707 {
708 struct i5400_pvt *pvt;
709
710 pvt = mci->pvt_info;
711
712 /* Decrement usage count for devices */
713 pci_dev_put(pvt->branch_1);
714 pci_dev_put(pvt->branch_0);
715 pci_dev_put(pvt->fsb_error_regs);
716 pci_dev_put(pvt->branchmap_werrors);
717 }
718
719 /*
720 * i5400_get_devices Find and perform 'get' operation on the MCH's
721 * device/functions we want to reference for this driver
722 *
723 * Need to 'get' device 16 func 1 and func 2
724 */
725 static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
726 {
727 struct i5400_pvt *pvt;
728 struct pci_dev *pdev;
729
730 pvt = mci->pvt_info;
731 pvt->branchmap_werrors = NULL;
732 pvt->fsb_error_regs = NULL;
733 pvt->branch_0 = NULL;
734 pvt->branch_1 = NULL;
735
736 /* Attempt to 'get' the MCH register we want */
737 pdev = NULL;
738 while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
739 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
740 PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
741 if (!pdev) {
742 /* End of list, leave */
743 i5400_printk(KERN_ERR,
744 "'system address,Process Bus' "
745 "device not found:"
746 "vendor 0x%x device 0x%x ERR funcs "
747 "(broken BIOS?)\n",
748 PCI_VENDOR_ID_INTEL,
749 PCI_DEVICE_ID_INTEL_5400_ERR);
750 goto error;
751 }
752
753 /* Store device 16 funcs 1 and 2 */
754 switch (PCI_FUNC(pdev->devfn)) {
755 case 1:
756 pvt->branchmap_werrors = pdev;
757 break;
758 case 2:
759 pvt->fsb_error_regs = pdev;
760 break;
761 }
762 }
763
764 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
765 pci_name(pvt->system_address),
766 pvt->system_address->vendor, pvt->system_address->device);
767 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
768 pci_name(pvt->branchmap_werrors),
769 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
770 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
771 pci_name(pvt->fsb_error_regs),
772 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
773
774 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
775 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);
776 if (!pvt->branch_0) {
777 i5400_printk(KERN_ERR,
778 "MC: 'BRANCH 0' device not found:"
779 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
780 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);
781 goto error;
782 }
783
784 /* If this device claims to have more than 2 channels then
785 * fetch Branch 1's information
786 */
787 if (pvt->maxch < CHANNELS_PER_BRANCH)
788 return 0;
789
790 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
791 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL);
792 if (!pvt->branch_1) {
793 i5400_printk(KERN_ERR,
794 "MC: 'BRANCH 1' device not found:"
795 "vendor 0x%x device 0x%x Func 0 "
796 "(broken BIOS?)\n",
797 PCI_VENDOR_ID_INTEL,
798 PCI_DEVICE_ID_INTEL_5400_FBD1);
799 goto error;
800 }
801
802 return 0;
803
804 error:
805 i5400_put_devices(mci);
806 return -ENODEV;
807 }
808
809 /*
810 * determine_amb_present
811 *
812 * the information is contained in NUM_MTRS_PER_BRANCH different
813 * registers determining which of the NUM_MTRS_PER_BRANCH requires
814 * knowing which channel is in question
815 *
816 * 2 branches, each with 2 channels
817 * b0_ambpresent0 for channel '0'
818 * b0_ambpresent1 for channel '1'
819 * b1_ambpresent0 for channel '2'
820 * b1_ambpresent1 for channel '3'
821 */
822 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
823 {
824 int amb_present;
825
826 if (channel < CHANNELS_PER_BRANCH) {
827 if (channel & 0x1)
828 amb_present = pvt->b0_ambpresent1;
829 else
830 amb_present = pvt->b0_ambpresent0;
831 } else {
832 if (channel & 0x1)
833 amb_present = pvt->b1_ambpresent1;
834 else
835 amb_present = pvt->b1_ambpresent0;
836 }
837
838 return amb_present;
839 }
840
841 /*
842 * determine_mtr(pvt, csrow, channel)
843 *
844 * return the proper MTR register as determine by the csrow and desired channel
845 */
846 static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
847 {
848 int mtr;
849 int n;
850
851 /* There is one MTR for each slot pair of FB-DIMMs,
852 Each slot may have one or two ranks (2 csrows),
853 Each slot pair may be at branch 0 or branch 1.
854 So, csrow should be divided by eight
855 */
856 n = csrow >> 3;
857
858 if (n >= NUM_MTRS_PER_BRANCH) {
859 debugf0("ERROR: trying to access an invalid csrow: %d\n",
860 csrow);
861 return 0;
862 }
863
864 if (channel < CHANNELS_PER_BRANCH)
865 mtr = pvt->b0_mtr[n];
866 else
867 mtr = pvt->b1_mtr[n];
868
869 return mtr;
870 }
871
872 /*
873 */
874 static void decode_mtr(int slot_row, u16 mtr)
875 {
876 int ans;
877
878 ans = MTR_DIMMS_PRESENT(mtr);
879
880 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
881 ans ? "Present" : "NOT Present");
882 if (!ans)
883 return;
884
885 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
886
887 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
888 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
889
890 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
891 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
892 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
893 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
894 }
895
896 static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
897 struct i5400_dimm_info *dinfo)
898 {
899 int mtr;
900 int amb_present_reg;
901 int addrBits;
902
903 mtr = determine_mtr(pvt, csrow, channel);
904 if (MTR_DIMMS_PRESENT(mtr)) {
905 amb_present_reg = determine_amb_present_reg(pvt, channel);
906
907 /* Determine if there is a DIMM present in this DIMM slot */
908 if (amb_present_reg & (1 << (csrow >> 1))) {
909 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
910
911 if (!((dinfo->dual_rank == 0) &&
912 ((csrow & 0x1) == 0x1))) {
913 /* Start with the number of bits for a Bank
914 * on the DRAM */
915 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
916 /* Add thenumber of ROW bits */
917 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
918 /* add the number of COLUMN bits */
919 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
920
921 addrBits += 6; /* add 64 bits per DIMM */
922 addrBits -= 20; /* divide by 2^^20 */
923 addrBits -= 3; /* 8 bits per bytes */
924
925 dinfo->megabytes = 1 << addrBits;
926 }
927 }
928 }
929 }
930
931 /*
932 * calculate_dimm_size
933 *
934 * also will output a DIMM matrix map, if debug is enabled, for viewing
935 * how the DIMMs are populated
936 */
937 static void calculate_dimm_size(struct i5400_pvt *pvt)
938 {
939 struct i5400_dimm_info *dinfo;
940 int csrow, max_csrows;
941 char *p, *mem_buffer;
942 int space, n;
943 int channel;
944
945 /* ================= Generate some debug output ================= */
946 space = PAGE_SIZE;
947 mem_buffer = p = kmalloc(space, GFP_KERNEL);
948 if (p == NULL) {
949 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
950 __FILE__, __func__);
951 return;
952 }
953
954 /* Scan all the actual CSROWS (which is # of DIMMS * 2)
955 * and calculate the information for each DIMM
956 * Start with the highest csrow first, to display it first
957 * and work toward the 0th csrow
958 */
959 max_csrows = pvt->maxdimmperch * 2;
960 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
961
962 /* on an odd csrow, first output a 'boundary' marker,
963 * then reset the message buffer */
964 if (csrow & 0x1) {
965 n = snprintf(p, space, "---------------------------"
966 "--------------------------------");
967 p += n;
968 space -= n;
969 debugf2("%s\n", mem_buffer);
970 p = mem_buffer;
971 space = PAGE_SIZE;
972 }
973 n = snprintf(p, space, "csrow %2d ", csrow);
974 p += n;
975 space -= n;
976
977 for (channel = 0; channel < pvt->maxch; channel++) {
978 dinfo = &pvt->dimm_info[csrow][channel];
979 handle_channel(pvt, csrow, channel, dinfo);
980 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
981 p += n;
982 space -= n;
983 }
984 debugf2("%s\n", mem_buffer);
985 p = mem_buffer;
986 space = PAGE_SIZE;
987 }
988
989 /* Output the last bottom 'boundary' marker */
990 n = snprintf(p, space, "---------------------------"
991 "--------------------------------");
992 p += n;
993 space -= n;
994 debugf2("%s\n", mem_buffer);
995 p = mem_buffer;
996 space = PAGE_SIZE;
997
998 /* now output the 'channel' labels */
999 n = snprintf(p, space, " ");
1000 p += n;
1001 space -= n;
1002 for (channel = 0; channel < pvt->maxch; channel++) {
1003 n = snprintf(p, space, "channel %d | ", channel);
1004 p += n;
1005 space -= n;
1006 }
1007
1008 /* output the last message and free buffer */
1009 debugf2("%s\n", mem_buffer);
1010 kfree(mem_buffer);
1011 }
1012
1013 /*
1014 * i5400_get_mc_regs read in the necessary registers and
1015 * cache locally
1016 *
1017 * Fills in the private data members
1018 */
1019 static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1020 {
1021 struct i5400_pvt *pvt;
1022 u32 actual_tolm;
1023 u16 limit;
1024 int slot_row;
1025 int maxch;
1026 int maxdimmperch;
1027 int way0, way1;
1028
1029 pvt = mci->pvt_info;
1030
1031 pci_read_config_dword(pvt->system_address, AMBASE,
1032 (u32 *) &pvt->ambase);
1033 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1034 ((u32 *) &pvt->ambase) + sizeof(u32));
1035
1036 maxdimmperch = pvt->maxdimmperch;
1037 maxch = pvt->maxch;
1038
1039 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1040 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1041
1042 /* Get the Branch Map regs */
1043 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1044 pvt->tolm >>= 12;
1045 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1046 pvt->tolm);
1047
1048 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1049 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1050 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1051
1052 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1053 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1054
1055 /* Get the MIR[0-1] regs */
1056 limit = (pvt->mir0 >> 4) & 0x0fff;
1057 way0 = pvt->mir0 & 0x1;
1058 way1 = pvt->mir0 & 0x2;
1059 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1060 limit = (pvt->mir1 >> 4) & 0xfff;
1061 way0 = pvt->mir1 & 0x1;
1062 way1 = pvt->mir1 & 0x2;
1063 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1064
1065 /* Get the set of MTR[0-3] regs by each branch */
1066 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++) {
1067 int where = MTR0 + (slot_row * sizeof(u32));
1068
1069 /* Branch 0 set of MTR registers */
1070 pci_read_config_word(pvt->branch_0, where,
1071 &pvt->b0_mtr[slot_row]);
1072
1073 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1074 pvt->b0_mtr[slot_row]);
1075
1076 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1077 pvt->b1_mtr[slot_row] = 0;
1078 continue;
1079 }
1080
1081 /* Branch 1 set of MTR registers */
1082 pci_read_config_word(pvt->branch_1, where,
1083 &pvt->b1_mtr[slot_row]);
1084 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, where,
1085 pvt->b1_mtr[slot_row]);
1086 }
1087
1088 /* Read and dump branch 0's MTRs */
1089 debugf2("\nMemory Technology Registers:\n");
1090 debugf2(" Branch 0:\n");
1091 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
1092 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1093
1094 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1095 &pvt->b0_ambpresent0);
1096 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1097 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1098 &pvt->b0_ambpresent1);
1099 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1100
1101 /* Only if we have 2 branchs (4 channels) */
1102 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1103 pvt->b1_ambpresent0 = 0;
1104 pvt->b1_ambpresent1 = 0;
1105 } else {
1106 /* Read and dump branch 1's MTRs */
1107 debugf2(" Branch 1:\n");
1108 for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
1109 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1110
1111 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1112 &pvt->b1_ambpresent0);
1113 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1114 pvt->b1_ambpresent0);
1115 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1116 &pvt->b1_ambpresent1);
1117 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1118 pvt->b1_ambpresent1);
1119 }
1120
1121 /* Go and determine the size of each DIMM and place in an
1122 * orderly matrix */
1123 calculate_dimm_size(pvt);
1124 }
1125
1126 /*
1127 * i5400_init_csrows Initialize the 'csrows' table within
1128 * the mci control structure with the
1129 * addressing of memory.
1130 *
1131 * return:
1132 * 0 success
1133 * 1 no actual memory found on this MC
1134 */
1135 static int i5400_init_csrows(struct mem_ctl_info *mci)
1136 {
1137 struct i5400_pvt *pvt;
1138 struct csrow_info *p_csrow;
1139 int empty, channel_count;
1140 int max_csrows;
1141 int mtr;
1142 int csrow_megs;
1143 int channel;
1144 int csrow;
1145
1146 pvt = mci->pvt_info;
1147
1148 channel_count = pvt->maxch;
1149 max_csrows = pvt->maxdimmperch * 2;
1150
1151 empty = 1; /* Assume NO memory */
1152
1153 for (csrow = 0; csrow < max_csrows; csrow++) {
1154 p_csrow = &mci->csrows[csrow];
1155
1156 p_csrow->csrow_idx = csrow;
1157
1158 /* use branch 0 for the basis */
1159 mtr = determine_mtr(pvt, csrow, 0);
1160
1161 /* if no DIMMS on this row, continue */
1162 if (!MTR_DIMMS_PRESENT(mtr))
1163 continue;
1164
1165 /* FAKE OUT VALUES, FIXME */
1166 p_csrow->first_page = 0 + csrow * 20;
1167 p_csrow->last_page = 9 + csrow * 20;
1168 p_csrow->page_mask = 0xFFF;
1169
1170 p_csrow->grain = 8;
1171
1172 csrow_megs = 0;
1173 for (channel = 0; channel < pvt->maxch; channel++)
1174 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1175
1176 p_csrow->nr_pages = csrow_megs << 8;
1177
1178 /* Assume DDR2 for now */
1179 p_csrow->mtype = MEM_FB_DDR2;
1180
1181 /* ask what device type on this row */
1182 if (MTR_DRAM_WIDTH(mtr))
1183 p_csrow->dtype = DEV_X8;
1184 else
1185 p_csrow->dtype = DEV_X4;
1186
1187 p_csrow->edac_mode = EDAC_S8ECD8ED;
1188
1189 empty = 0;
1190 }
1191
1192 return empty;
1193 }
1194
1195 /*
1196 * i5400_enable_error_reporting
1197 * Turn on the memory reporting features of the hardware
1198 */
1199 static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
1200 {
1201 struct i5400_pvt *pvt;
1202 u32 fbd_error_mask;
1203
1204 pvt = mci->pvt_info;
1205
1206 /* Read the FBD Error Mask Register */
1207 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1208 &fbd_error_mask);
1209
1210 /* Enable with a '0' */
1211 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1212
1213 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1214 fbd_error_mask);
1215 }
1216
1217 /*
1218 * i5400_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
1219 *
1220 * ask the device how many channels are present and how many CSROWS
1221 * as well
1222 */
1223 static void i5400_get_dimm_and_channel_counts(struct pci_dev *pdev,
1224 int *num_dimms_per_channel,
1225 int *num_channels)
1226 {
1227 u8 value;
1228
1229 /* Need to retrieve just how many channels and dimms per channel are
1230 * supported on this memory controller
1231 */
1232 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1233 *num_dimms_per_channel = (int)value * 2;
1234
1235 pci_read_config_byte(pdev, MAXCH, &value);
1236 *num_channels = (int)value;
1237 }
1238
1239 /*
1240 * i5400_probe1 Probe for ONE instance of device to see if it is
1241 * present.
1242 * return:
1243 * 0 for FOUND a device
1244 * < 0 for error code
1245 */
1246 static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
1247 {
1248 struct mem_ctl_info *mci;
1249 struct i5400_pvt *pvt;
1250 int num_channels;
1251 int num_dimms_per_channel;
1252 int num_csrows;
1253
1254 if (dev_idx >= ARRAY_SIZE(i5400_devs))
1255 return -EINVAL;
1256
1257 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1258 __func__,
1259 pdev->bus->number,
1260 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1261
1262 /* We only are looking for func 0 of the set */
1263 if (PCI_FUNC(pdev->devfn) != 0)
1264 return -ENODEV;
1265
1266 /* Ask the devices for the number of CSROWS and CHANNELS so
1267 * that we can calculate the memory resources, etc
1268 *
1269 * The Chipset will report what it can handle which will be greater
1270 * or equal to what the motherboard manufacturer will implement.
1271 *
1272 * As we don't have a motherboard identification routine to determine
1273 * actual number of slots/dimms per channel, we thus utilize the
1274 * resource as specified by the chipset. Thus, we might have
1275 * have more DIMMs per channel than actually on the mobo, but this
1276 * allows the driver to support upto the chipset max, without
1277 * some fancy mobo determination.
1278 */
1279 i5400_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1280 &num_channels);
1281 num_csrows = num_dimms_per_channel * 2;
1282
1283 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1284 __func__, num_channels, num_dimms_per_channel, num_csrows);
1285
1286 /* allocate a new MC control structure */
1287 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1288
1289 if (mci == NULL)
1290 return -ENOMEM;
1291
1292 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1293
1294 mci->dev = &pdev->dev; /* record ptr to the generic device */
1295
1296 pvt = mci->pvt_info;
1297 pvt->system_address = pdev; /* Record this device in our private */
1298 pvt->maxch = num_channels;
1299 pvt->maxdimmperch = num_dimms_per_channel;
1300
1301 /* 'get' the pci devices we want to reserve for our use */
1302 if (i5400_get_devices(mci, dev_idx))
1303 goto fail0;
1304
1305 /* Time to get serious */
1306 i5400_get_mc_regs(mci); /* retrieve the hardware registers */
1307
1308 mci->mc_idx = 0;
1309 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1310 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1311 mci->edac_cap = EDAC_FLAG_NONE;
1312 mci->mod_name = "i5400_edac.c";
1313 mci->mod_ver = I5400_REVISION;
1314 mci->ctl_name = i5400_devs[dev_idx].ctl_name;
1315 mci->dev_name = pci_name(pdev);
1316 mci->ctl_page_to_phys = NULL;
1317
1318 /* Set the function pointer to an actual operation function */
1319 mci->edac_check = i5400_check_error;
1320
1321 /* initialize the MC control structure 'csrows' table
1322 * with the mapping and control information */
1323 if (i5400_init_csrows(mci)) {
1324 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1325 " because i5400_init_csrows() returned nonzero "
1326 "value\n");
1327 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1328 } else {
1329 debugf1("MC: Enable error reporting now\n");
1330 i5400_enable_error_reporting(mci);
1331 }
1332
1333 /* add this new MC control structure to EDAC's list of MCs */
1334 if (edac_mc_add_mc(mci)) {
1335 debugf0("MC: " __FILE__
1336 ": %s(): failed edac_mc_add_mc()\n", __func__);
1337 /* FIXME: perhaps some code should go here that disables error
1338 * reporting if we just enabled it
1339 */
1340 goto fail1;
1341 }
1342
1343 i5400_clear_error(mci);
1344
1345 /* allocating generic PCI control info */
1346 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1347 if (!i5400_pci) {
1348 printk(KERN_WARNING
1349 "%s(): Unable to create PCI control\n",
1350 __func__);
1351 printk(KERN_WARNING
1352 "%s(): PCI error report via EDAC not setup\n",
1353 __func__);
1354 }
1355
1356 return 0;
1357
1358 /* Error exit unwinding stack */
1359 fail1:
1360
1361 i5400_put_devices(mci);
1362
1363 fail0:
1364 edac_mc_free(mci);
1365 return -ENODEV;
1366 }
1367
1368 /*
1369 * i5400_init_one constructor for one instance of device
1370 *
1371 * returns:
1372 * negative on error
1373 * count (>= 0)
1374 */
1375 static int __devinit i5400_init_one(struct pci_dev *pdev,
1376 const struct pci_device_id *id)
1377 {
1378 int rc;
1379
1380 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1381
1382 /* wake up device */
1383 rc = pci_enable_device(pdev);
1384 if (rc == -EIO)
1385 return rc;
1386
1387 /* now probe and enable the device */
1388 return i5400_probe1(pdev, id->driver_data);
1389 }
1390
1391 /*
1392 * i5400_remove_one destructor for one instance of device
1393 *
1394 */
1395 static void __devexit i5400_remove_one(struct pci_dev *pdev)
1396 {
1397 struct mem_ctl_info *mci;
1398
1399 debugf0(__FILE__ ": %s()\n", __func__);
1400
1401 if (i5400_pci)
1402 edac_pci_release_generic_ctl(i5400_pci);
1403
1404 mci = edac_mc_del_mc(&pdev->dev);
1405 if (!mci)
1406 return;
1407
1408 /* retrieve references to resources, and free those resources */
1409 i5400_put_devices(mci);
1410
1411 edac_mc_free(mci);
1412 }
1413
1414 /*
1415 * pci_device_id table for which devices we are looking for
1416 *
1417 * The "E500P" device is the first device supported.
1418 */
1419 static const struct pci_device_id i5400_pci_tbl[] __devinitdata = {
1420 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
1421 {0,} /* 0 terminated list. */
1422 };
1423
1424 MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);
1425
1426 /*
1427 * i5400_driver pci_driver structure for this module
1428 *
1429 */
1430 static struct pci_driver i5400_driver = {
1431 .name = "i5400_edac",
1432 .probe = i5400_init_one,
1433 .remove = __devexit_p(i5400_remove_one),
1434 .id_table = i5400_pci_tbl,
1435 };
1436
1437 /*
1438 * i5400_init Module entry function
1439 * Try to initialize this module for its devices
1440 */
1441 static int __init i5400_init(void)
1442 {
1443 int pci_rc;
1444
1445 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1446
1447 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1448 opstate_init();
1449
1450 pci_rc = pci_register_driver(&i5400_driver);
1451
1452 return (pci_rc < 0) ? pci_rc : 0;
1453 }
1454
1455 /*
1456 * i5400_exit() Module exit function
1457 * Unregister the driver
1458 */
1459 static void __exit i5400_exit(void)
1460 {
1461 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1462 pci_unregister_driver(&i5400_driver);
1463 }
1464
1465 module_init(i5400_init);
1466 module_exit(i5400_exit);
1467
1468 MODULE_LICENSE("GPL");
1469 MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>");
1470 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1471 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1472 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "
1473 I5400_REVISION);
1474
1475 module_param(edac_op_state, int, 0444);
1476 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
connection oriented routing - ARCHIVE NO UPDATES HERE