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rcv reorder queue bugfix
[cor_2_6_31.git] / drivers / net / qlge / qlge.h
blob6ed5317ab1c09a11d6d71eb05c7046f19cfe9bad
1 /*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7 #ifndef _QLGE_H_
8 #define _QLGE_H_
9
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12
13 /*
14 * General definitions...
15 */
16 #define DRV_NAME "qlge"
17 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
18 #define DRV_VERSION "v1.00.00-b3"
19
20 #define PFX "qlge: "
21 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
22 do { \
23 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
24 ; \
25 else \
26 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
27 "%s: " fmt, __func__, ##args); \
28 } while (0)
29
30 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
31
32 #define QLGE_VENDOR_ID 0x1077
33 #define QLGE_DEVICE_ID_8012 0x8012
34 #define QLGE_DEVICE_ID_8000 0x8000
35 #define MAX_CPUS 8
36 #define MAX_TX_RINGS MAX_CPUS
37 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
38
39 #define NUM_TX_RING_ENTRIES 256
40 #define NUM_RX_RING_ENTRIES 256
41
42 #define NUM_SMALL_BUFFERS 512
43 #define NUM_LARGE_BUFFERS 512
44 #define DB_PAGE_SIZE 4096
45
46 /* Calculate the number of (4k) pages required to
47 * contain a buffer queue of the given length.
48 */
49 #define MAX_DB_PAGES_PER_BQ(x) \
50 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
51 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
52
53 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
54 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
56 #define SMALL_BUFFER_SIZE 256
57 #define LARGE_BUFFER_SIZE PAGE_SIZE
58 #define MAX_SPLIT_SIZE 1023
59 #define QLGE_SB_PAD 32
60
61 #define MAX_CQ 128
62 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
63 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
64 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
65 #define UDELAY_COUNT 3
66 #define UDELAY_DELAY 100
67
68
69 #define TX_DESC_PER_IOCB 8
70 /* The maximum number of frags we handle is based
71 * on PAGE_SIZE...
72 */
73 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
74 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
75 #else /* all other page sizes */
76 #define TX_DESC_PER_OAL 0
77 #endif
78
79 /* MPI test register definitions. This register
80 * is used for determining alternate NIC function's
81 * PCI->func number.
82 */
83 enum {
84 MPI_TEST_FUNC_PORT_CFG = 0x1002,
85 MPI_TEST_NIC1_FUNC_SHIFT = 1,
86 MPI_TEST_NIC2_FUNC_SHIFT = 5,
87 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
88 };
89
90 /*
91 * Processor Address Register (PROC_ADDR) bit definitions.
92 */
93 enum {
94
95 /* Misc. stuff */
96 MAILBOX_COUNT = 16,
97
98 PROC_ADDR_RDY = (1 << 31),
99 PROC_ADDR_R = (1 << 30),
100 PROC_ADDR_ERR = (1 << 29),
101 PROC_ADDR_DA = (1 << 28),
102 PROC_ADDR_FUNC0_MBI = 0x00001180,
103 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
104 PROC_ADDR_FUNC0_CTL = 0x000011a1,
105 PROC_ADDR_FUNC2_MBI = 0x00001280,
106 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
107 PROC_ADDR_FUNC2_CTL = 0x000012a1,
108 PROC_ADDR_MPI_RISC = 0x00000000,
109 PROC_ADDR_MDE = 0x00010000,
110 PROC_ADDR_REGBLOCK = 0x00020000,
111 PROC_ADDR_RISC_REG = 0x00030000,
112 };
113
114 /*
115 * System Register (SYS) bit definitions.
116 */
117 enum {
118 SYS_EFE = (1 << 0),
119 SYS_FAE = (1 << 1),
120 SYS_MDC = (1 << 2),
121 SYS_DST = (1 << 3),
122 SYS_DWC = (1 << 4),
123 SYS_EVW = (1 << 5),
124 SYS_OMP_DLY_MASK = 0x3f000000,
125 /*
126 * There are no values defined as of edit #15.
127 */
128 SYS_ODI = (1 << 14),
129 };
130
131 /*
132 * Reset/Failover Register (RST_FO) bit definitions.
133 */
134 enum {
135 RST_FO_TFO = (1 << 0),
136 RST_FO_RR_MASK = 0x00060000,
137 RST_FO_RR_CQ_CAM = 0x00000000,
138 RST_FO_RR_DROP = 0x00000001,
139 RST_FO_RR_DQ = 0x00000002,
140 RST_FO_RR_RCV_FUNC_CQ = 0x00000003,
141 RST_FO_FRB = (1 << 12),
142 RST_FO_MOP = (1 << 13),
143 RST_FO_REG = (1 << 14),
144 RST_FO_FR = (1 << 15),
145 };
146
147 /*
148 * Function Specific Control Register (FSC) bit definitions.
149 */
150 enum {
151 FSC_DBRST_MASK = 0x00070000,
152 FSC_DBRST_256 = 0x00000000,
153 FSC_DBRST_512 = 0x00000001,
154 FSC_DBRST_768 = 0x00000002,
155 FSC_DBRST_1024 = 0x00000003,
156 FSC_DBL_MASK = 0x00180000,
157 FSC_DBL_DBRST = 0x00000000,
158 FSC_DBL_MAX_PLD = 0x00000008,
159 FSC_DBL_MAX_BRST = 0x00000010,
160 FSC_DBL_128_BYTES = 0x00000018,
161 FSC_EC = (1 << 5),
162 FSC_EPC_MASK = 0x00c00000,
163 FSC_EPC_INBOUND = (1 << 6),
164 FSC_EPC_OUTBOUND = (1 << 7),
165 FSC_VM_PAGESIZE_MASK = 0x07000000,
166 FSC_VM_PAGE_2K = 0x00000100,
167 FSC_VM_PAGE_4K = 0x00000200,
168 FSC_VM_PAGE_8K = 0x00000300,
169 FSC_VM_PAGE_64K = 0x00000600,
170 FSC_SH = (1 << 11),
171 FSC_DSB = (1 << 12),
172 FSC_STE = (1 << 13),
173 FSC_FE = (1 << 15),
174 };
175
176 /*
177 * Host Command Status Register (CSR) bit definitions.
178 */
179 enum {
180 CSR_ERR_STS_MASK = 0x0000003f,
181 /*
182 * There are no valued defined as of edit #15.
183 */
184 CSR_RR = (1 << 8),
185 CSR_HRI = (1 << 9),
186 CSR_RP = (1 << 10),
187 CSR_CMD_PARM_SHIFT = 22,
188 CSR_CMD_NOP = 0x00000000,
189 CSR_CMD_SET_RST = 0x10000000,
190 CSR_CMD_CLR_RST = 0x20000000,
191 CSR_CMD_SET_PAUSE = 0x30000000,
192 CSR_CMD_CLR_PAUSE = 0x40000000,
193 CSR_CMD_SET_H2R_INT = 0x50000000,
194 CSR_CMD_CLR_H2R_INT = 0x60000000,
195 CSR_CMD_PAR_EN = 0x70000000,
196 CSR_CMD_SET_BAD_PAR = 0x80000000,
197 CSR_CMD_CLR_BAD_PAR = 0x90000000,
198 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
199 };
200
201 /*
202 * Configuration Register (CFG) bit definitions.
203 */
204 enum {
205 CFG_LRQ = (1 << 0),
206 CFG_DRQ = (1 << 1),
207 CFG_LR = (1 << 2),
208 CFG_DR = (1 << 3),
209 CFG_LE = (1 << 5),
210 CFG_LCQ = (1 << 6),
211 CFG_DCQ = (1 << 7),
212 CFG_Q_SHIFT = 8,
213 CFG_Q_MASK = 0x7f000000,
214 };
215
216 /*
217 * Status Register (STS) bit definitions.
218 */
219 enum {
220 STS_FE = (1 << 0),
221 STS_PI = (1 << 1),
222 STS_PL0 = (1 << 2),
223 STS_PL1 = (1 << 3),
224 STS_PI0 = (1 << 4),
225 STS_PI1 = (1 << 5),
226 STS_FUNC_ID_MASK = 0x000000c0,
227 STS_FUNC_ID_SHIFT = 6,
228 STS_F0E = (1 << 8),
229 STS_F1E = (1 << 9),
230 STS_F2E = (1 << 10),
231 STS_F3E = (1 << 11),
232 STS_NFE = (1 << 12),
233 };
234
235 /*
236 * Interrupt Enable Register (INTR_EN) bit definitions.
237 */
238 enum {
239 INTR_EN_INTR_MASK = 0x007f0000,
240 INTR_EN_TYPE_MASK = 0x03000000,
241 INTR_EN_TYPE_ENABLE = 0x00000100,
242 INTR_EN_TYPE_DISABLE = 0x00000200,
243 INTR_EN_TYPE_READ = 0x00000300,
244 INTR_EN_IHD = (1 << 13),
245 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
246 INTR_EN_EI = (1 << 14),
247 INTR_EN_EN = (1 << 15),
248 };
249
250 /*
251 * Interrupt Mask Register (INTR_MASK) bit definitions.
252 */
253 enum {
254 INTR_MASK_PI = (1 << 0),
255 INTR_MASK_HL0 = (1 << 1),
256 INTR_MASK_LH0 = (1 << 2),
257 INTR_MASK_HL1 = (1 << 3),
258 INTR_MASK_LH1 = (1 << 4),
259 INTR_MASK_SE = (1 << 5),
260 INTR_MASK_LSC = (1 << 6),
261 INTR_MASK_MC = (1 << 7),
262 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
263 };
264
265 /*
266 * Register (REV_ID) bit definitions.
267 */
268 enum {
269 REV_ID_MASK = 0x0000000f,
270 REV_ID_NICROLL_SHIFT = 0,
271 REV_ID_NICREV_SHIFT = 4,
272 REV_ID_XGROLL_SHIFT = 8,
273 REV_ID_XGREV_SHIFT = 12,
274 REV_ID_CHIPREV_SHIFT = 28,
275 };
276
277 /*
278 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
279 */
280 enum {
281 FRC_ECC_ERR_VW = (1 << 12),
282 FRC_ECC_ERR_VB = (1 << 13),
283 FRC_ECC_ERR_NI = (1 << 14),
284 FRC_ECC_ERR_NO = (1 << 15),
285 FRC_ECC_PFE_SHIFT = 16,
286 FRC_ECC_ERR_DO = (1 << 18),
287 FRC_ECC_P14 = (1 << 19),
288 };
289
290 /*
291 * Error Status Register (ERR_STS) bit definitions.
292 */
293 enum {
294 ERR_STS_NOF = (1 << 0),
295 ERR_STS_NIF = (1 << 1),
296 ERR_STS_DRP = (1 << 2),
297 ERR_STS_XGP = (1 << 3),
298 ERR_STS_FOU = (1 << 4),
299 ERR_STS_FOC = (1 << 5),
300 ERR_STS_FOF = (1 << 6),
301 ERR_STS_FIU = (1 << 7),
302 ERR_STS_FIC = (1 << 8),
303 ERR_STS_FIF = (1 << 9),
304 ERR_STS_MOF = (1 << 10),
305 ERR_STS_TA = (1 << 11),
306 ERR_STS_MA = (1 << 12),
307 ERR_STS_MPE = (1 << 13),
308 ERR_STS_SCE = (1 << 14),
309 ERR_STS_STE = (1 << 15),
310 ERR_STS_FOW = (1 << 16),
311 ERR_STS_UE = (1 << 17),
312 ERR_STS_MCH = (1 << 26),
313 ERR_STS_LOC_SHIFT = 27,
314 };
315
316 /*
317 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
318 */
319 enum {
320 RAM_DBG_ADDR_FW = (1 << 30),
321 RAM_DBG_ADDR_FR = (1 << 31),
322 };
323
324 /*
325 * Semaphore Register (SEM) bit definitions.
326 */
327 enum {
328 /*
329 * Example:
330 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
331 */
332 SEM_CLEAR = 0,
333 SEM_SET = 1,
334 SEM_FORCE = 3,
335 SEM_XGMAC0_SHIFT = 0,
336 SEM_XGMAC1_SHIFT = 2,
337 SEM_ICB_SHIFT = 4,
338 SEM_MAC_ADDR_SHIFT = 6,
339 SEM_FLASH_SHIFT = 8,
340 SEM_PROBE_SHIFT = 10,
341 SEM_RT_IDX_SHIFT = 12,
342 SEM_PROC_REG_SHIFT = 14,
343 SEM_XGMAC0_MASK = 0x00030000,
344 SEM_XGMAC1_MASK = 0x000c0000,
345 SEM_ICB_MASK = 0x00300000,
346 SEM_MAC_ADDR_MASK = 0x00c00000,
347 SEM_FLASH_MASK = 0x03000000,
348 SEM_PROBE_MASK = 0x0c000000,
349 SEM_RT_IDX_MASK = 0x30000000,
350 SEM_PROC_REG_MASK = 0xc0000000,
351 };
352
353 /*
354 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
355 */
356 enum {
357 XGMAC_ADDR_RDY = (1 << 31),
358 XGMAC_ADDR_R = (1 << 30),
359 XGMAC_ADDR_XME = (1 << 29),
360
361 /* XGMAC control registers */
362 PAUSE_SRC_LO = 0x00000100,
363 PAUSE_SRC_HI = 0x00000104,
364 GLOBAL_CFG = 0x00000108,
365 GLOBAL_CFG_RESET = (1 << 0),
366 GLOBAL_CFG_JUMBO = (1 << 6),
367 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
368 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
369 TX_CFG = 0x0000010c,
370 TX_CFG_RESET = (1 << 0),
371 TX_CFG_EN = (1 << 1),
372 TX_CFG_PREAM = (1 << 2),
373 RX_CFG = 0x00000110,
374 RX_CFG_RESET = (1 << 0),
375 RX_CFG_EN = (1 << 1),
376 RX_CFG_PREAM = (1 << 2),
377 FLOW_CTL = 0x0000011c,
378 PAUSE_OPCODE = 0x00000120,
379 PAUSE_TIMER = 0x00000124,
380 PAUSE_FRM_DEST_LO = 0x00000128,
381 PAUSE_FRM_DEST_HI = 0x0000012c,
382 MAC_TX_PARAMS = 0x00000134,
383 MAC_TX_PARAMS_JUMBO = (1 << 31),
384 MAC_TX_PARAMS_SIZE_SHIFT = 16,
385 MAC_RX_PARAMS = 0x00000138,
386 MAC_SYS_INT = 0x00000144,
387 MAC_SYS_INT_MASK = 0x00000148,
388 MAC_MGMT_INT = 0x0000014c,
389 MAC_MGMT_IN_MASK = 0x00000150,
390 EXT_ARB_MODE = 0x000001fc,
391
392 /* XGMAC TX statistics registers */
393 TX_PKTS = 0x00000200,
394 TX_BYTES = 0x00000208,
395 TX_MCAST_PKTS = 0x00000210,
396 TX_BCAST_PKTS = 0x00000218,
397 TX_UCAST_PKTS = 0x00000220,
398 TX_CTL_PKTS = 0x00000228,
399 TX_PAUSE_PKTS = 0x00000230,
400 TX_64_PKT = 0x00000238,
401 TX_65_TO_127_PKT = 0x00000240,
402 TX_128_TO_255_PKT = 0x00000248,
403 TX_256_511_PKT = 0x00000250,
404 TX_512_TO_1023_PKT = 0x00000258,
405 TX_1024_TO_1518_PKT = 0x00000260,
406 TX_1519_TO_MAX_PKT = 0x00000268,
407 TX_UNDERSIZE_PKT = 0x00000270,
408 TX_OVERSIZE_PKT = 0x00000278,
409
410 /* XGMAC statistics control registers */
411 RX_HALF_FULL_DET = 0x000002a0,
412 TX_HALF_FULL_DET = 0x000002a4,
413 RX_OVERFLOW_DET = 0x000002a8,
414 TX_OVERFLOW_DET = 0x000002ac,
415 RX_HALF_FULL_MASK = 0x000002b0,
416 TX_HALF_FULL_MASK = 0x000002b4,
417 RX_OVERFLOW_MASK = 0x000002b8,
418 TX_OVERFLOW_MASK = 0x000002bc,
419 STAT_CNT_CTL = 0x000002c0,
420 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
421 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
422 AUX_RX_HALF_FULL_DET = 0x000002d0,
423 AUX_TX_HALF_FULL_DET = 0x000002d4,
424 AUX_RX_OVERFLOW_DET = 0x000002d8,
425 AUX_TX_OVERFLOW_DET = 0x000002dc,
426 AUX_RX_HALF_FULL_MASK = 0x000002f0,
427 AUX_TX_HALF_FULL_MASK = 0x000002f4,
428 AUX_RX_OVERFLOW_MASK = 0x000002f8,
429 AUX_TX_OVERFLOW_MASK = 0x000002fc,
430
431 /* XGMAC RX statistics registers */
432 RX_BYTES = 0x00000300,
433 RX_BYTES_OK = 0x00000308,
434 RX_PKTS = 0x00000310,
435 RX_PKTS_OK = 0x00000318,
436 RX_BCAST_PKTS = 0x00000320,
437 RX_MCAST_PKTS = 0x00000328,
438 RX_UCAST_PKTS = 0x00000330,
439 RX_UNDERSIZE_PKTS = 0x00000338,
440 RX_OVERSIZE_PKTS = 0x00000340,
441 RX_JABBER_PKTS = 0x00000348,
442 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
443 RX_DROP_EVENTS = 0x00000358,
444 RX_FCERR_PKTS = 0x00000360,
445 RX_ALIGN_ERR = 0x00000368,
446 RX_SYMBOL_ERR = 0x00000370,
447 RX_MAC_ERR = 0x00000378,
448 RX_CTL_PKTS = 0x00000380,
449 RX_PAUSE_PKTS = 0x00000388,
450 RX_64_PKTS = 0x00000390,
451 RX_65_TO_127_PKTS = 0x00000398,
452 RX_128_255_PKTS = 0x000003a0,
453 RX_256_511_PKTS = 0x000003a8,
454 RX_512_TO_1023_PKTS = 0x000003b0,
455 RX_1024_TO_1518_PKTS = 0x000003b8,
456 RX_1519_TO_MAX_PKTS = 0x000003c0,
457 RX_LEN_ERR_PKTS = 0x000003c8,
458
459 /* XGMAC MDIO control registers */
460 MDIO_TX_DATA = 0x00000400,
461 MDIO_RX_DATA = 0x00000410,
462 MDIO_CMD = 0x00000420,
463 MDIO_PHY_ADDR = 0x00000430,
464 MDIO_PORT = 0x00000440,
465 MDIO_STATUS = 0x00000450,
466
467 /* XGMAC AUX statistics registers */
468 };
469
470 /*
471 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
472 */
473 enum {
474 ETS_QUEUE_SHIFT = 29,
475 ETS_REF = (1 << 26),
476 ETS_RS = (1 << 27),
477 ETS_P = (1 << 28),
478 ETS_FC_COS_SHIFT = 23,
479 };
480
481 /*
482 * Flash Address Register (FLASH_ADDR) bit definitions.
483 */
484 enum {
485 FLASH_ADDR_RDY = (1 << 31),
486 FLASH_ADDR_R = (1 << 30),
487 FLASH_ADDR_ERR = (1 << 29),
488 };
489
490 /*
491 * Stop CQ Processing Register (CQ_STOP) bit definitions.
492 */
493 enum {
494 CQ_STOP_QUEUE_MASK = (0x007f0000),
495 CQ_STOP_TYPE_MASK = (0x03000000),
496 CQ_STOP_TYPE_START = 0x00000100,
497 CQ_STOP_TYPE_STOP = 0x00000200,
498 CQ_STOP_TYPE_READ = 0x00000300,
499 CQ_STOP_EN = (1 << 15),
500 };
501
502 /*
503 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
504 */
505 enum {
506 MAC_ADDR_IDX_SHIFT = 4,
507 MAC_ADDR_TYPE_SHIFT = 16,
508 MAC_ADDR_TYPE_MASK = 0x000f0000,
509 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
510 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
511 MAC_ADDR_TYPE_VLAN = 0x00020000,
512 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
513 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
514 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
515 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
516 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
517 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
518 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
519 MAC_ADDR_ADR = (1 << 25),
520 MAC_ADDR_RS = (1 << 26),
521 MAC_ADDR_E = (1 << 27),
522 MAC_ADDR_MR = (1 << 30),
523 MAC_ADDR_MW = (1 << 31),
524 MAX_MULTICAST_ENTRIES = 32,
525 };
526
527 /*
528 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
529 */
530 enum {
531 SPLT_HDR_EP = (1 << 31),
532 };
533
534 /*
535 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
536 */
537 enum {
538 FC_RCV_CFG_ECT = (1 << 15),
539 FC_RCV_CFG_DFH = (1 << 20),
540 FC_RCV_CFG_DVF = (1 << 21),
541 FC_RCV_CFG_RCE = (1 << 27),
542 FC_RCV_CFG_RFE = (1 << 28),
543 FC_RCV_CFG_TEE = (1 << 29),
544 FC_RCV_CFG_TCE = (1 << 30),
545 FC_RCV_CFG_TFE = (1 << 31),
546 };
547
548 /*
549 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
550 */
551 enum {
552 NIC_RCV_CFG_PPE = (1 << 0),
553 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
554 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
555 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
556 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
557 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
558 NIC_RCV_CFG_RV = (1 << 3),
559 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
560 NIC_RCV_CFG_DFQ_SHIFT = 8,
561 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
562 };
563
564 /*
565 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
566 */
567 enum {
568 MGMT_RCV_CFG_ARP = (1 << 0),
569 MGMT_RCV_CFG_DHC = (1 << 1),
570 MGMT_RCV_CFG_DHS = (1 << 2),
571 MGMT_RCV_CFG_NP = (1 << 3),
572 MGMT_RCV_CFG_I6N = (1 << 4),
573 MGMT_RCV_CFG_I6R = (1 << 5),
574 MGMT_RCV_CFG_DH6 = (1 << 6),
575 MGMT_RCV_CFG_UD1 = (1 << 7),
576 MGMT_RCV_CFG_UD0 = (1 << 8),
577 MGMT_RCV_CFG_BCT = (1 << 9),
578 MGMT_RCV_CFG_MCT = (1 << 10),
579 MGMT_RCV_CFG_DM = (1 << 11),
580 MGMT_RCV_CFG_RM = (1 << 12),
581 MGMT_RCV_CFG_STL = (1 << 13),
582 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
583 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
584 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
585 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
586 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
587 };
588
589 /*
590 * Routing Index Register (RT_IDX) bit definitions.
591 */
592 enum {
593 RT_IDX_IDX_SHIFT = 8,
594 RT_IDX_TYPE_MASK = 0x000f0000,
595 RT_IDX_TYPE_RT = 0x00000000,
596 RT_IDX_TYPE_RT_INV = 0x00010000,
597 RT_IDX_TYPE_NICQ = 0x00020000,
598 RT_IDX_TYPE_NICQ_INV = 0x00030000,
599 RT_IDX_DST_MASK = 0x00700000,
600 RT_IDX_DST_RSS = 0x00000000,
601 RT_IDX_DST_CAM_Q = 0x00100000,
602 RT_IDX_DST_COS_Q = 0x00200000,
603 RT_IDX_DST_DFLT_Q = 0x00300000,
604 RT_IDX_DST_DEST_Q = 0x00400000,
605 RT_IDX_RS = (1 << 26),
606 RT_IDX_E = (1 << 27),
607 RT_IDX_MR = (1 << 30),
608 RT_IDX_MW = (1 << 31),
609
610 /* Nic Queue format - type 2 bits */
611 RT_IDX_BCAST = (1 << 0),
612 RT_IDX_MCAST = (1 << 1),
613 RT_IDX_MCAST_MATCH = (1 << 2),
614 RT_IDX_MCAST_REG_MATCH = (1 << 3),
615 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
616 RT_IDX_FC_MACH = (1 << 5),
617 RT_IDX_ETH_FCOE = (1 << 6),
618 RT_IDX_CAM_HIT = (1 << 7),
619 RT_IDX_CAM_BIT0 = (1 << 8),
620 RT_IDX_CAM_BIT1 = (1 << 9),
621 RT_IDX_VLAN_TAG = (1 << 10),
622 RT_IDX_VLAN_MATCH = (1 << 11),
623 RT_IDX_VLAN_FILTER = (1 << 12),
624 RT_IDX_ETH_SKIP1 = (1 << 13),
625 RT_IDX_ETH_SKIP2 = (1 << 14),
626 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
627 RT_IDX_802_3 = (1 << 16),
628 RT_IDX_LLDP = (1 << 17),
629 RT_IDX_UNUSED018 = (1 << 18),
630 RT_IDX_UNUSED019 = (1 << 19),
631 RT_IDX_UNUSED20 = (1 << 20),
632 RT_IDX_UNUSED21 = (1 << 21),
633 RT_IDX_ERR = (1 << 22),
634 RT_IDX_VALID = (1 << 23),
635 RT_IDX_TU_CSUM_ERR = (1 << 24),
636 RT_IDX_IP_CSUM_ERR = (1 << 25),
637 RT_IDX_MAC_ERR = (1 << 26),
638 RT_IDX_RSS_TCP6 = (1 << 27),
639 RT_IDX_RSS_TCP4 = (1 << 28),
640 RT_IDX_RSS_IPV6 = (1 << 29),
641 RT_IDX_RSS_IPV4 = (1 << 30),
642 RT_IDX_RSS_MATCH = (1 << 31),
643
644 /* Hierarchy for the NIC Queue Mask */
645 RT_IDX_ALL_ERR_SLOT = 0,
646 RT_IDX_MAC_ERR_SLOT = 0,
647 RT_IDX_IP_CSUM_ERR_SLOT = 1,
648 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
649 RT_IDX_BCAST_SLOT = 3,
650 RT_IDX_MCAST_MATCH_SLOT = 4,
651 RT_IDX_ALLMULTI_SLOT = 5,
652 RT_IDX_UNUSED6_SLOT = 6,
653 RT_IDX_UNUSED7_SLOT = 7,
654 RT_IDX_RSS_MATCH_SLOT = 8,
655 RT_IDX_RSS_IPV4_SLOT = 8,
656 RT_IDX_RSS_IPV6_SLOT = 9,
657 RT_IDX_RSS_TCP4_SLOT = 10,
658 RT_IDX_RSS_TCP6_SLOT = 11,
659 RT_IDX_CAM_HIT_SLOT = 12,
660 RT_IDX_UNUSED013 = 13,
661 RT_IDX_UNUSED014 = 14,
662 RT_IDX_PROMISCUOUS_SLOT = 15,
663 RT_IDX_MAX_SLOTS = 16,
664 };
665
666 /*
667 * Control Register Set Map
668 */
669 enum {
670 PROC_ADDR = 0, /* Use semaphore */
671 PROC_DATA = 0x04, /* Use semaphore */
672 SYS = 0x08,
673 RST_FO = 0x0c,
674 FSC = 0x10,
675 CSR = 0x14,
676 LED = 0x18,
677 ICB_RID = 0x1c, /* Use semaphore */
678 ICB_L = 0x20, /* Use semaphore */
679 ICB_H = 0x24, /* Use semaphore */
680 CFG = 0x28,
681 BIOS_ADDR = 0x2c,
682 STS = 0x30,
683 INTR_EN = 0x34,
684 INTR_MASK = 0x38,
685 ISR1 = 0x3c,
686 ISR2 = 0x40,
687 ISR3 = 0x44,
688 ISR4 = 0x48,
689 REV_ID = 0x4c,
690 FRC_ECC_ERR = 0x50,
691 ERR_STS = 0x54,
692 RAM_DBG_ADDR = 0x58,
693 RAM_DBG_DATA = 0x5c,
694 ECC_ERR_CNT = 0x60,
695 SEM = 0x64,
696 GPIO_1 = 0x68, /* Use semaphore */
697 GPIO_2 = 0x6c, /* Use semaphore */
698 GPIO_3 = 0x70, /* Use semaphore */
699 RSVD2 = 0x74,
700 XGMAC_ADDR = 0x78, /* Use semaphore */
701 XGMAC_DATA = 0x7c, /* Use semaphore */
702 NIC_ETS = 0x80,
703 CNA_ETS = 0x84,
704 FLASH_ADDR = 0x88, /* Use semaphore */
705 FLASH_DATA = 0x8c, /* Use semaphore */
706 CQ_STOP = 0x90,
707 PAGE_TBL_RID = 0x94,
708 WQ_PAGE_TBL_LO = 0x98,
709 WQ_PAGE_TBL_HI = 0x9c,
710 CQ_PAGE_TBL_LO = 0xa0,
711 CQ_PAGE_TBL_HI = 0xa4,
712 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
713 MAC_ADDR_DATA = 0xac, /* Use semaphore */
714 COS_DFLT_CQ1 = 0xb0,
715 COS_DFLT_CQ2 = 0xb4,
716 ETYPE_SKIP1 = 0xb8,
717 ETYPE_SKIP2 = 0xbc,
718 SPLT_HDR = 0xc0,
719 FC_PAUSE_THRES = 0xc4,
720 NIC_PAUSE_THRES = 0xc8,
721 FC_ETHERTYPE = 0xcc,
722 FC_RCV_CFG = 0xd0,
723 NIC_RCV_CFG = 0xd4,
724 FC_COS_TAGS = 0xd8,
725 NIC_COS_TAGS = 0xdc,
726 MGMT_RCV_CFG = 0xe0,
727 RT_IDX = 0xe4,
728 RT_DATA = 0xe8,
729 RSVD7 = 0xec,
730 XG_SERDES_ADDR = 0xf0,
731 XG_SERDES_DATA = 0xf4,
732 PRB_MX_ADDR = 0xf8, /* Use semaphore */
733 PRB_MX_DATA = 0xfc, /* Use semaphore */
734 };
735
736 /*
737 * CAM output format.
738 */
739 enum {
740 CAM_OUT_ROUTE_FC = 0,
741 CAM_OUT_ROUTE_NIC = 1,
742 CAM_OUT_FUNC_SHIFT = 2,
743 CAM_OUT_RV = (1 << 4),
744 CAM_OUT_SH = (1 << 15),
745 CAM_OUT_CQ_ID_SHIFT = 5,
746 };
747
748 /*
749 * Mailbox definitions
750 */
751 enum {
752 /* Asynchronous Event Notifications */
753 AEN_SYS_ERR = 0x00008002,
754 AEN_LINK_UP = 0x00008011,
755 AEN_LINK_DOWN = 0x00008012,
756 AEN_IDC_CMPLT = 0x00008100,
757 AEN_IDC_REQ = 0x00008101,
758 AEN_IDC_EXT = 0x00008102,
759 AEN_DCBX_CHG = 0x00008110,
760 AEN_AEN_LOST = 0x00008120,
761 AEN_AEN_SFP_IN = 0x00008130,
762 AEN_AEN_SFP_OUT = 0x00008131,
763 AEN_FW_INIT_DONE = 0x00008400,
764 AEN_FW_INIT_FAIL = 0x00008401,
765
766 /* Mailbox Command Opcodes. */
767 MB_CMD_NOP = 0x00000000,
768 MB_CMD_EX_FW = 0x00000002,
769 MB_CMD_MB_TEST = 0x00000006,
770 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
771 MB_CMD_ABOUT_FW = 0x00000008,
772 MB_CMD_COPY_RISC_RAM = 0x0000000a,
773 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
774 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
775 MB_CMD_WRITE_RAM = 0x0000000d,
776 MB_CMD_INIT_RISC_RAM = 0x0000000e,
777 MB_CMD_READ_RAM = 0x0000000f,
778 MB_CMD_STOP_FW = 0x00000014,
779 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
780 MB_CMD_WRITE_SFP = 0x00000030,
781 MB_CMD_READ_SFP = 0x00000031,
782 MB_CMD_INIT_FW = 0x00000060,
783 MB_CMD_GET_IFCB = 0x00000061,
784 MB_CMD_GET_FW_STATE = 0x00000069,
785 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
786 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
787 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
788 MB_WOL_DISABLE = 0,
789 MB_WOL_MAGIC_PKT = (1 << 1),
790 MB_WOL_FLTR = (1 << 2),
791 MB_WOL_UCAST = (1 << 3),
792 MB_WOL_MCAST = (1 << 4),
793 MB_WOL_BCAST = (1 << 5),
794 MB_WOL_LINK_UP = (1 << 6),
795 MB_WOL_LINK_DOWN = (1 << 7),
796 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
797 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
798 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
799 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
800 MB_CMD_SET_WOL_IMMED = 0x00000115,
801 MB_CMD_PORT_RESET = 0x00000120,
802 MB_CMD_SET_PORT_CFG = 0x00000122,
803 MB_CMD_GET_PORT_CFG = 0x00000123,
804 MB_CMD_GET_LINK_STS = 0x00000124,
805
806 /* Mailbox Command Status. */
807 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
808 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
809 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
810 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
811 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
812 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
813 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
814 };
815
816 struct mbox_params {
817 u32 mbox_in[MAILBOX_COUNT];
818 u32 mbox_out[MAILBOX_COUNT];
819 int in_count;
820 int out_count;
821 };
822
823 struct flash_params_8012 {
824 u8 dev_id_str[4];
825 __le16 size;
826 __le16 csum;
827 __le16 ver;
828 __le16 sub_dev_id;
829 u8 mac_addr[6];
830 __le16 res;
831 };
832
833 /* 8000 device's flash is a different structure
834 * at a different offset in flash.
835 */
836 #define FUNC0_FLASH_OFFSET 0x140200
837 #define FUNC1_FLASH_OFFSET 0x140600
838
839 /* Flash related data structures. */
840 struct flash_params_8000 {
841 u8 dev_id_str[4]; /* "8000" */
842 __le16 ver;
843 __le16 size;
844 __le16 csum;
845 __le16 reserved0;
846 __le16 total_size;
847 __le16 entry_count;
848 u8 data_type0;
849 u8 data_size0;
850 u8 mac_addr[6];
851 u8 data_type1;
852 u8 data_size1;
853 u8 mac_addr1[6];
854 u8 data_type2;
855 u8 data_size2;
856 __le16 vlan_id;
857 u8 data_type3;
858 u8 data_size3;
859 __le16 last;
860 u8 reserved1[464];
861 __le16 subsys_ven_id;
862 __le16 subsys_dev_id;
863 u8 reserved2[4];
864 };
865
866 union flash_params {
867 struct flash_params_8012 flash_params_8012;
868 struct flash_params_8000 flash_params_8000;
869 };
870
871 /*
872 * doorbell space for the rx ring context
873 */
874 struct rx_doorbell_context {
875 u32 cnsmr_idx; /* 0x00 */
876 u32 valid; /* 0x04 */
877 u32 reserved[4]; /* 0x08-0x14 */
878 u32 lbq_prod_idx; /* 0x18 */
879 u32 sbq_prod_idx; /* 0x1c */
880 };
881
882 /*
883 * doorbell space for the tx ring context
884 */
885 struct tx_doorbell_context {
886 u32 prod_idx; /* 0x00 */
887 u32 valid; /* 0x04 */
888 u32 reserved[4]; /* 0x08-0x14 */
889 u32 lbq_prod_idx; /* 0x18 */
890 u32 sbq_prod_idx; /* 0x1c */
891 };
892
893 /* DATA STRUCTURES SHARED WITH HARDWARE. */
894 struct tx_buf_desc {
895 __le64 addr;
896 __le32 len;
897 #define TX_DESC_LEN_MASK 0x000fffff
898 #define TX_DESC_C 0x40000000
899 #define TX_DESC_E 0x80000000
900 } __attribute((packed));
901
902 /*
903 * IOCB Definitions...
904 */
905
906 #define OPCODE_OB_MAC_IOCB 0x01
907 #define OPCODE_OB_MAC_TSO_IOCB 0x02
908 #define OPCODE_IB_MAC_IOCB 0x20
909 #define OPCODE_IB_MPI_IOCB 0x21
910 #define OPCODE_IB_AE_IOCB 0x3f
911
912 struct ob_mac_iocb_req {
913 u8 opcode;
914 u8 flags1;
915 #define OB_MAC_IOCB_REQ_OI 0x01
916 #define OB_MAC_IOCB_REQ_I 0x02
917 #define OB_MAC_IOCB_REQ_D 0x08
918 #define OB_MAC_IOCB_REQ_F 0x10
919 u8 flags2;
920 u8 flags3;
921 #define OB_MAC_IOCB_DFP 0x02
922 #define OB_MAC_IOCB_V 0x04
923 __le32 reserved1[2];
924 __le16 frame_len;
925 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
926 __le16 reserved2;
927 u32 tid;
928 u32 txq_idx;
929 __le32 reserved3;
930 __le16 vlan_tci;
931 __le16 reserved4;
932 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
933 } __attribute((packed));
934
935 struct ob_mac_iocb_rsp {
936 u8 opcode; /* */
937 u8 flags1; /* */
938 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
939 #define OB_MAC_IOCB_RSP_I 0x02 /* */
940 #define OB_MAC_IOCB_RSP_E 0x08 /* */
941 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
942 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
943 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
944 u8 flags2; /* */
945 u8 flags3; /* */
946 #define OB_MAC_IOCB_RSP_B 0x80 /* */
947 u32 tid;
948 u32 txq_idx;
949 __le32 reserved[13];
950 } __attribute((packed));
951
952 struct ob_mac_tso_iocb_req {
953 u8 opcode;
954 u8 flags1;
955 #define OB_MAC_TSO_IOCB_OI 0x01
956 #define OB_MAC_TSO_IOCB_I 0x02
957 #define OB_MAC_TSO_IOCB_D 0x08
958 #define OB_MAC_TSO_IOCB_IP4 0x40
959 #define OB_MAC_TSO_IOCB_IP6 0x80
960 u8 flags2;
961 #define OB_MAC_TSO_IOCB_LSO 0x20
962 #define OB_MAC_TSO_IOCB_UC 0x40
963 #define OB_MAC_TSO_IOCB_TC 0x80
964 u8 flags3;
965 #define OB_MAC_TSO_IOCB_IC 0x01
966 #define OB_MAC_TSO_IOCB_DFP 0x02
967 #define OB_MAC_TSO_IOCB_V 0x04
968 __le32 reserved1[2];
969 __le32 frame_len;
970 u32 tid;
971 u32 txq_idx;
972 __le16 total_hdrs_len;
973 __le16 net_trans_offset;
974 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
975 __le16 vlan_tci;
976 __le16 mss;
977 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
978 } __attribute((packed));
979
980 struct ob_mac_tso_iocb_rsp {
981 u8 opcode;
982 u8 flags1;
983 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
984 #define OB_MAC_TSO_IOCB_RSP_I 0x02
985 #define OB_MAC_TSO_IOCB_RSP_E 0x08
986 #define OB_MAC_TSO_IOCB_RSP_S 0x10
987 #define OB_MAC_TSO_IOCB_RSP_L 0x20
988 #define OB_MAC_TSO_IOCB_RSP_P 0x40
989 u8 flags2; /* */
990 u8 flags3; /* */
991 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
992 u32 tid;
993 u32 txq_idx;
994 __le32 reserved2[13];
995 } __attribute((packed));
996
997 struct ib_mac_iocb_rsp {
998 u8 opcode; /* 0x20 */
999 u8 flags1;
1000 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1001 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1002 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1003 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1004 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1005 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1006 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1007 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1008 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1009 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1010 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1011 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1012 u8 flags2;
1013 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1014 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1015 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1016 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1017 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1018 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1019 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1020 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1021 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1022 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1023 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1024 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1025 u8 flags3;
1026 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1027 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1028 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1029 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1030 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1031 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1032 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1033 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1034 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1035 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1036 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1037 __le32 data_len; /* */
1038 __le64 data_addr; /* */
1039 __le32 rss; /* */
1040 __le16 vlan_id; /* 12 bits */
1041 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1042 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1043 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1044
1045 __le16 reserved1;
1046 __le32 reserved2[6];
1047 u8 reserved3[3];
1048 u8 flags4;
1049 #define IB_MAC_IOCB_RSP_HV 0x20
1050 #define IB_MAC_IOCB_RSP_HS 0x40
1051 #define IB_MAC_IOCB_RSP_HL 0x80
1052 __le32 hdr_len; /* */
1053 __le64 hdr_addr; /* */
1054 } __attribute((packed));
1055
1056 struct ib_ae_iocb_rsp {
1057 u8 opcode;
1058 u8 flags1;
1059 #define IB_AE_IOCB_RSP_OI 0x01
1060 #define IB_AE_IOCB_RSP_I 0x02
1061 u8 event;
1062 #define LINK_UP_EVENT 0x00
1063 #define LINK_DOWN_EVENT 0x01
1064 #define CAM_LOOKUP_ERR_EVENT 0x06
1065 #define SOFT_ECC_ERROR_EVENT 0x07
1066 #define MGMT_ERR_EVENT 0x08
1067 #define TEN_GIG_MAC_EVENT 0x09
1068 #define GPI0_H2L_EVENT 0x10
1069 #define GPI0_L2H_EVENT 0x20
1070 #define GPI1_H2L_EVENT 0x11
1071 #define GPI1_L2H_EVENT 0x21
1072 #define PCI_ERR_ANON_BUF_RD 0x40
1073 u8 q_id;
1074 __le32 reserved[15];
1075 } __attribute((packed));
1076
1077 /*
1078 * These three structures are for generic
1079 * handling of ib and ob iocbs.
1080 */
1081 struct ql_net_rsp_iocb {
1082 u8 opcode;
1083 u8 flags0;
1084 __le16 length;
1085 __le32 tid;
1086 __le32 reserved[14];
1087 } __attribute((packed));
1088
1089 struct net_req_iocb {
1090 u8 opcode;
1091 u8 flags0;
1092 __le16 flags1;
1093 __le32 tid;
1094 __le32 reserved1[30];
1095 } __attribute((packed));
1096
1097 /*
1098 * tx ring initialization control block for chip.
1099 * It is defined as:
1100 * "Work Queue Initialization Control Block"
1101 */
1102 struct wqicb {
1103 __le16 len;
1104 #define Q_LEN_V (1 << 4)
1105 #define Q_LEN_CPP_CONT 0x0000
1106 #define Q_LEN_CPP_16 0x0001
1107 #define Q_LEN_CPP_32 0x0002
1108 #define Q_LEN_CPP_64 0x0003
1109 #define Q_LEN_CPP_512 0x0006
1110 __le16 flags;
1111 #define Q_PRI_SHIFT 1
1112 #define Q_FLAGS_LC 0x1000
1113 #define Q_FLAGS_LB 0x2000
1114 #define Q_FLAGS_LI 0x4000
1115 #define Q_FLAGS_LO 0x8000
1116 __le16 cq_id_rss;
1117 #define Q_CQ_ID_RSS_RV 0x8000
1118 __le16 rid;
1119 __le64 addr;
1120 __le64 cnsmr_idx_addr;
1121 } __attribute((packed));
1122
1123 /*
1124 * rx ring initialization control block for chip.
1125 * It is defined as:
1126 * "Completion Queue Initialization Control Block"
1127 */
1128 struct cqicb {
1129 u8 msix_vect;
1130 u8 reserved1;
1131 u8 reserved2;
1132 u8 flags;
1133 #define FLAGS_LV 0x08
1134 #define FLAGS_LS 0x10
1135 #define FLAGS_LL 0x20
1136 #define FLAGS_LI 0x40
1137 #define FLAGS_LC 0x80
1138 __le16 len;
1139 #define LEN_V (1 << 4)
1140 #define LEN_CPP_CONT 0x0000
1141 #define LEN_CPP_32 0x0001
1142 #define LEN_CPP_64 0x0002
1143 #define LEN_CPP_128 0x0003
1144 __le16 rid;
1145 __le64 addr;
1146 __le64 prod_idx_addr;
1147 __le16 pkt_delay;
1148 __le16 irq_delay;
1149 __le64 lbq_addr;
1150 __le16 lbq_buf_size;
1151 __le16 lbq_len; /* entry count */
1152 __le64 sbq_addr;
1153 __le16 sbq_buf_size;
1154 __le16 sbq_len; /* entry count */
1155 } __attribute((packed));
1156
1157 struct ricb {
1158 u8 base_cq;
1159 #define RSS_L4K 0x80
1160 u8 flags;
1161 #define RSS_L6K 0x01
1162 #define RSS_LI 0x02
1163 #define RSS_LB 0x04
1164 #define RSS_LM 0x08
1165 #define RSS_RI4 0x10
1166 #define RSS_RT4 0x20
1167 #define RSS_RI6 0x40
1168 #define RSS_RT6 0x80
1169 __le16 mask;
1170 __le32 hash_cq_id[256];
1171 __le32 ipv6_hash_key[10];
1172 __le32 ipv4_hash_key[4];
1173 } __attribute((packed));
1174
1175 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1176
1177 struct oal {
1178 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1179 };
1180
1181 struct map_list {
1182 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1183 DECLARE_PCI_UNMAP_LEN(maplen);
1184 };
1185
1186 struct tx_ring_desc {
1187 struct sk_buff *skb;
1188 struct ob_mac_iocb_req *queue_entry;
1189 u32 index;
1190 struct oal oal;
1191 struct map_list map[MAX_SKB_FRAGS + 1];
1192 int map_cnt;
1193 struct tx_ring_desc *next;
1194 };
1195
1196 struct bq_desc {
1197 union {
1198 struct page *lbq_page;
1199 struct sk_buff *skb;
1200 } p;
1201 __le64 *addr;
1202 u32 index;
1203 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1204 DECLARE_PCI_UNMAP_LEN(maplen);
1205 };
1206
1207 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1208
1209 struct tx_ring {
1210 /*
1211 * queue info.
1212 */
1213 struct wqicb wqicb; /* structure used to inform chip of new queue */
1214 void *wq_base; /* pci_alloc:virtual addr for tx */
1215 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1216 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1217 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1218 u32 wq_size; /* size in bytes of queue area */
1219 u32 wq_len; /* number of entries in queue */
1220 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1221 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1222 u16 prod_idx; /* current value for prod idx */
1223 u16 cq_id; /* completion (rx) queue for tx completions */
1224 u8 wq_id; /* queue id for this entry */
1225 u8 reserved1[3];
1226 struct tx_ring_desc *q; /* descriptor list for the queue */
1227 spinlock_t lock;
1228 atomic_t tx_count; /* counts down for every outstanding IO */
1229 atomic_t queue_stopped; /* Turns queue off when full. */
1230 struct delayed_work tx_work;
1231 struct ql_adapter *qdev;
1232 };
1233
1234 /*
1235 * Type of inbound queue.
1236 */
1237 enum {
1238 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1239 TX_Q = 3, /* Handles outbound completions. */
1240 RX_Q = 4, /* Handles inbound completions. */
1241 };
1242
1243 struct rx_ring {
1244 struct cqicb cqicb; /* The chip's completion queue init control block. */
1245
1246 /* Completion queue elements. */
1247 void *cq_base;
1248 dma_addr_t cq_base_dma;
1249 u32 cq_size;
1250 u32 cq_len;
1251 u16 cq_id;
1252 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1253 dma_addr_t prod_idx_sh_reg_dma;
1254 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1255 u32 cnsmr_idx; /* current sw idx */
1256 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1257 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1258
1259 /* Large buffer queue elements. */
1260 u32 lbq_len; /* entry count */
1261 u32 lbq_size; /* size in bytes of queue */
1262 u32 lbq_buf_size;
1263 void *lbq_base;
1264 dma_addr_t lbq_base_dma;
1265 void *lbq_base_indirect;
1266 dma_addr_t lbq_base_indirect_dma;
1267 struct bq_desc *lbq; /* array of control blocks */
1268 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1269 u32 lbq_prod_idx; /* current sw prod idx */
1270 u32 lbq_curr_idx; /* next entry we expect */
1271 u32 lbq_clean_idx; /* beginning of new descs */
1272 u32 lbq_free_cnt; /* free buffer desc cnt */
1273
1274 /* Small buffer queue elements. */
1275 u32 sbq_len; /* entry count */
1276 u32 sbq_size; /* size in bytes of queue */
1277 u32 sbq_buf_size;
1278 void *sbq_base;
1279 dma_addr_t sbq_base_dma;
1280 void *sbq_base_indirect;
1281 dma_addr_t sbq_base_indirect_dma;
1282 struct bq_desc *sbq; /* array of control blocks */
1283 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1284 u32 sbq_prod_idx; /* current sw prod idx */
1285 u32 sbq_curr_idx; /* next entry we expect */
1286 u32 sbq_clean_idx; /* beginning of new descs */
1287 u32 sbq_free_cnt; /* free buffer desc cnt */
1288
1289 /* Misc. handler elements. */
1290 u32 type; /* Type of queue, tx, rx, or default. */
1291 u32 irq; /* Which vector this ring is assigned. */
1292 u32 cpu; /* Which CPU this should run on. */
1293 char name[IFNAMSIZ + 5];
1294 struct napi_struct napi;
1295 struct delayed_work rx_work;
1296 u8 reserved;
1297 struct ql_adapter *qdev;
1298 };
1299
1300 /*
1301 * RSS Initialization Control Block
1302 */
1303 struct hash_id {
1304 u8 value[4];
1305 };
1306
1307 struct nic_stats {
1308 /*
1309 * These stats come from offset 200h to 278h
1310 * in the XGMAC register.
1311 */
1312 u64 tx_pkts;
1313 u64 tx_bytes;
1314 u64 tx_mcast_pkts;
1315 u64 tx_bcast_pkts;
1316 u64 tx_ucast_pkts;
1317 u64 tx_ctl_pkts;
1318 u64 tx_pause_pkts;
1319 u64 tx_64_pkt;
1320 u64 tx_65_to_127_pkt;
1321 u64 tx_128_to_255_pkt;
1322 u64 tx_256_511_pkt;
1323 u64 tx_512_to_1023_pkt;
1324 u64 tx_1024_to_1518_pkt;
1325 u64 tx_1519_to_max_pkt;
1326 u64 tx_undersize_pkt;
1327 u64 tx_oversize_pkt;
1328
1329 /*
1330 * These stats come from offset 300h to 3C8h
1331 * in the XGMAC register.
1332 */
1333 u64 rx_bytes;
1334 u64 rx_bytes_ok;
1335 u64 rx_pkts;
1336 u64 rx_pkts_ok;
1337 u64 rx_bcast_pkts;
1338 u64 rx_mcast_pkts;
1339 u64 rx_ucast_pkts;
1340 u64 rx_undersize_pkts;
1341 u64 rx_oversize_pkts;
1342 u64 rx_jabber_pkts;
1343 u64 rx_undersize_fcerr_pkts;
1344 u64 rx_drop_events;
1345 u64 rx_fcerr_pkts;
1346 u64 rx_align_err;
1347 u64 rx_symbol_err;
1348 u64 rx_mac_err;
1349 u64 rx_ctl_pkts;
1350 u64 rx_pause_pkts;
1351 u64 rx_64_pkts;
1352 u64 rx_65_to_127_pkts;
1353 u64 rx_128_255_pkts;
1354 u64 rx_256_511_pkts;
1355 u64 rx_512_to_1023_pkts;
1356 u64 rx_1024_to_1518_pkts;
1357 u64 rx_1519_to_max_pkts;
1358 u64 rx_len_err_pkts;
1359 };
1360
1361 /*
1362 * intr_context structure is used during initialization
1363 * to hook the interrupts. It is also used in a single
1364 * irq environment as a context to the ISR.
1365 */
1366 struct intr_context {
1367 struct ql_adapter *qdev;
1368 u32 intr;
1369 u32 hooked;
1370 u32 intr_en_mask; /* value/mask used to enable this intr */
1371 u32 intr_dis_mask; /* value/mask used to disable this intr */
1372 u32 intr_read_mask; /* value/mask used to read this intr */
1373 char name[IFNAMSIZ * 2];
1374 atomic_t irq_cnt; /* irq_cnt is used in single vector
1375 * environment. It's incremented for each
1376 * irq handler that is scheduled. When each
1377 * handler finishes it decrements irq_cnt and
1378 * enables interrupts if it's zero. */
1379 irq_handler_t handler;
1380 };
1381
1382 /* adapter flags definitions. */
1383 enum {
1384 QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */
1385 QL_LEGACY_ENABLED = (1 << 3),
1386 QL_MSI_ENABLED = (1 << 3),
1387 QL_MSIX_ENABLED = (1 << 4),
1388 QL_DMA64 = (1 << 5),
1389 QL_PROMISCUOUS = (1 << 6),
1390 QL_ALLMULTI = (1 << 7),
1391 QL_PORT_CFG = (1 << 8),
1392 QL_CAM_RT_SET = (1 << 9),
1393 };
1394
1395 /* link_status bit definitions */
1396 enum {
1397 STS_LOOPBACK_MASK = 0x00000700,
1398 STS_LOOPBACK_PCS = 0x00000100,
1399 STS_LOOPBACK_HSS = 0x00000200,
1400 STS_LOOPBACK_EXT = 0x00000300,
1401 STS_PAUSE_MASK = 0x000000c0,
1402 STS_PAUSE_STD = 0x00000040,
1403 STS_PAUSE_PRI = 0x00000080,
1404 STS_SPEED_MASK = 0x00000038,
1405 STS_SPEED_100Mb = 0x00000000,
1406 STS_SPEED_1Gb = 0x00000008,
1407 STS_SPEED_10Gb = 0x00000010,
1408 STS_LINK_TYPE_MASK = 0x00000007,
1409 STS_LINK_TYPE_XFI = 0x00000001,
1410 STS_LINK_TYPE_XAUI = 0x00000002,
1411 STS_LINK_TYPE_XFI_BP = 0x00000003,
1412 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1413 STS_LINK_TYPE_10GBASET = 0x00000005,
1414 };
1415
1416 /* link_config bit definitions */
1417 enum {
1418 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1419 CFG_PAUSE_MASK = 0x00000060,
1420 CFG_PAUSE_STD = 0x00000020,
1421 CFG_PAUSE_PRI = 0x00000040,
1422 CFG_DCBX = 0x00000010,
1423 CFG_LOOPBACK_MASK = 0x00000007,
1424 CFG_LOOPBACK_PCS = 0x00000002,
1425 CFG_LOOPBACK_HSS = 0x00000004,
1426 CFG_LOOPBACK_EXT = 0x00000006,
1427 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
1428 };
1429
1430 struct nic_operations {
1431
1432 int (*get_flash) (struct ql_adapter *);
1433 int (*port_initialize) (struct ql_adapter *);
1434 };
1435
1436 /*
1437 * The main Adapter structure definition.
1438 * This structure has all fields relevant to the hardware.
1439 */
1440 struct ql_adapter {
1441 struct ricb ricb;
1442 unsigned long flags;
1443 u32 wol;
1444
1445 struct nic_stats nic_stats;
1446
1447 struct vlan_group *vlgrp;
1448
1449 /* PCI Configuration information for this device */
1450 struct pci_dev *pdev;
1451 struct net_device *ndev; /* Parent NET device */
1452
1453 /* Hardware information */
1454 u32 chip_rev_id;
1455 u32 fw_rev_id;
1456 u32 func; /* PCI function for this adapter */
1457 u32 alt_func; /* PCI function for alternate adapter */
1458 u32 port; /* Port number this adapter */
1459
1460 spinlock_t adapter_lock;
1461 spinlock_t hw_lock;
1462 spinlock_t stats_lock;
1463
1464 /* PCI Bus Relative Register Addresses */
1465 void __iomem *reg_base;
1466 void __iomem *doorbell_area;
1467 u32 doorbell_area_size;
1468
1469 u32 msg_enable;
1470
1471 /* Page for Shadow Registers */
1472 void *rx_ring_shadow_reg_area;
1473 dma_addr_t rx_ring_shadow_reg_dma;
1474 void *tx_ring_shadow_reg_area;
1475 dma_addr_t tx_ring_shadow_reg_dma;
1476
1477 u32 mailbox_in;
1478 u32 mailbox_out;
1479 struct mbox_params idc_mbc;
1480 struct mutex mpi_mutex;
1481
1482 int tx_ring_size;
1483 int rx_ring_size;
1484 u32 intr_count;
1485 struct msix_entry *msi_x_entry;
1486 struct intr_context intr_context[MAX_RX_RINGS];
1487
1488 int tx_ring_count; /* One per online CPU. */
1489 u32 rss_ring_first_cq_id;/* index of first inbound (rss) rx_ring */
1490 u32 rss_ring_count; /* One per online CPU. */
1491 /*
1492 * rx_ring_count =
1493 * one default queue +
1494 * (CPU count * outbound completion rx_ring) +
1495 * (CPU count * inbound (RSS) completion rx_ring)
1496 */
1497 int rx_ring_count;
1498 int ring_mem_size;
1499 void *ring_mem;
1500
1501 struct rx_ring rx_ring[MAX_RX_RINGS];
1502 struct tx_ring tx_ring[MAX_TX_RINGS];
1503
1504 int rx_csum;
1505 u32 default_rx_queue;
1506
1507 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1508 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1509 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1510 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1511
1512 u32 xg_sem_mask;
1513 u32 port_link_up;
1514 u32 port_init;
1515 u32 link_status;
1516 u32 link_config;
1517 u32 max_frame_size;
1518
1519 union flash_params flash;
1520
1521 struct net_device_stats stats;
1522 struct workqueue_struct *q_workqueue;
1523 struct workqueue_struct *workqueue;
1524 struct delayed_work asic_reset_work;
1525 struct delayed_work mpi_reset_work;
1526 struct delayed_work mpi_work;
1527 struct delayed_work mpi_port_cfg_work;
1528 struct delayed_work mpi_idc_work;
1529 struct completion ide_completion;
1530 struct nic_operations *nic_ops;
1531 u16 device_id;
1532 };
1533
1534 /*
1535 * Typical Register accessor for memory mapped device.
1536 */
1537 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1538 {
1539 return readl(qdev->reg_base + reg);
1540 }
1541
1542 /*
1543 * Typical Register accessor for memory mapped device.
1544 */
1545 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1546 {
1547 writel(val, qdev->reg_base + reg);
1548 }
1549
1550 /*
1551 * Doorbell Registers:
1552 * Doorbell registers are virtual registers in the PCI memory space.
1553 * The space is allocated by the chip during PCI initialization. The
1554 * device driver finds the doorbell address in BAR 3 in PCI config space.
1555 * The registers are used to control outbound and inbound queues. For
1556 * example, the producer index for an outbound queue. Each queue uses
1557 * 1 4k chunk of memory. The lower half of the space is for outbound
1558 * queues. The upper half is for inbound queues.
1559 */
1560 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1561 {
1562 writel(val, addr);
1563 mmiowb();
1564 }
1565
1566 /*
1567 * Shadow Registers:
1568 * Outbound queues have a consumer index that is maintained by the chip.
1569 * Inbound queues have a producer index that is maintained by the chip.
1570 * For lower overhead, these registers are "shadowed" to host memory
1571 * which allows the device driver to track the queue progress without
1572 * PCI reads. When an entry is placed on an inbound queue, the chip will
1573 * update the relevant index register and then copy the value to the
1574 * shadow register in host memory.
1575 */
1576 static inline u32 ql_read_sh_reg(__le32 *addr)
1577 {
1578 u32 reg;
1579 reg = le32_to_cpu(*addr);
1580 rmb();
1581 return reg;
1582 }
1583
1584 extern char qlge_driver_name[];
1585 extern const char qlge_driver_version[];
1586 extern const struct ethtool_ops qlge_ethtool_ops;
1587
1588 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1589 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1590 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1591 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1592 u32 *value);
1593 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1594 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1595 u16 q_id);
1596 void ql_queue_fw_error(struct ql_adapter *qdev);
1597 void ql_mpi_work(struct work_struct *work);
1598 void ql_mpi_reset_work(struct work_struct *work);
1599 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1600 void ql_queue_asic_error(struct ql_adapter *qdev);
1601 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
1602 void ql_set_ethtool_ops(struct net_device *ndev);
1603 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1604 void ql_mpi_idc_work(struct work_struct *work);
1605 void ql_mpi_port_cfg_work(struct work_struct *work);
1606 int ql_mb_get_fw_state(struct ql_adapter *qdev);
1607 int ql_cam_route_initialize(struct ql_adapter *qdev);
1608 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1609 int ql_mb_about_fw(struct ql_adapter *qdev);
1610 void ql_link_on(struct ql_adapter *qdev);
1611 void ql_link_off(struct ql_adapter *qdev);
1612
1613 #if 1
1614 #define QL_ALL_DUMP
1615 #define QL_REG_DUMP
1616 #define QL_DEV_DUMP
1617 #define QL_CB_DUMP
1618 /* #define QL_IB_DUMP */
1619 /* #define QL_OB_DUMP */
1620 #endif
1621
1622 #ifdef QL_REG_DUMP
1623 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1624 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1625 extern void ql_dump_regs(struct ql_adapter *qdev);
1626 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1627 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1628 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1629 #else
1630 #define QL_DUMP_REGS(qdev)
1631 #define QL_DUMP_ROUTE(qdev)
1632 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1633 #endif
1634
1635 #ifdef QL_STAT_DUMP
1636 extern void ql_dump_stat(struct ql_adapter *qdev);
1637 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1638 #else
1639 #define QL_DUMP_STAT(qdev)
1640 #endif
1641
1642 #ifdef QL_DEV_DUMP
1643 extern void ql_dump_qdev(struct ql_adapter *qdev);
1644 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1645 #else
1646 #define QL_DUMP_QDEV(qdev)
1647 #endif
1648
1649 #ifdef QL_CB_DUMP
1650 extern void ql_dump_wqicb(struct wqicb *wqicb);
1651 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1652 extern void ql_dump_ricb(struct ricb *ricb);
1653 extern void ql_dump_cqicb(struct cqicb *cqicb);
1654 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1655 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1656 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1657 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1658 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1659 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1660 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1661 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1662 ql_dump_hw_cb(qdev, size, bit, q_id)
1663 #else
1664 #define QL_DUMP_RICB(ricb)
1665 #define QL_DUMP_WQICB(wqicb)
1666 #define QL_DUMP_TX_RING(tx_ring)
1667 #define QL_DUMP_CQICB(cqicb)
1668 #define QL_DUMP_RX_RING(rx_ring)
1669 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1670 #endif
1671
1672 #ifdef QL_OB_DUMP
1673 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1674 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1675 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1676 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1677 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1678 #else
1679 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1680 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1681 #endif
1682
1683 #ifdef QL_IB_DUMP
1684 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1685 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1686 #else
1687 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1688 #endif
1689
1690 #ifdef QL_ALL_DUMP
1691 extern void ql_dump_all(struct ql_adapter *qdev);
1692 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1693 #else
1694 #define QL_DUMP_ALL(qdev)
1695 #endif
1696
1697 #endif /* _QLGE_H_ */
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