2 * File: arch/blackfin/mach-bf561/smp.c
3 * Author: Philippe Gerum <rpm@xenomai.org>
5 * Copyright 2007 Analog Devices Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see the file COPYING, or write
19 * to the Free Software Foundation, Inc.,
20 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/delay.h>
30 static DEFINE_SPINLOCK(boot_lock
);
32 static cpumask_t cpu_callin_map
;
35 * platform_init_cpus() - Tell the world about how many cores we
36 * have. This is called while setting up the architecture support
37 * (setup_arch()), so don't be too demanding here with respect to
38 * available kernel services.
41 void __init
platform_init_cpus(void)
43 cpu_set(0, cpu_possible_map
); /* CoreA */
44 cpu_set(1, cpu_possible_map
); /* CoreB */
47 void __init
platform_prepare_cpus(unsigned int max_cpus
)
51 len
= &coreb_trampoline_end
- &coreb_trampoline_start
+ 1;
52 BUG_ON(len
> L1_CODE_LENGTH
);
54 dma_memcpy((void *)COREB_L1_CODE_START
, &coreb_trampoline_start
, len
);
56 /* Both cores ought to be present on a bf561! */
57 cpu_set(0, cpu_present_map
); /* CoreA */
58 cpu_set(1, cpu_present_map
); /* CoreB */
60 printk(KERN_INFO
"CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START
);
63 int __init
setup_profiling_timer(unsigned int multiplier
) /* not supported */
68 void __cpuinit
platform_secondary_init(unsigned int cpu
)
72 /* Clone setup for peripheral interrupt sources from CoreA. */
73 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
74 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
77 /* Clone setup for IARs from CoreA. */
78 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
79 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
80 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
81 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
82 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
83 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
84 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
85 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
90 /* Calibrate loops per jiffy value. */
93 /* Store CPU-private information to the cpu_data array. */
94 bfin_setup_cpudata(cpu
);
96 /* We are done with local CPU inits, unblock the boot CPU. */
97 cpu_set(cpu
, cpu_callin_map
);
98 spin_lock(&boot_lock
);
99 spin_unlock(&boot_lock
);
102 int __cpuinit
platform_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
104 unsigned long timeout
;
106 /* CoreB already running?! */
107 BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT
) == 0);
109 printk(KERN_INFO
"Booting Core B.\n");
111 spin_lock(&boot_lock
);
113 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
115 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT
);
118 timeout
= jiffies
+ 1 * HZ
;
119 while (time_before(jiffies
, timeout
)) {
120 if (cpu_isset(cpu
, cpu_callin_map
))
126 spin_unlock(&boot_lock
);
128 return cpu_isset(cpu
, cpu_callin_map
) ? 0 : -ENOSYS
;
131 void __init
platform_request_ipi(irq_handler_t handler
)
135 ret
= request_irq(IRQ_SUPPLE_0
, handler
, IRQF_DISABLED
,
136 "Supplemental Interrupt0", handler
);
138 panic("Cannot request supplemental interrupt 0 for IPI service");
141 void platform_send_ipi(cpumask_t callmap
)
145 for_each_cpu_mask(cpu
, callmap
) {
148 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu
)));
153 void platform_send_ipi_cpu(unsigned int cpu
)
157 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu
)));
161 void platform_clear_ipi(unsigned int cpu
)
165 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu
)));