arch/mips/dec/kn02xa-berr.c

   1 /*
   2  *      linux/arch/mips/dec/kn02xa-berr.c
   3  *
   4  *      Bus error event handling code for 5000-series systems equipped
   5  *      with parity error detection logic, i.e. DECstation/DECsystem
   6  *      5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
   7  *      DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
   8  *      (KN04-CA) systems.
   9  *
  10  *      Copyright (c) 2005  Maciej W. Rozycki
  11  *
  12  *      This program is free software; you can redistribute it and/or
  13  *      modify it under the terms of the GNU General Public License
  14  *      as published by the Free Software Foundation; either version
  15  *      2 of the License, or (at your option) any later version.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22
  23 #include <asm/addrspace.h>
  24 #include <asm/irq_regs.h>
  25 #include <asm/ptrace.h>
  26 #include <asm/system.h>
  27 #include <asm/traps.h>
  28
  29 #include <asm/dec/kn02ca.h>
  30 #include <asm/dec/kn02xa.h>
  31 #include <asm/dec/kn05.h>
  32
  33 static inline void dec_kn02xa_be_ack(void)
  34 {
  35         volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
  36         volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
  37
  38         *mer = KN02CA_MER_INTR;         /* Clear errors; keep the ARC IRQ. */
  39         *mem_intr = 0;                  /* Any write clears the bus IRQ. */
  40         iob();
  41 }
  42
  43 static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
  44                                  int invoker)
  45 {
  46         volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
  47         volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
  48
  49         static const char excstr[] = "exception";
  50         static const char intstr[] = "interrupt";
  51         static const char cpustr[] = "CPU";
  52         static const char mreadstr[] = "memory read";
  53         static const char readstr[] = "read";
  54         static const char writestr[] = "write";
  55         static const char timestr[] = "timeout";
  56         static const char paritystr[] = "parity error";
  57         static const char lanestat[][4] = { " OK", "BAD" };
  58
  59         const char *kind, *agent, *cycle, *event;
  60         unsigned long address;
  61
  62         u32 mer = *kn02xa_mer;
  63         u32 ear = *kn02xa_ear;
  64         int action = MIPS_BE_FATAL;
  65
  66         /* Ack ASAP, so that any subsequent errors get caught. */
  67         dec_kn02xa_be_ack();
  68
  69         kind = invoker ? intstr : excstr;
  70
  71         /* No DMA errors? */
  72         agent = cpustr;
  73
  74         address = ear & KN02XA_EAR_ADDRESS;
  75
  76         /* Low 256MB is decoded as memory, high -- as TC. */
  77         if (address < 0x10000000) {
  78                 cycle = mreadstr;
  79                 event = paritystr;
  80         } else {
  81                 cycle = invoker ? writestr : readstr;
  82                 event = timestr;
  83         }
  84
  85         if (is_fixup)
  86                 action = MIPS_BE_FIXUP;
  87
  88         if (action != MIPS_BE_FIXUP)
  89                 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
  90                         kind, agent, cycle, event, address);
  91
  92         if (action != MIPS_BE_FIXUP && address < 0x10000000)
  93                 printk(KERN_ALERT "  Byte lane status %#3x -- "
  94                        "#3: %s, #2: %s, #1: %s, #0: %s\n",
  95                        (mer & KN02XA_MER_BYTERR) >> 8,
  96                        lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
  97                        lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
  98                        lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
  99                        lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
 100
 101         return action;
 102 }
 103
 104 int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
 105 {
 106         return dec_kn02xa_be_backend(regs, is_fixup, 0);
 107 }
 108
 109 irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id)
 110 {
 111         struct pt_regs *regs = get_irq_regs();
 112         int action = dec_kn02xa_be_backend(regs, 0, 1);
 113
 114         if (action == MIPS_BE_DISCARD)
 115                 return IRQ_HANDLED;
 116
 117         /*
 118          * FIXME: Find the affected processes and kill them, otherwise
 119          * we must die.
 120          *
 121          * The interrupt is asynchronously delivered thus EPC and RA
 122          * may be irrelevant, but are printed for a reference.
 123          */
 124         printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
 125                regs->cp0_epc, regs->regs[31]);
 126         die("Unrecoverable bus error", regs);
 127 }
 128
 129
 130 void __init dec_kn02xa_be_init(void)
 131 {
 132         volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 133
 134         /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
 135         if (current_cpu_type() == CPU_R4000SC)
 136                 *mbcs |= KN4K_MB_CSR_EE;
 137         fast_iob();
 138
 139         /* Clear any leftover errors from the firmware. */
 140         dec_kn02xa_be_ack();
 141 }