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[cor_2_6_31.git] / arch / mips / kernel / cpu-probe.c
blob1abe9905c9c1895ef220bc51f7f4ddf366b5cfad
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19
20 #include <asm/bugs.h>
21 #include <asm/cpu.h>
22 #include <asm/fpu.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
25 #include <asm/watch.h>
26
27 /*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This
30 * points to the function that implements CPU specific wait.
31 * The wait instruction stops the pipeline and reduces the power consumption of
32 * the CPU very much.
33 */
34 void (*cpu_wait)(void) = NULL;
35
36 static void r3081_wait(void)
37 {
38 unsigned long cfg = read_c0_conf();
39 write_c0_conf(cfg | R30XX_CONF_HALT);
40 }
41
42 static void r39xx_wait(void)
43 {
44 local_irq_disable();
45 if (!need_resched())
46 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
47 local_irq_enable();
48 }
49
50 extern void r4k_wait(void);
51
52 /*
53 * This variant is preferable as it allows testing need_resched and going to
54 * sleep depending on the outcome atomically. Unfortunately the "It is
55 * implementation-dependent whether the pipeline restarts when a non-enabled
56 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
57 * using this version a gamble.
58 */
59 void r4k_wait_irqoff(void)
60 {
61 local_irq_disable();
62 if (!need_resched())
63 __asm__(" .set push \n"
64 " .set mips3 \n"
65 " wait \n"
66 " .set pop \n");
67 local_irq_enable();
68 __asm__(" .globl __pastwait \n"
69 "__pastwait: \n");
70 return;
71 }
72
73 /*
74 * The RM7000 variant has to handle erratum 38. The workaround is to not
75 * have any pending stores when the WAIT instruction is executed.
76 */
77 static void rm7k_wait_irqoff(void)
78 {
79 local_irq_disable();
80 if (!need_resched())
81 __asm__(
82 " .set push \n"
83 " .set mips3 \n"
84 " .set noat \n"
85 " mfc0 $1, $12 \n"
86 " sync \n"
87 " mtc0 $1, $12 # stalls until W stage \n"
88 " wait \n"
89 " mtc0 $1, $12 # stalls until W stage \n"
90 " .set pop \n");
91 local_irq_enable();
92 }
93
94 /* The Au1xxx wait is available only if using 32khz counter or
95 * external timer source, but specifically not CP0 Counter. */
96 int allow_au1k_wait;
97
98 static void au1k_wait(void)
99 {
100 if (!allow_au1k_wait)
101 return;
102
103 /* using the wait instruction makes CP0 counter unusable */
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116 }
117
118 static int __initdata nowait = 0;
119
120 static int __init wait_disable(char *s)
121 {
122 nowait = 1;
123
124 return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 void __init check_wait(void)
130 {
131 struct cpuinfo_mips *c = &current_cpu_data;
132
133 if (nowait) {
134 printk("Wait instruction disabled.\n");
135 return;
136 }
137
138 switch (c->cputype) {
139 case CPU_R3081:
140 case CPU_R3081E:
141 cpu_wait = r3081_wait;
142 break;
143 case CPU_TX3927:
144 cpu_wait = r39xx_wait;
145 break;
146 case CPU_R4200:
147 /* case CPU_R4300: */
148 case CPU_R4600:
149 case CPU_R4640:
150 case CPU_R4650:
151 case CPU_R4700:
152 case CPU_R5000:
153 case CPU_R5500:
154 case CPU_NEVADA:
155 case CPU_4KC:
156 case CPU_4KEC:
157 case CPU_4KSC:
158 case CPU_5KC:
159 case CPU_25KF:
160 case CPU_PR4450:
161 case CPU_BCM3302:
162 case CPU_CAVIUM_OCTEON:
163 cpu_wait = r4k_wait;
164 break;
165
166 case CPU_RM7000:
167 cpu_wait = rm7k_wait_irqoff;
168 break;
169
170 case CPU_24K:
171 case CPU_34K:
172 case CPU_1004K:
173 cpu_wait = r4k_wait;
174 if (read_c0_config7() & MIPS_CONF7_WII)
175 cpu_wait = r4k_wait_irqoff;
176 break;
177
178 case CPU_74K:
179 cpu_wait = r4k_wait;
180 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
181 cpu_wait = r4k_wait_irqoff;
182 break;
183
184 case CPU_TX49XX:
185 cpu_wait = r4k_wait_irqoff;
186 break;
187 case CPU_ALCHEMY:
188 cpu_wait = au1k_wait;
189 break;
190 case CPU_20KC:
191 /*
192 * WAIT on Rev1.0 has E1, E2, E3 and E16.
193 * WAIT on Rev2.0 and Rev3.0 has E16.
194 * Rev3.1 WAIT is nop, why bother
195 */
196 if ((c->processor_id & 0xff) <= 0x64)
197 break;
198
199 /*
200 * Another rev is incremeting c0_count at a reduced clock
201 * rate while in WAIT mode. So we basically have the choice
202 * between using the cp0 timer as clocksource or avoiding
203 * the WAIT instruction. Until more details are known,
204 * disable the use of WAIT for 20Kc entirely.
205 cpu_wait = r4k_wait;
206 */
207 break;
208 case CPU_RM9000:
209 if ((c->processor_id & 0x00ff) >= 0x40)
210 cpu_wait = r4k_wait;
211 break;
212 default:
213 break;
214 }
215 }
216
217 static inline void check_errata(void)
218 {
219 struct cpuinfo_mips *c = &current_cpu_data;
220
221 switch (c->cputype) {
222 case CPU_34K:
223 /*
224 * Erratum "RPS May Cause Incorrect Instruction Execution"
225 * This code only handles VPE0, any SMP/SMTC/RTOS code
226 * making use of VPE1 will be responsable for that VPE.
227 */
228 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
229 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
230 break;
231 default:
232 break;
233 }
234 }
235
236 void __init check_bugs32(void)
237 {
238 check_errata();
239 }
240
241 /*
242 * Probe whether cpu has config register by trying to play with
243 * alternate cache bit and see whether it matters.
244 * It's used by cpu_probe to distinguish between R3000A and R3081.
245 */
246 static inline int cpu_has_confreg(void)
247 {
248 #ifdef CONFIG_CPU_R3000
249 extern unsigned long r3k_cache_size(unsigned long);
250 unsigned long size1, size2;
251 unsigned long cfg = read_c0_conf();
252
253 size1 = r3k_cache_size(ST0_ISC);
254 write_c0_conf(cfg ^ R30XX_CONF_AC);
255 size2 = r3k_cache_size(ST0_ISC);
256 write_c0_conf(cfg);
257 return size1 != size2;
258 #else
259 return 0;
260 #endif
261 }
262
263 /*
264 * Get the FPU Implementation/Revision.
265 */
266 static inline unsigned long cpu_get_fpu_id(void)
267 {
268 unsigned long tmp, fpu_id;
269
270 tmp = read_c0_status();
271 __enable_fpu();
272 fpu_id = read_32bit_cp1_register(CP1_REVISION);
273 write_c0_status(tmp);
274 return fpu_id;
275 }
276
277 /*
278 * Check the CPU has an FPU the official way.
279 */
280 static inline int __cpu_has_fpu(void)
281 {
282 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
283 }
284
285 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
286 | MIPS_CPU_COUNTER)
287
288 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
289 {
290 switch (c->processor_id & 0xff00) {
291 case PRID_IMP_R2000:
292 c->cputype = CPU_R2000;
293 __cpu_name[cpu] = "R2000";
294 c->isa_level = MIPS_CPU_ISA_I;
295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
296 MIPS_CPU_NOFPUEX;
297 if (__cpu_has_fpu())
298 c->options |= MIPS_CPU_FPU;
299 c->tlbsize = 64;
300 break;
301 case PRID_IMP_R3000:
302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
303 if (cpu_has_confreg()) {
304 c->cputype = CPU_R3081E;
305 __cpu_name[cpu] = "R3081";
306 } else {
307 c->cputype = CPU_R3000A;
308 __cpu_name[cpu] = "R3000A";
309 }
310 break;
311 } else {
312 c->cputype = CPU_R3000;
313 __cpu_name[cpu] = "R3000";
314 }
315 c->isa_level = MIPS_CPU_ISA_I;
316 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
317 MIPS_CPU_NOFPUEX;
318 if (__cpu_has_fpu())
319 c->options |= MIPS_CPU_FPU;
320 c->tlbsize = 64;
321 break;
322 case PRID_IMP_R4000:
323 if (read_c0_config() & CONF_SC) {
324 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
325 c->cputype = CPU_R4400PC;
326 __cpu_name[cpu] = "R4400PC";
327 } else {
328 c->cputype = CPU_R4000PC;
329 __cpu_name[cpu] = "R4000PC";
330 }
331 } else {
332 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
333 c->cputype = CPU_R4400SC;
334 __cpu_name[cpu] = "R4400SC";
335 } else {
336 c->cputype = CPU_R4000SC;
337 __cpu_name[cpu] = "R4000SC";
338 }
339 }
340
341 c->isa_level = MIPS_CPU_ISA_III;
342 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
343 MIPS_CPU_WATCH | MIPS_CPU_VCE |
344 MIPS_CPU_LLSC;
345 c->tlbsize = 48;
346 break;
347 case PRID_IMP_VR41XX:
348 switch (c->processor_id & 0xf0) {
349 case PRID_REV_VR4111:
350 c->cputype = CPU_VR4111;
351 __cpu_name[cpu] = "NEC VR4111";
352 break;
353 case PRID_REV_VR4121:
354 c->cputype = CPU_VR4121;
355 __cpu_name[cpu] = "NEC VR4121";
356 break;
357 case PRID_REV_VR4122:
358 if ((c->processor_id & 0xf) < 0x3) {
359 c->cputype = CPU_VR4122;
360 __cpu_name[cpu] = "NEC VR4122";
361 } else {
362 c->cputype = CPU_VR4181A;
363 __cpu_name[cpu] = "NEC VR4181A";
364 }
365 break;
366 case PRID_REV_VR4130:
367 if ((c->processor_id & 0xf) < 0x4) {
368 c->cputype = CPU_VR4131;
369 __cpu_name[cpu] = "NEC VR4131";
370 } else {
371 c->cputype = CPU_VR4133;
372 __cpu_name[cpu] = "NEC VR4133";
373 }
374 break;
375 default:
376 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
377 c->cputype = CPU_VR41XX;
378 __cpu_name[cpu] = "NEC Vr41xx";
379 break;
380 }
381 c->isa_level = MIPS_CPU_ISA_III;
382 c->options = R4K_OPTS;
383 c->tlbsize = 32;
384 break;
385 case PRID_IMP_R4300:
386 c->cputype = CPU_R4300;
387 __cpu_name[cpu] = "R4300";
388 c->isa_level = MIPS_CPU_ISA_III;
389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
390 MIPS_CPU_LLSC;
391 c->tlbsize = 32;
392 break;
393 case PRID_IMP_R4600:
394 c->cputype = CPU_R4600;
395 __cpu_name[cpu] = "R4600";
396 c->isa_level = MIPS_CPU_ISA_III;
397 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
398 MIPS_CPU_LLSC;
399 c->tlbsize = 48;
400 break;
401 #if 0
402 case PRID_IMP_R4650:
403 /*
404 * This processor doesn't have an MMU, so it's not
405 * "real easy" to run Linux on it. It is left purely
406 * for documentation. Commented out because it shares
407 * it's c0_prid id number with the TX3900.
408 */
409 c->cputype = CPU_R4650;
410 __cpu_name[cpu] = "R4650";
411 c->isa_level = MIPS_CPU_ISA_III;
412 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
413 c->tlbsize = 48;
414 break;
415 #endif
416 case PRID_IMP_TX39:
417 c->isa_level = MIPS_CPU_ISA_I;
418 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
419
420 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
421 c->cputype = CPU_TX3927;
422 __cpu_name[cpu] = "TX3927";
423 c->tlbsize = 64;
424 } else {
425 switch (c->processor_id & 0xff) {
426 case PRID_REV_TX3912:
427 c->cputype = CPU_TX3912;
428 __cpu_name[cpu] = "TX3912";
429 c->tlbsize = 32;
430 break;
431 case PRID_REV_TX3922:
432 c->cputype = CPU_TX3922;
433 __cpu_name[cpu] = "TX3922";
434 c->tlbsize = 64;
435 break;
436 }
437 }
438 break;
439 case PRID_IMP_R4700:
440 c->cputype = CPU_R4700;
441 __cpu_name[cpu] = "R4700";
442 c->isa_level = MIPS_CPU_ISA_III;
443 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
444 MIPS_CPU_LLSC;
445 c->tlbsize = 48;
446 break;
447 case PRID_IMP_TX49:
448 c->cputype = CPU_TX49XX;
449 __cpu_name[cpu] = "R49XX";
450 c->isa_level = MIPS_CPU_ISA_III;
451 c->options = R4K_OPTS | MIPS_CPU_LLSC;
452 if (!(c->processor_id & 0x08))
453 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
454 c->tlbsize = 48;
455 break;
456 case PRID_IMP_R5000:
457 c->cputype = CPU_R5000;
458 __cpu_name[cpu] = "R5000";
459 c->isa_level = MIPS_CPU_ISA_IV;
460 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
461 MIPS_CPU_LLSC;
462 c->tlbsize = 48;
463 break;
464 case PRID_IMP_R5432:
465 c->cputype = CPU_R5432;
466 __cpu_name[cpu] = "R5432";
467 c->isa_level = MIPS_CPU_ISA_IV;
468 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
469 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
470 c->tlbsize = 48;
471 break;
472 case PRID_IMP_R5500:
473 c->cputype = CPU_R5500;
474 __cpu_name[cpu] = "R5500";
475 c->isa_level = MIPS_CPU_ISA_IV;
476 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
477 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
478 c->tlbsize = 48;
479 break;
480 case PRID_IMP_NEVADA:
481 c->cputype = CPU_NEVADA;
482 __cpu_name[cpu] = "Nevada";
483 c->isa_level = MIPS_CPU_ISA_IV;
484 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
485 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
486 c->tlbsize = 48;
487 break;
488 case PRID_IMP_R6000:
489 c->cputype = CPU_R6000;
490 __cpu_name[cpu] = "R6000";
491 c->isa_level = MIPS_CPU_ISA_II;
492 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
493 MIPS_CPU_LLSC;
494 c->tlbsize = 32;
495 break;
496 case PRID_IMP_R6000A:
497 c->cputype = CPU_R6000A;
498 __cpu_name[cpu] = "R6000A";
499 c->isa_level = MIPS_CPU_ISA_II;
500 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
501 MIPS_CPU_LLSC;
502 c->tlbsize = 32;
503 break;
504 case PRID_IMP_RM7000:
505 c->cputype = CPU_RM7000;
506 __cpu_name[cpu] = "RM7000";
507 c->isa_level = MIPS_CPU_ISA_IV;
508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
509 MIPS_CPU_LLSC;
510 /*
511 * Undocumented RM7000: Bit 29 in the info register of
512 * the RM7000 v2.0 indicates if the TLB has 48 or 64
513 * entries.
514 *
515 * 29 1 => 64 entry JTLB
516 * 0 => 48 entry JTLB
517 */
518 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
519 break;
520 case PRID_IMP_RM9000:
521 c->cputype = CPU_RM9000;
522 __cpu_name[cpu] = "RM9000";
523 c->isa_level = MIPS_CPU_ISA_IV;
524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
525 MIPS_CPU_LLSC;
526 /*
527 * Bit 29 in the info register of the RM9000
528 * indicates if the TLB has 48 or 64 entries.
529 *
530 * 29 1 => 64 entry JTLB
531 * 0 => 48 entry JTLB
532 */
533 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
534 break;
535 case PRID_IMP_R8000:
536 c->cputype = CPU_R8000;
537 __cpu_name[cpu] = "RM8000";
538 c->isa_level = MIPS_CPU_ISA_IV;
539 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
540 MIPS_CPU_FPU | MIPS_CPU_32FPR |
541 MIPS_CPU_LLSC;
542 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
543 break;
544 case PRID_IMP_R10000:
545 c->cputype = CPU_R10000;
546 __cpu_name[cpu] = "R10000";
547 c->isa_level = MIPS_CPU_ISA_IV;
548 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
549 MIPS_CPU_FPU | MIPS_CPU_32FPR |
550 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
551 MIPS_CPU_LLSC;
552 c->tlbsize = 64;
553 break;
554 case PRID_IMP_R12000:
555 c->cputype = CPU_R12000;
556 __cpu_name[cpu] = "R12000";
557 c->isa_level = MIPS_CPU_ISA_IV;
558 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
559 MIPS_CPU_FPU | MIPS_CPU_32FPR |
560 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
561 MIPS_CPU_LLSC;
562 c->tlbsize = 64;
563 break;
564 case PRID_IMP_R14000:
565 c->cputype = CPU_R14000;
566 __cpu_name[cpu] = "R14000";
567 c->isa_level = MIPS_CPU_ISA_IV;
568 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
569 MIPS_CPU_FPU | MIPS_CPU_32FPR |
570 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
571 MIPS_CPU_LLSC;
572 c->tlbsize = 64;
573 break;
574 case PRID_IMP_LOONGSON2:
575 c->cputype = CPU_LOONGSON2;
576 __cpu_name[cpu] = "ICT Loongson-2";
577 c->isa_level = MIPS_CPU_ISA_III;
578 c->options = R4K_OPTS |
579 MIPS_CPU_FPU | MIPS_CPU_LLSC |
580 MIPS_CPU_32FPR;
581 c->tlbsize = 64;
582 break;
583 }
584 }
585
586 static char unknown_isa[] __cpuinitdata = KERN_ERR \
587 "Unsupported ISA type, c0.config0: %d.";
588
589 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
590 {
591 unsigned int config0;
592 int isa;
593
594 config0 = read_c0_config();
595
596 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
597 c->options |= MIPS_CPU_TLB;
598 isa = (config0 & MIPS_CONF_AT) >> 13;
599 switch (isa) {
600 case 0:
601 switch ((config0 & MIPS_CONF_AR) >> 10) {
602 case 0:
603 c->isa_level = MIPS_CPU_ISA_M32R1;
604 break;
605 case 1:
606 c->isa_level = MIPS_CPU_ISA_M32R2;
607 break;
608 default:
609 goto unknown;
610 }
611 break;
612 case 2:
613 switch ((config0 & MIPS_CONF_AR) >> 10) {
614 case 0:
615 c->isa_level = MIPS_CPU_ISA_M64R1;
616 break;
617 case 1:
618 c->isa_level = MIPS_CPU_ISA_M64R2;
619 break;
620 default:
621 goto unknown;
622 }
623 break;
624 default:
625 goto unknown;
626 }
627
628 return config0 & MIPS_CONF_M;
629
630 unknown:
631 panic(unknown_isa, config0);
632 }
633
634 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
635 {
636 unsigned int config1;
637
638 config1 = read_c0_config1();
639
640 if (config1 & MIPS_CONF1_MD)
641 c->ases |= MIPS_ASE_MDMX;
642 if (config1 & MIPS_CONF1_WR)
643 c->options |= MIPS_CPU_WATCH;
644 if (config1 & MIPS_CONF1_CA)
645 c->ases |= MIPS_ASE_MIPS16;
646 if (config1 & MIPS_CONF1_EP)
647 c->options |= MIPS_CPU_EJTAG;
648 if (config1 & MIPS_CONF1_FP) {
649 c->options |= MIPS_CPU_FPU;
650 c->options |= MIPS_CPU_32FPR;
651 }
652 if (cpu_has_tlb)
653 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
654
655 return config1 & MIPS_CONF_M;
656 }
657
658 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
659 {
660 unsigned int config2;
661
662 config2 = read_c0_config2();
663
664 if (config2 & MIPS_CONF2_SL)
665 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
666
667 return config2 & MIPS_CONF_M;
668 }
669
670 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
671 {
672 unsigned int config3;
673
674 config3 = read_c0_config3();
675
676 if (config3 & MIPS_CONF3_SM)
677 c->ases |= MIPS_ASE_SMARTMIPS;
678 if (config3 & MIPS_CONF3_DSP)
679 c->ases |= MIPS_ASE_DSP;
680 if (config3 & MIPS_CONF3_VINT)
681 c->options |= MIPS_CPU_VINT;
682 if (config3 & MIPS_CONF3_VEIC)
683 c->options |= MIPS_CPU_VEIC;
684 if (config3 & MIPS_CONF3_MT)
685 c->ases |= MIPS_ASE_MIPSMT;
686 if (config3 & MIPS_CONF3_ULRI)
687 c->options |= MIPS_CPU_ULRI;
688
689 return config3 & MIPS_CONF_M;
690 }
691
692 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
693 {
694 int ok;
695
696 /* MIPS32 or MIPS64 compliant CPU. */
697 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
698 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
699
700 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
701
702 ok = decode_config0(c); /* Read Config registers. */
703 BUG_ON(!ok); /* Arch spec violation! */
704 if (ok)
705 ok = decode_config1(c);
706 if (ok)
707 ok = decode_config2(c);
708 if (ok)
709 ok = decode_config3(c);
710
711 mips_probe_watch_registers(c);
712 }
713
714 #ifdef CONFIG_CPU_MIPSR2
715 extern void spram_config(void);
716 #else
717 static inline void spram_config(void) {}
718 #endif
719
720 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
721 {
722 decode_configs(c);
723 switch (c->processor_id & 0xff00) {
724 case PRID_IMP_4KC:
725 c->cputype = CPU_4KC;
726 __cpu_name[cpu] = "MIPS 4Kc";
727 break;
728 case PRID_IMP_4KEC:
729 c->cputype = CPU_4KEC;
730 __cpu_name[cpu] = "MIPS 4KEc";
731 break;
732 case PRID_IMP_4KECR2:
733 c->cputype = CPU_4KEC;
734 __cpu_name[cpu] = "MIPS 4KEc";
735 break;
736 case PRID_IMP_4KSC:
737 case PRID_IMP_4KSD:
738 c->cputype = CPU_4KSC;
739 __cpu_name[cpu] = "MIPS 4KSc";
740 break;
741 case PRID_IMP_5KC:
742 c->cputype = CPU_5KC;
743 __cpu_name[cpu] = "MIPS 5Kc";
744 break;
745 case PRID_IMP_20KC:
746 c->cputype = CPU_20KC;
747 __cpu_name[cpu] = "MIPS 20Kc";
748 break;
749 case PRID_IMP_24K:
750 case PRID_IMP_24KE:
751 c->cputype = CPU_24K;
752 __cpu_name[cpu] = "MIPS 24Kc";
753 break;
754 case PRID_IMP_25KF:
755 c->cputype = CPU_25KF;
756 __cpu_name[cpu] = "MIPS 25Kc";
757 break;
758 case PRID_IMP_34K:
759 c->cputype = CPU_34K;
760 __cpu_name[cpu] = "MIPS 34Kc";
761 break;
762 case PRID_IMP_74K:
763 c->cputype = CPU_74K;
764 __cpu_name[cpu] = "MIPS 74Kc";
765 break;
766 case PRID_IMP_1004K:
767 c->cputype = CPU_1004K;
768 __cpu_name[cpu] = "MIPS 1004Kc";
769 break;
770 }
771
772 spram_config();
773 }
774
775 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
776 {
777 decode_configs(c);
778 switch (c->processor_id & 0xff00) {
779 case PRID_IMP_AU1_REV1:
780 case PRID_IMP_AU1_REV2:
781 c->cputype = CPU_ALCHEMY;
782 switch ((c->processor_id >> 24) & 0xff) {
783 case 0:
784 __cpu_name[cpu] = "Au1000";
785 break;
786 case 1:
787 __cpu_name[cpu] = "Au1500";
788 break;
789 case 2:
790 __cpu_name[cpu] = "Au1100";
791 break;
792 case 3:
793 __cpu_name[cpu] = "Au1550";
794 break;
795 case 4:
796 __cpu_name[cpu] = "Au1200";
797 if ((c->processor_id & 0xff) == 2)
798 __cpu_name[cpu] = "Au1250";
799 break;
800 case 5:
801 __cpu_name[cpu] = "Au1210";
802 break;
803 default:
804 __cpu_name[cpu] = "Au1xxx";
805 break;
806 }
807 break;
808 }
809 }
810
811 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
812 {
813 decode_configs(c);
814
815 switch (c->processor_id & 0xff00) {
816 case PRID_IMP_SB1:
817 c->cputype = CPU_SB1;
818 __cpu_name[cpu] = "SiByte SB1";
819 /* FPU in pass1 is known to have issues. */
820 if ((c->processor_id & 0xff) < 0x02)
821 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
822 break;
823 case PRID_IMP_SB1A:
824 c->cputype = CPU_SB1A;
825 __cpu_name[cpu] = "SiByte SB1A";
826 break;
827 }
828 }
829
830 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
831 {
832 decode_configs(c);
833 switch (c->processor_id & 0xff00) {
834 case PRID_IMP_SR71000:
835 c->cputype = CPU_SR71000;
836 __cpu_name[cpu] = "Sandcraft SR71000";
837 c->scache.ways = 8;
838 c->tlbsize = 64;
839 break;
840 }
841 }
842
843 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
844 {
845 decode_configs(c);
846 switch (c->processor_id & 0xff00) {
847 case PRID_IMP_PR4450:
848 c->cputype = CPU_PR4450;
849 __cpu_name[cpu] = "Philips PR4450";
850 c->isa_level = MIPS_CPU_ISA_M32R1;
851 break;
852 }
853 }
854
855 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
856 {
857 decode_configs(c);
858 switch (c->processor_id & 0xff00) {
859 case PRID_IMP_BCM3302:
860 c->cputype = CPU_BCM3302;
861 __cpu_name[cpu] = "Broadcom BCM3302";
862 break;
863 case PRID_IMP_BCM4710:
864 c->cputype = CPU_BCM4710;
865 __cpu_name[cpu] = "Broadcom BCM4710";
866 break;
867 }
868 }
869
870 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
871 {
872 decode_configs(c);
873 switch (c->processor_id & 0xff00) {
874 case PRID_IMP_CAVIUM_CN38XX:
875 case PRID_IMP_CAVIUM_CN31XX:
876 case PRID_IMP_CAVIUM_CN30XX:
877 case PRID_IMP_CAVIUM_CN58XX:
878 case PRID_IMP_CAVIUM_CN56XX:
879 case PRID_IMP_CAVIUM_CN50XX:
880 case PRID_IMP_CAVIUM_CN52XX:
881 c->cputype = CPU_CAVIUM_OCTEON;
882 __cpu_name[cpu] = "Cavium Octeon";
883 break;
884 default:
885 printk(KERN_INFO "Unknown Octeon chip!\n");
886 c->cputype = CPU_UNKNOWN;
887 break;
888 }
889 }
890
891 const char *__cpu_name[NR_CPUS];
892
893 __cpuinit void cpu_probe(void)
894 {
895 struct cpuinfo_mips *c = &current_cpu_data;
896 unsigned int cpu = smp_processor_id();
897
898 c->processor_id = PRID_IMP_UNKNOWN;
899 c->fpu_id = FPIR_IMP_NONE;
900 c->cputype = CPU_UNKNOWN;
901
902 c->processor_id = read_c0_prid();
903 switch (c->processor_id & 0xff0000) {
904 case PRID_COMP_LEGACY:
905 cpu_probe_legacy(c, cpu);
906 break;
907 case PRID_COMP_MIPS:
908 cpu_probe_mips(c, cpu);
909 break;
910 case PRID_COMP_ALCHEMY:
911 cpu_probe_alchemy(c, cpu);
912 break;
913 case PRID_COMP_SIBYTE:
914 cpu_probe_sibyte(c, cpu);
915 break;
916 case PRID_COMP_BROADCOM:
917 cpu_probe_broadcom(c, cpu);
918 break;
919 case PRID_COMP_SANDCRAFT:
920 cpu_probe_sandcraft(c, cpu);
921 break;
922 case PRID_COMP_NXP:
923 cpu_probe_nxp(c, cpu);
924 break;
925 case PRID_COMP_CAVIUM:
926 cpu_probe_cavium(c, cpu);
927 break;
928 }
929
930 BUG_ON(!__cpu_name[cpu]);
931 BUG_ON(c->cputype == CPU_UNKNOWN);
932
933 /*
934 * Platform code can force the cpu type to optimize code
935 * generation. In that case be sure the cpu type is correctly
936 * manually setup otherwise it could trigger some nasty bugs.
937 */
938 BUG_ON(current_cpu_type() != c->cputype);
939
940 if (c->options & MIPS_CPU_FPU) {
941 c->fpu_id = cpu_get_fpu_id();
942
943 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
944 c->isa_level == MIPS_CPU_ISA_M32R2 ||
945 c->isa_level == MIPS_CPU_ISA_M64R1 ||
946 c->isa_level == MIPS_CPU_ISA_M64R2) {
947 if (c->fpu_id & MIPS_FPIR_3D)
948 c->ases |= MIPS_ASE_MIPS3D;
949 }
950 }
951
952 if (cpu_has_mips_r2)
953 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
954 else
955 c->srsets = 1;
956 }
957
958 __cpuinit void cpu_report(void)
959 {
960 struct cpuinfo_mips *c = &current_cpu_data;
961
962 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
963 c->processor_id, cpu_name_string());
964 if (c->options & MIPS_CPU_FPU)
965 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
966 }
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