arch/mips/sibyte/bcm1480/irq.c

   1 /*
   2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/errno.h>
  29 #include <asm/irq_regs.h>
  30 #include <asm/signal.h>
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/sibyte/bcm1480_regs.h>
  35 #include <asm/sibyte/bcm1480_int.h>
  36 #include <asm/sibyte/bcm1480_scd.h>
  37
  38 #include <asm/sibyte/sb1250_uart.h>
  39 #include <asm/sibyte/sb1250.h>
  40
  41 /*
  42  * These are the routines that handle all the low level interrupt stuff.
  43  * Actions handled here are: initialization of the interrupt map, requesting of
  44  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  45  * for interrupt lines
  46  */
  47
  48
  49 static void end_bcm1480_irq(unsigned int irq);
  50 static void enable_bcm1480_irq(unsigned int irq);
  51 static void disable_bcm1480_irq(unsigned int irq);
  52 static void ack_bcm1480_irq(unsigned int irq);
  53 #ifdef CONFIG_SMP
  54 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
  55 #endif
  56
  57 #ifdef CONFIG_PCI
  58 extern unsigned long ht_eoi_space;
  59 #endif
  60
  61 static struct irq_chip bcm1480_irq_type = {
  62         .name = "BCM1480-IMR",
  63         .ack = ack_bcm1480_irq,
  64         .mask = disable_bcm1480_irq,
  65         .mask_ack = ack_bcm1480_irq,
  66         .unmask = enable_bcm1480_irq,
  67         .end = end_bcm1480_irq,
  68 #ifdef CONFIG_SMP
  69         .set_affinity = bcm1480_set_affinity
  70 #endif
  71 };
  72
  73 /* Store the CPU id (not the logical number) */
  74 int bcm1480_irq_owner[BCM1480_NR_IRQS];
  75
  76 DEFINE_SPINLOCK(bcm1480_imr_lock);
  77
  78 void bcm1480_mask_irq(int cpu, int irq)
  79 {
  80         unsigned long flags, hl_spacing;
  81         u64 cur_ints;
  82
  83         spin_lock_irqsave(&bcm1480_imr_lock, flags);
  84         hl_spacing = 0;
  85         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
  86                 hl_spacing = BCM1480_IMR_HL_SPACING;
  87                 irq -= BCM1480_NR_IRQS_HALF;
  88         }
  89         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  90         cur_ints |= (((u64) 1) << irq);
  91         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  92         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
  93 }
  94
  95 void bcm1480_unmask_irq(int cpu, int irq)
  96 {
  97         unsigned long flags, hl_spacing;
  98         u64 cur_ints;
  99
 100         spin_lock_irqsave(&bcm1480_imr_lock, flags);
 101         hl_spacing = 0;
 102         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
 103                 hl_spacing = BCM1480_IMR_HL_SPACING;
 104                 irq -= BCM1480_NR_IRQS_HALF;
 105         }
 106         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 107         cur_ints &= ~(((u64) 1) << irq);
 108         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 109         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 110 }
 111
 112 #ifdef CONFIG_SMP
 113 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
 114 {
 115         int i = 0, old_cpu, cpu, int_on, k;
 116         u64 cur_ints;
 117         unsigned long flags;
 118         unsigned int irq_dirty;
 119
 120         if (cpumask_weight(mask) != 1) {
 121                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 122                 return -1;
 123         }
 124         i = cpumask_first(mask);
 125
 126         /* Convert logical CPU to physical CPU */
 127         cpu = cpu_logical_map(i);
 128
 129         /* Protect against other affinity changers and IMR manipulation */
 130         spin_lock_irqsave(&bcm1480_imr_lock, flags);
 131
 132         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 133         old_cpu = bcm1480_irq_owner[irq];
 134         irq_dirty = irq;
 135         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 136                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 137         }
 138
 139         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
 140                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 141                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
 142                 if (int_on) {
 143                         /* If it was on, mask it */
 144                         cur_ints |= (((u64) 1) << irq_dirty);
 145                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 146                 }
 147                 bcm1480_irq_owner[irq] = cpu;
 148                 if (int_on) {
 149                         /* unmask for the new CPU */
 150                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 151                         cur_ints &= ~(((u64) 1) << irq_dirty);
 152                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 153                 }
 154         }
 155         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 156
 157         return 0;
 158 }
 159 #endif
 160
 161
 162 /*****************************************************************************/
 163
 164 static void disable_bcm1480_irq(unsigned int irq)
 165 {
 166         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 167 }
 168
 169 static void enable_bcm1480_irq(unsigned int irq)
 170 {
 171         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 172 }
 173
 174
 175 static void ack_bcm1480_irq(unsigned int irq)
 176 {
 177         u64 pending;
 178         unsigned int irq_dirty;
 179         int k;
 180
 181         /*
 182          * If the interrupt was an HT interrupt, now is the time to
 183          * clear it.  NOTE: we assume the HT bridge was set up to
 184          * deliver the interrupts to all CPUs (which makes affinity
 185          * changing easier for us)
 186          */
 187         irq_dirty = irq;
 188         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 189                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 190         }
 191         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
 192                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
 193                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
 194                 pending &= ((u64)1 << (irq_dirty));
 195                 if (pending) {
 196 #ifdef CONFIG_SMP
 197                         int i;
 198                         for (i=0; i<NR_CPUS; i++) {
 199                                 /*
 200                                  * Clear for all CPUs so an affinity switch
 201                                  * doesn't find an old status
 202                                  */
 203                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
 204                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 205                         }
 206 #else
 207                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 208 #endif
 209
 210                         /*
 211                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 212                          * Pass 2, the LDT world may be edge-triggered, but
 213                          * this EOI shouldn't hurt.  If they are
 214                          * level-sensitive, the EOI is required.
 215                          */
 216 #ifdef CONFIG_PCI
 217                         if (ht_eoi_space)
 218                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
 219 #endif
 220                 }
 221         }
 222         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 223 }
 224
 225
 226 static void end_bcm1480_irq(unsigned int irq)
 227 {
 228         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 229                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 230         }
 231 }
 232
 233
 234 void __init init_bcm1480_irqs(void)
 235 {
 236         int i;
 237
 238         for (i = 0; i < BCM1480_NR_IRQS; i++) {
 239                 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
 240                 bcm1480_irq_owner[i] = 0;
 241         }
 242 }
 243
 244 /*
 245  *  init_IRQ is called early in the boot sequence from init/main.c.  It
 246  *  is responsible for setting up the interrupt mapper and installing the
 247  *  handler that will be responsible for dispatching interrupts to the
 248  *  "right" place.
 249  */
 250 /*
 251  * For now, map all interrupts to IP[2].  We could save
 252  * some cycles by parceling out system interrupts to different
 253  * IP lines, but keep it simple for bringup.  We'll also direct
 254  * all interrupts to a single CPU; we should probably route
 255  * PCI and LDT to one cpu and everything else to the other
 256  * to balance the load a bit.
 257  *
 258  * On the second cpu, everything is set to IP5, which is
 259  * ignored, EXCEPT the mailbox interrupt.  That one is
 260  * set to IP[2] so it is handled.  This is needed so we
 261  * can do cross-cpu function calls, as requred by SMP
 262  */
 263
 264 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
 265 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
 266 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
 267 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
 268 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
 269
 270 void __init arch_init_irq(void)
 271 {
 272         unsigned int i, cpu;
 273         u64 tmp;
 274         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 275                 STATUSF_IP1 | STATUSF_IP0;
 276
 277         /* Default everything to IP2 */
 278         /* Start with _high registers which has no bit 0 interrupt source */
 279         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
 280                 for (cpu = 0; cpu < 4; cpu++) {
 281                         __raw_writeq(IMR_IP2_VAL,
 282                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 283                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
 284                 }
 285         }
 286
 287         /* Now do _low registers */
 288         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
 289                 for (cpu = 0; cpu < 4; cpu++) {
 290                         __raw_writeq(IMR_IP2_VAL,
 291                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 292                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
 293                 }
 294         }
 295
 296         init_bcm1480_irqs();
 297
 298         /*
 299          * Map the high 16 bits of mailbox_0 registers to IP[3], for
 300          * inter-cpu messages
 301          */
 302         /* Was I1 */
 303         for (cpu = 0; cpu < 4; cpu++) {
 304                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
 305                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
 306         }
 307
 308
 309         /* Clear the mailboxes.  The firmware may leave them dirty */
 310         for (cpu = 0; cpu < 4; cpu++) {
 311                 __raw_writeq(0xffffffffffffffffULL,
 312                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
 313                 __raw_writeq(0xffffffffffffffffULL,
 314                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
 315         }
 316
 317
 318         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
 319         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
 320         for (cpu = 0; cpu < 4; cpu++) {
 321                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
 322         }
 323         tmp = ~((u64) 0);
 324         for (cpu = 0; cpu < 4; cpu++) {
 325                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
 326         }
 327
 328         /*
 329          * Note that the timer interrupts are also mapped, but this is
 330          * done in bcm1480_time_init().  Also, the profiling driver
 331          * does its own management of IP7.
 332          */
 333
 334         /* Enable necessary IPs, disable the rest */
 335         change_c0_status(ST0_IM, imask);
 336 }
 337
 338 extern void bcm1480_mailbox_interrupt(void);
 339
 340 static inline void dispatch_ip2(void)
 341 {
 342         unsigned long long mask_h, mask_l;
 343         unsigned int cpu = smp_processor_id();
 344         unsigned long base;
 345
 346         /*
 347          * Default...we've hit an IP[2] interrupt, which means we've got to
 348          * check the 1480 interrupt registers to figure out what to do.  Need
 349          * to detect which CPU we're on, now that smp_affinity is supported.
 350          */
 351         base = A_BCM1480_IMR_MAPPER(cpu);
 352         mask_h = __raw_readq(
 353                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
 354         mask_l = __raw_readq(
 355                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
 356
 357         if (mask_h) {
 358                 if (mask_h ^ 1)
 359                         do_IRQ(fls64(mask_h) - 1);
 360                 else if (mask_l)
 361                         do_IRQ(63 + fls64(mask_l));
 362         }
 363 }
 364
 365 asmlinkage void plat_irq_dispatch(void)
 366 {
 367         unsigned int cpu = smp_processor_id();
 368         unsigned int pending;
 369
 370 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 371         /* Set compare to count to silence count/compare timer interrupts */
 372         write_c0_compare(read_c0_count());
 373 #endif
 374
 375         pending = read_c0_cause() & read_c0_status();
 376
 377 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 378         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
 379                 sbprof_cpu_intr();
 380         else
 381 #endif
 382
 383         if (pending & CAUSEF_IP4)
 384                 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
 385 #ifdef CONFIG_SMP
 386         else if (pending & CAUSEF_IP3)
 387                 bcm1480_mailbox_interrupt();
 388 #endif
 389
 390         else if (pending & CAUSEF_IP2)
 391                 dispatch_ip2();
 392 }