arch/parisc/kernel/pci.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1997, 1998 Ralf Baechle
   7  * Copyright (C) 1999 SuSE GmbH
   8  * Copyright (C) 1999-2001 Hewlett-Packard Company
   9  * Copyright (C) 1999-2001 Grant Grundler
  10  */
  11 #include <linux/eisa.h>
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/slab.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/io.h>
  20 #include <asm/system.h>
  21 #include <asm/cache.h>          /* for L1_CACHE_BYTES */
  22 #include <asm/superio.h>
  23
  24 #define DEBUG_RESOURCES 0
  25 #define DEBUG_CONFIG 0
  26
  27 #if DEBUG_CONFIG
  28 # define DBGC(x...)     printk(KERN_DEBUG x)
  29 #else
  30 # define DBGC(x...)
  31 #endif
  32
  33
  34 #if DEBUG_RESOURCES
  35 #define DBG_RES(x...)   printk(KERN_DEBUG x)
  36 #else
  37 #define DBG_RES(x...)
  38 #endif
  39
  40 /* To be used as: mdelay(pci_post_reset_delay);
  41  *
  42  * post_reset is the time the kernel should stall to prevent anyone from
  43  * accessing the PCI bus once #RESET is de-asserted.
  44  * PCI spec somewhere says 1 second but with multi-PCI bus systems,
  45  * this makes the boot time much longer than necessary.
  46  * 20ms seems to work for all the HP PCI implementations to date.
  47  *
  48  * #define pci_post_reset_delay 50
  49  */
  50
  51 struct pci_port_ops *pci_port __read_mostly;
  52 struct pci_bios_ops *pci_bios __read_mostly;
  53
  54 static int pci_hba_count __read_mostly;
  55
  56 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data.  */
  57 #define PCI_HBA_MAX 32
  58 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
  59
  60
  61 /********************************************************************
  62 **
  63 ** I/O port space support
  64 **
  65 *********************************************************************/
  66
  67 /* EISA port numbers and PCI port numbers share the same interface.  Some
  68  * machines have both EISA and PCI adapters installed.  Rather than turn
  69  * pci_port into an array, we reserve bus 0 for EISA and call the EISA
  70  * routines if the access is to a port on bus 0.  We don't want to fix
  71  * EISA and ISA drivers which assume port space is <= 0xffff.
  72  */
  73
  74 #ifdef CONFIG_EISA
  75 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
  76 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
  77 #else
  78 #define EISA_IN(size)
  79 #define EISA_OUT(size)
  80 #endif
  81
  82 #define PCI_PORT_IN(type, size) \
  83 u##size in##type (int addr) \
  84 { \
  85         int b = PCI_PORT_HBA(addr); \
  86         EISA_IN(size); \
  87         if (!parisc_pci_hba[b]) return (u##size) -1; \
  88         return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
  89 } \
  90 EXPORT_SYMBOL(in##type);
  91
  92 PCI_PORT_IN(b,  8)
  93 PCI_PORT_IN(w, 16)
  94 PCI_PORT_IN(l, 32)
  95
  96
  97 #define PCI_PORT_OUT(type, size) \
  98 void out##type (u##size d, int addr) \
  99 { \
 100         int b = PCI_PORT_HBA(addr); \
 101         EISA_OUT(size); \
 102         if (!parisc_pci_hba[b]) return; \
 103         pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
 104 } \
 105 EXPORT_SYMBOL(out##type);
 106
 107 PCI_PORT_OUT(b,  8)
 108 PCI_PORT_OUT(w, 16)
 109 PCI_PORT_OUT(l, 32)
 110
 111
 112
 113 /*
 114  * BIOS32 replacement.
 115  */
 116 static int __init pcibios_init(void)
 117 {
 118         if (!pci_bios)
 119                 return -1;
 120
 121         if (pci_bios->init) {
 122                 pci_bios->init();
 123         } else {
 124                 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
 125         }
 126         return 0;
 127 }
 128
 129
 130 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
 131 void pcibios_fixup_bus(struct pci_bus *bus)
 132 {
 133         if (pci_bios->fixup_bus) {
 134                 pci_bios->fixup_bus(bus);
 135         } else {
 136                 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
 137         }
 138 }
 139
 140
 141 char *pcibios_setup(char *str)
 142 {
 143         return str;
 144 }
 145
 146 /*
 147  * Called by pci_set_master() - a driver interface.
 148  *
 149  * Legacy PDC guarantees to set:
 150  *      Map Memory BAR's into PA IO space.
 151  *      Map Expansion ROM BAR into one common PA IO space per bus.
 152  *      Map IO BAR's into PCI IO space.
 153  *      Command (see below)
 154  *      Cache Line Size
 155  *      Latency Timer
 156  *      Interrupt Line
 157  *      PPB: secondary latency timer, io/mmio base/limit,
 158  *              bus numbers, bridge control
 159  *
 160  */
 161 void pcibios_set_master(struct pci_dev *dev)
 162 {
 163         u8 lat;
 164
 165         /* If someone already mucked with this, don't touch it. */
 166         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 167         if (lat >= 16) return;
 168
 169         /*
 170         ** HP generally has fewer devices on the bus than other architectures.
 171         ** upper byte is PCI_LATENCY_TIMER.
 172         */
 173         pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
 174                                 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
 175 }
 176
 177
 178 void __init pcibios_init_bus(struct pci_bus *bus)
 179 {
 180         struct pci_dev *dev = bus->self;
 181         unsigned short bridge_ctl;
 182
 183         /* We deal only with pci controllers and pci-pci bridges. */
 184         if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 185                 return;
 186
 187         /* PCI-PCI bridge - set the cache line and default latency
 188            (32) for primary and secondary buses. */
 189         pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
 190
 191         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
 192         bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
 193         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
 194 }
 195
 196 /* called by drivers/pci/setup-bus.c:pci_setup_bridge().  */
 197 void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
 198                 struct pci_bus_region *region, struct resource *res)
 199 {
 200 #ifdef CONFIG_64BIT
 201         struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
 202 #endif
 203
 204         if (res->flags & IORESOURCE_IO) {
 205                 /*
 206                 ** I/O space may see busnumbers here. Something
 207                 ** in the form of 0xbbxxxx where bb is the bus num
 208                 ** and xxxx is the I/O port space address.
 209                 ** Remaining address translation are done in the
 210                 ** PCI Host adapter specific code - ie dino_out8.
 211                 */
 212                 region->start = PCI_PORT_ADDR(res->start);
 213                 region->end   = PCI_PORT_ADDR(res->end);
 214         } else if (res->flags & IORESOURCE_MEM) {
 215                 /* Convert MMIO addr to PCI addr (undo global virtualization) */
 216                 region->start = PCI_BUS_ADDR(hba, res->start);
 217                 region->end   = PCI_BUS_ADDR(hba, res->end);
 218         }
 219
 220         DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
 221                 dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
 222                 region->start, region->end);
 223 }
 224
 225 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 226                               struct pci_bus_region *region)
 227 {
 228 #ifdef CONFIG_64BIT
 229         struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
 230 #endif
 231
 232         if (res->flags & IORESOURCE_MEM) {
 233                 res->start = PCI_HOST_ADDR(hba, region->start);
 234                 res->end = PCI_HOST_ADDR(hba, region->end);
 235         }
 236
 237         if (res->flags & IORESOURCE_IO) {
 238                 res->start = region->start;
 239                 res->end = region->end;
 240         }
 241 }
 242
 243 #ifdef CONFIG_HOTPLUG
 244 EXPORT_SYMBOL(pcibios_resource_to_bus);
 245 EXPORT_SYMBOL(pcibios_bus_to_resource);
 246 #endif
 247
 248 /*
 249  * pcibios align resources() is called every time generic PCI code
 250  * wants to generate a new address. The process of looking for
 251  * an available address, each candidate is first "aligned" and
 252  * then checked if the resource is available until a match is found.
 253  *
 254  * Since we are just checking candidates, don't use any fields other
 255  * than res->start.
 256  */
 257 void pcibios_align_resource(void *data, struct resource *res,
 258                                 resource_size_t size, resource_size_t alignment)
 259 {
 260         resource_size_t mask, align;
 261
 262         DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
 263                 pci_name(((struct pci_dev *) data)),
 264                 res->parent, res->start, res->end,
 265                 (int) res->flags, size, alignment);
 266
 267         /* If it's not IO, then it's gotta be MEM */
 268         align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 269
 270         /* Align to largest of MIN or input size */
 271         mask = max(alignment, align) - 1;
 272         res->start += mask;
 273         res->start &= ~mask;
 274
 275         /* The caller updates the end field, we don't.  */
 276 }
 277
 278
 279 /*
 280  * A driver is enabling the device.  We make sure that all the appropriate
 281  * bits are set to allow the device to operate as the driver is expecting.
 282  * We enable the port IO and memory IO bits if the device has any BARs of
 283  * that type, and we enable the PERR and SERR bits unconditionally.
 284  * Drivers that do not need parity (eg graphics and possibly networking)
 285  * can clear these bits if they want.
 286  */
 287 int pcibios_enable_device(struct pci_dev *dev, int mask)
 288 {
 289         int err;
 290         u16 cmd, old_cmd;
 291
 292         err = pci_enable_resources(dev, mask);
 293         if (err < 0)
 294                 return err;
 295
 296         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 297         old_cmd = cmd;
 298
 299         cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
 300
 301 #if 0
 302         /* If bridge/bus controller has FBB enabled, child must too. */
 303         if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
 304                 cmd |= PCI_COMMAND_FAST_BACK;
 305 #endif
 306
 307         if (cmd != old_cmd) {
 308                 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
 309                         old_cmd, cmd);
 310                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 311         }
 312         return 0;
 313 }
 314
 315
 316 /* PA-RISC specific */
 317 void pcibios_register_hba(struct pci_hba_data *hba)
 318 {
 319         if (pci_hba_count >= PCI_HBA_MAX) {
 320                 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
 321                 return;
 322         }
 323
 324         parisc_pci_hba[pci_hba_count] = hba;
 325         hba->hba_num = pci_hba_count++;
 326 }
 327
 328 subsys_initcall(pcibios_init);