arch/powerpc/boot/dts/p2020ds.dts

   1 /*
   2  * P2020 DS Device Tree Source
   3  *
   4  * Copyright 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "fsl,P2020";
  15         compatible = "fsl,P2020DS";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,P2020@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         next-level-cache = <&L2>;
  38                 };
  39
  40                 PowerPC,P2020@1 {
  41                         device_type = "cpu";
  42                         reg = <0x1>;
  43                         next-level-cache = <&L2>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49         };
  50
  51         localbus@ffe05000 {
  52                 #address-cells = <2>;
  53                 #size-cells = <1>;
  54                 compatible = "fsl,elbc", "simple-bus";
  55                 reg = <0 0xffe05000 0 0x1000>;
  56                 interrupts = <19 2>;
  57                 interrupt-parent = <&mpic>;
  58
  59                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  60                           0x1 0x0 0x0 0xe0000000 0x08000000
  61                           0x2 0x0 0x0 0xffa00000 0x00040000
  62                           0x3 0x0 0x0 0xffdf0000 0x00008000
  63                           0x4 0x0 0x0 0xffa40000 0x00040000
  64                           0x5 0x0 0x0 0xffa80000 0x00040000
  65                           0x6 0x0 0x0 0xffac0000 0x00040000>;
  66
  67                 nor@0,0 {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         compatible = "cfi-flash";
  71                         reg = <0x0 0x0 0x8000000>;
  72                         bank-width = <2>;
  73                         device-width = <1>;
  74
  75                         ramdisk@0 {
  76                                 reg = <0x0 0x03000000>;
  77                                 read-only;
  78                         };
  79
  80                         diagnostic@3000000 {
  81                                 reg = <0x03000000 0x00e00000>;
  82                                 read-only;
  83                         };
  84
  85                         dink@3e00000 {
  86                                 reg = <0x03e00000 0x00200000>;
  87                                 read-only;
  88                         };
  89
  90                         kernel@4000000 {
  91                                 reg = <0x04000000 0x00400000>;
  92                                 read-only;
  93                         };
  94
  95                         jffs2@4400000 {
  96                                 reg = <0x04400000 0x03b00000>;
  97                         };
  98
  99                         dtb@7f00000 {
 100                                 reg = <0x07f00000 0x00080000>;
 101                                 read-only;
 102                         };
 103
 104                         u-boot@7f80000 {
 105                                 reg = <0x07f80000 0x00080000>;
 106                                 read-only;
 107                         };
 108                 };
 109
 110                 nand@2,0 {
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         compatible = "fsl,elbc-fcm-nand";
 114                         reg = <0x2 0x0 0x40000>;
 115
 116                         u-boot@0 {
 117                                 reg = <0x0 0x02000000>;
 118                                 read-only;
 119                         };
 120
 121                         jffs2@2000000 {
 122                                 reg = <0x02000000 0x10000000>;
 123                         };
 124
 125                         ramdisk@12000000 {
 126                                 reg = <0x12000000 0x08000000>;
 127                                 read-only;
 128                         };
 129
 130                         kernel@1a000000 {
 131                                 reg = <0x1a000000 0x04000000>;
 132                         };
 133
 134                         dtb@1e000000 {
 135                                 reg = <0x1e000000 0x01000000>;
 136                                 read-only;
 137                         };
 138
 139                         empty@1f000000 {
 140                                 reg = <0x1f000000 0x21000000>;
 141                         };
 142                 };
 143
 144                 nand@4,0 {
 145                         compatible = "fsl,elbc-fcm-nand";
 146                         reg = <0x4 0x0 0x40000>;
 147                 };
 148
 149                 nand@5,0 {
 150                         compatible = "fsl,elbc-fcm-nand";
 151                         reg = <0x5 0x0 0x40000>;
 152                 };
 153
 154                 nand@6,0 {
 155                         compatible = "fsl,elbc-fcm-nand";
 156                         reg = <0x6 0x0 0x40000>;
 157                 };
 158         };
 159
 160         soc@ffe00000 {
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163                 device_type = "soc";
 164                 compatible = "fsl,p2020-immr", "simple-bus";
 165                 ranges = <0x0 0 0xffe00000 0x100000>;
 166                 bus-frequency = <0>;            // Filled out by uboot.
 167
 168                 ecm-law@0 {
 169                         compatible = "fsl,ecm-law";
 170                         reg = <0x0 0x1000>;
 171                         fsl,num-laws = <12>;
 172                 };
 173
 174                 ecm@1000 {
 175                         compatible = "fsl,p2020-ecm", "fsl,ecm";
 176                         reg = <0x1000 0x1000>;
 177                         interrupts = <17 2>;
 178                         interrupt-parent = <&mpic>;
 179                 };
 180
 181                 memory-controller@2000 {
 182                         compatible = "fsl,p2020-memory-controller";
 183                         reg = <0x2000 0x1000>;
 184                         interrupt-parent = <&mpic>;
 185                         interrupts = <18 2>;
 186                 };
 187
 188                 i2c@3000 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         cell-index = <0>;
 192                         compatible = "fsl-i2c";
 193                         reg = <0x3000 0x100>;
 194                         interrupts = <43 2>;
 195                         interrupt-parent = <&mpic>;
 196                         dfsrr;
 197                 };
 198
 199                 i2c@3100 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         cell-index = <1>;
 203                         compatible = "fsl-i2c";
 204                         reg = <0x3100 0x100>;
 205                         interrupts = <43 2>;
 206                         interrupt-parent = <&mpic>;
 207                         dfsrr;
 208                 };
 209
 210                 serial0: serial@4500 {
 211                         cell-index = <0>;
 212                         device_type = "serial";
 213                         compatible = "ns16550";
 214                         reg = <0x4500 0x100>;
 215                         clock-frequency = <0>;
 216                         interrupts = <42 2>;
 217                         interrupt-parent = <&mpic>;
 218                 };
 219
 220                 serial1: serial@4600 {
 221                         cell-index = <1>;
 222                         device_type = "serial";
 223                         compatible = "ns16550";
 224                         reg = <0x4600 0x100>;
 225                         clock-frequency = <0>;
 226                         interrupts = <42 2>;
 227                         interrupt-parent = <&mpic>;
 228                 };
 229
 230                 spi@7000 {
 231                         compatible = "fsl,espi";
 232                         reg = <0x7000 0x1000>;
 233                         interrupts = <59 0x2>;
 234                         interrupt-parent = <&mpic>;
 235                 };
 236
 237                 dma@c300 {
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         compatible = "fsl,eloplus-dma";
 241                         reg = <0xc300 0x4>;
 242                         ranges = <0x0 0xc100 0x200>;
 243                         cell-index = <1>;
 244                         dma-channel@0 {
 245                                 compatible = "fsl,eloplus-dma-channel";
 246                                 reg = <0x0 0x80>;
 247                                 cell-index = <0>;
 248                                 interrupt-parent = <&mpic>;
 249                                 interrupts = <76 2>;
 250                         };
 251                         dma-channel@80 {
 252                                 compatible = "fsl,eloplus-dma-channel";
 253                                 reg = <0x80 0x80>;
 254                                 cell-index = <1>;
 255                                 interrupt-parent = <&mpic>;
 256                                 interrupts = <77 2>;
 257                         };
 258                         dma-channel@100 {
 259                                 compatible = "fsl,eloplus-dma-channel";
 260                                 reg = <0x100 0x80>;
 261                                 cell-index = <2>;
 262                                 interrupt-parent = <&mpic>;
 263                                 interrupts = <78 2>;
 264                         };
 265                         dma-channel@180 {
 266                                 compatible = "fsl,eloplus-dma-channel";
 267                                 reg = <0x180 0x80>;
 268                                 cell-index = <3>;
 269                                 interrupt-parent = <&mpic>;
 270                                 interrupts = <79 2>;
 271                         };
 272                 };
 273
 274                 gpio: gpio-controller@f000 {
 275                         #gpio-cells = <2>;
 276                         compatible = "fsl,mpc8572-gpio";
 277                         reg = <0xf000 0x100>;
 278                         interrupts = <47 0x2>;
 279                         interrupt-parent = <&mpic>;
 280                         gpio-controller;
 281                 };
 282
 283                 L2: l2-cache-controller@20000 {
 284                         compatible = "fsl,p2020-l2-cache-controller";
 285                         reg = <0x20000 0x1000>;
 286                         cache-line-size = <32>; // 32 bytes
 287                         cache-size = <0x80000>; // L2, 512k
 288                         interrupt-parent = <&mpic>;
 289                         interrupts = <16 2>;
 290                 };
 291
 292                 dma@21300 {
 293                         #address-cells = <1>;
 294                         #size-cells = <1>;
 295                         compatible = "fsl,eloplus-dma";
 296                         reg = <0x21300 0x4>;
 297                         ranges = <0x0 0x21100 0x200>;
 298                         cell-index = <0>;
 299                         dma-channel@0 {
 300                                 compatible = "fsl,eloplus-dma-channel";
 301                                 reg = <0x0 0x80>;
 302                                 cell-index = <0>;
 303                                 interrupt-parent = <&mpic>;
 304                                 interrupts = <20 2>;
 305                         };
 306                         dma-channel@80 {
 307                                 compatible = "fsl,eloplus-dma-channel";
 308                                 reg = <0x80 0x80>;
 309                                 cell-index = <1>;
 310                                 interrupt-parent = <&mpic>;
 311                                 interrupts = <21 2>;
 312                         };
 313                         dma-channel@100 {
 314                                 compatible = "fsl,eloplus-dma-channel";
 315                                 reg = <0x100 0x80>;
 316                                 cell-index = <2>;
 317                                 interrupt-parent = <&mpic>;
 318                                 interrupts = <22 2>;
 319                         };
 320                         dma-channel@180 {
 321                                 compatible = "fsl,eloplus-dma-channel";
 322                                 reg = <0x180 0x80>;
 323                                 cell-index = <3>;
 324                                 interrupt-parent = <&mpic>;
 325                                 interrupts = <23 2>;
 326                         };
 327                 };
 328
 329                 usb@22000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "fsl-usb2-dr";
 333                         reg = <0x22000 0x1000>;
 334                         interrupt-parent = <&mpic>;
 335                         interrupts = <28 0x2>;
 336                         phy_type = "ulpi";
 337                 };
 338
 339                 enet0: ethernet@24000 {
 340                         #address-cells = <1>;
 341                         #size-cells = <1>;
 342                         cell-index = <0>;
 343                         device_type = "network";
 344                         model = "eTSEC";
 345                         compatible = "gianfar";
 346                         reg = <0x24000 0x1000>;
 347                         ranges = <0x0 0x24000 0x1000>;
 348                         local-mac-address = [ 00 00 00 00 00 00 ];
 349                         interrupts = <29 2 30 2 34 2>;
 350                         interrupt-parent = <&mpic>;
 351                         tbi-handle = <&tbi0>;
 352                         phy-handle = <&phy0>;
 353                         phy-connection-type = "rgmii-id";
 354
 355                         mdio@520 {
 356                                 #address-cells = <1>;
 357                                 #size-cells = <0>;
 358                                 compatible = "fsl,gianfar-mdio";
 359                                 reg = <0x520 0x20>;
 360
 361                                 phy0: ethernet-phy@0 {
 362                                         interrupt-parent = <&mpic>;
 363                                         interrupts = <3 1>;
 364                                         reg = <0x0>;
 365                                 };
 366                                 phy1: ethernet-phy@1 {
 367                                         interrupt-parent = <&mpic>;
 368                                         interrupts = <3 1>;
 369                                         reg = <0x1>;
 370                                 };
 371                                 phy2: ethernet-phy@2 {
 372                                         interrupt-parent = <&mpic>;
 373                                         interrupts = <3 1>;
 374                                         reg = <0x2>;
 375                                 };
 376                                 tbi0: tbi-phy@11 {
 377                                         reg = <0x11>;
 378                                         device_type = "tbi-phy";
 379                                 };
 380                         };
 381                 };
 382
 383                 enet1: ethernet@25000 {
 384                         #address-cells = <1>;
 385                         #size-cells = <1>;
 386                         cell-index = <1>;
 387                         device_type = "network";
 388                         model = "eTSEC";
 389                         compatible = "gianfar";
 390                         reg = <0x25000 0x1000>;
 391                         ranges = <0x0 0x25000 0x1000>;
 392                         local-mac-address = [ 00 00 00 00 00 00 ];
 393                         interrupts = <35 2 36 2 40 2>;
 394                         interrupt-parent = <&mpic>;
 395                         tbi-handle = <&tbi1>;
 396                         phy-handle = <&phy1>;
 397                         phy-connection-type = "rgmii-id";
 398
 399                         mdio@520 {
 400                                 #address-cells = <1>;
 401                                 #size-cells = <0>;
 402                                 compatible = "fsl,gianfar-tbi";
 403                                 reg = <0x520 0x20>;
 404
 405                                 tbi1: tbi-phy@11 {
 406                                         reg = <0x11>;
 407                                         device_type = "tbi-phy";
 408                                 };
 409                         };
 410                 };
 411
 412                 enet2: ethernet@26000 {
 413                         #address-cells = <1>;
 414                         #size-cells = <1>;
 415                         cell-index = <2>;
 416                         device_type = "network";
 417                         model = "eTSEC";
 418                         compatible = "gianfar";
 419                         reg = <0x26000 0x1000>;
 420                         ranges = <0x0 0x26000 0x1000>;
 421                         local-mac-address = [ 00 00 00 00 00 00 ];
 422                         interrupts = <31 2 32 2 33 2>;
 423                         interrupt-parent = <&mpic>;
 424                         tbi-handle = <&tbi2>;
 425                         phy-handle = <&phy2>;
 426                         phy-connection-type = "rgmii-id";
 427
 428                         mdio@520 {
 429                                 #address-cells = <1>;
 430                                 #size-cells = <0>;
 431                                 compatible = "fsl,gianfar-tbi";
 432                                 reg = <0x520 0x20>;
 433
 434                                 tbi2: tbi-phy@11 {
 435                                         reg = <0x11>;
 436                                         device_type = "tbi-phy";
 437                                 };
 438                         };
 439                 };
 440
 441                 sdhci@2e000 {
 442                         compatible = "fsl,p2020-esdhc", "fsl,esdhc";
 443                         reg = <0x2e000 0x1000>;
 444                         interrupts = <72 0x2>;
 445                         interrupt-parent = <&mpic>;
 446                         /* Filled in by U-Boot */
 447                         clock-frequency = <0>;
 448                 };
 449
 450                 crypto@30000 {
 451                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 452                                      "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 453                         reg = <0x30000 0x10000>;
 454                         interrupts = <45 2 58 2>;
 455                         interrupt-parent = <&mpic>;
 456                         fsl,num-channels = <4>;
 457                         fsl,channel-fifo-len = <24>;
 458                         fsl,exec-units-mask = <0xbfe>;
 459                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 460                 };
 461
 462                 mpic: pic@40000 {
 463                         interrupt-controller;
 464                         #address-cells = <0>;
 465                         #interrupt-cells = <2>;
 466                         reg = <0x40000 0x40000>;
 467                         compatible = "chrp,open-pic";
 468                         device_type = "open-pic";
 469                 };
 470
 471                 msi@41600 {
 472                         compatible = "fsl,mpic-msi";
 473                         reg = <0x41600 0x80>;
 474                         msi-available-ranges = <0 0x100>;
 475                         interrupts = <
 476                                 0xe0 0
 477                                 0xe1 0
 478                                 0xe2 0
 479                                 0xe3 0
 480                                 0xe4 0
 481                                 0xe5 0
 482                                 0xe6 0
 483                                 0xe7 0>;
 484                         interrupt-parent = <&mpic>;
 485                 };
 486
 487                 global-utilities@e0000 {        //global utilities block
 488                         compatible = "fsl,p2020-guts";
 489                         reg = <0xe0000 0x1000>;
 490                         fsl,has-rstcr;
 491                 };
 492         };
 493
 494         pci0: pcie@ffe08000 {
 495                 compatible = "fsl,mpc8548-pcie";
 496                 device_type = "pci";
 497                 #interrupt-cells = <1>;
 498                 #size-cells = <2>;
 499                 #address-cells = <3>;
 500                 reg = <0 0xffe08000 0 0x1000>;
 501                 bus-range = <0 255>;
 502                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 503                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
 504                 clock-frequency = <33333333>;
 505                 interrupt-parent = <&mpic>;
 506                 interrupts = <24 2>;
 507                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 508                 interrupt-map = <
 509                         /* IDSEL 0x0 */
 510                         0000 0x0 0x0 0x1 &mpic 0x8 0x1
 511                         0000 0x0 0x0 0x2 &mpic 0x9 0x1
 512                         0000 0x0 0x0 0x3 &mpic 0xa 0x1
 513                         0000 0x0 0x0 0x4 &mpic 0xb 0x1
 514                         >;
 515                 pcie@0 {
 516                         reg = <0x0 0x0 0x0 0x0 0x0>;
 517                         #size-cells = <2>;
 518                         #address-cells = <3>;
 519                         device_type = "pci";
 520                         ranges = <0x2000000 0x0 0x80000000
 521                                   0x2000000 0x0 0x80000000
 522                                   0x0 0x20000000
 523
 524                                   0x1000000 0x0 0x0
 525                                   0x1000000 0x0 0x0
 526                                   0x0 0x10000>;
 527                 };
 528         };
 529
 530         pci1: pcie@ffe09000 {
 531                 compatible = "fsl,mpc8548-pcie";
 532                 device_type = "pci";
 533                 #interrupt-cells = <1>;
 534                 #size-cells = <2>;
 535                 #address-cells = <3>;
 536                 reg = <0 0xffe09000 0 0x1000>;
 537                 bus-range = <0 255>;
 538                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 539                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 540                 clock-frequency = <33333333>;
 541                 interrupt-parent = <&mpic>;
 542                 interrupts = <25 2>;
 543                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 544                 interrupt-map = <
 545
 546                         // IDSEL 0x11 func 0 - PCI slot 1
 547                         0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
 548                         0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
 549
 550                         // IDSEL 0x11 func 1 - PCI slot 1
 551                         0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
 552                         0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
 553
 554                         // IDSEL 0x11 func 2 - PCI slot 1
 555                         0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
 556                         0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
 557
 558                         // IDSEL 0x11 func 3 - PCI slot 1
 559                         0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
 560                         0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
 561
 562                         // IDSEL 0x11 func 4 - PCI slot 1
 563                         0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
 564                         0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
 565
 566                         // IDSEL 0x11 func 5 - PCI slot 1
 567                         0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
 568                         0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
 569
 570                         // IDSEL 0x11 func 6 - PCI slot 1
 571                         0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
 572                         0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
 573
 574                         // IDSEL 0x11 func 7 - PCI slot 1
 575                         0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
 576                         0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
 577
 578                         // IDSEL 0x1d  Audio
 579                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 580
 581                         // IDSEL 0x1e Legacy
 582                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 583                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 584
 585                         // IDSEL 0x1f IDE/SATA
 586                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 587                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 588                         >;
 589
 590                 pcie@0 {
 591                         reg = <0x0 0x0 0x0 0x0 0x0>;
 592                         #size-cells = <2>;
 593                         #address-cells = <3>;
 594                         device_type = "pci";
 595                         ranges = <0x2000000 0x0 0xa0000000
 596                                   0x2000000 0x0 0xa0000000
 597                                   0x0 0x20000000
 598
 599                                   0x1000000 0x0 0x0
 600                                   0x1000000 0x0 0x0
 601                                   0x0 0x10000>;
 602                         uli1575@0 {
 603                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 604                                 #size-cells = <2>;
 605                                 #address-cells = <3>;
 606                                 ranges = <0x2000000 0x0 0xa0000000
 607                                           0x2000000 0x0 0xa0000000
 608                                           0x0 0x20000000
 609
 610                                           0x1000000 0x0 0x0
 611                                           0x1000000 0x0 0x0
 612                                           0x0 0x10000>;
 613                                 isa@1e {
 614                                         device_type = "isa";
 615                                         #interrupt-cells = <2>;
 616                                         #size-cells = <1>;
 617                                         #address-cells = <2>;
 618                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 619                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
 620                                                   0x1000>;
 621                                         interrupt-parent = <&i8259>;
 622
 623                                         i8259: interrupt-controller@20 {
 624                                                 reg = <0x1 0x20 0x2
 625                                                        0x1 0xa0 0x2
 626                                                        0x1 0x4d0 0x2>;
 627                                                 interrupt-controller;
 628                                                 device_type = "interrupt-controller";
 629                                                 #address-cells = <0>;
 630                                                 #interrupt-cells = <2>;
 631                                                 compatible = "chrp,iic";
 632                                                 interrupts = <4 1>;
 633                                                 interrupt-parent = <&mpic>;
 634                                         };
 635
 636                                         i8042@60 {
 637                                                 #size-cells = <0>;
 638                                                 #address-cells = <1>;
 639                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 640                                                 interrupts = <1 3 12 3>;
 641                                                 interrupt-parent =
 642                                                         <&i8259>;
 643
 644                                                 keyboard@0 {
 645                                                         reg = <0x0>;
 646                                                         compatible = "pnpPNP,303";
 647                                                 };
 648
 649                                                 mouse@1 {
 650                                                         reg = <0x1>;
 651                                                         compatible = "pnpPNP,f03";
 652                                                 };
 653                                         };
 654
 655                                         rtc@70 {
 656                                                 compatible = "pnpPNP,b00";
 657                                                 reg = <0x1 0x70 0x2>;
 658                                         };
 659
 660                                         gpio@400 {
 661                                                 reg = <0x1 0x400 0x80>;
 662                                         };
 663                                 };
 664                         };
 665                 };
 666
 667         };
 668
 669         pci2: pcie@ffe0a000 {
 670                 compatible = "fsl,mpc8548-pcie";
 671                 device_type = "pci";
 672                 #interrupt-cells = <1>;
 673                 #size-cells = <2>;
 674                 #address-cells = <3>;
 675                 reg = <0 0xffe0a000 0 0x1000>;
 676                 bus-range = <0 255>;
 677                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 678                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
 679                 clock-frequency = <33333333>;
 680                 interrupt-parent = <&mpic>;
 681                 interrupts = <26 2>;
 682                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 683                 interrupt-map = <
 684                         /* IDSEL 0x0 */
 685                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 686                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 687                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 688                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 689                         >;
 690                 pcie@0 {
 691                         reg = <0x0 0x0 0x0 0x0 0x0>;
 692                         #size-cells = <2>;
 693                         #address-cells = <3>;
 694                         device_type = "pci";
 695                         ranges = <0x2000000 0x0 0xc0000000
 696                                   0x2000000 0x0 0xc0000000
 697                                   0x0 0x20000000
 698
 699                                   0x1000000 0x0 0x0
 700                                   0x1000000 0x0 0x0
 701                                   0x0 0x10000>;
 702                 };
 703         };
 704 };