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[cor_2_6_31.git] / sound / pci / hda / patch_nvhdmi.c
blobf5792e2eea82dd412dd18f7aca3b6f328027444b
1 /*
2 * Universal Interface for Intel High Definition Audio Codec
4 * HD audio interface patch for NVIDIA HDMI codecs
6 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
7 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * This driver is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This driver is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include "hda_codec.h"
30 #include "hda_local.h"
32 struct nvhdmi_spec {
33 struct hda_multi_out multiout;
35 struct hda_pcm pcm_rec;
38 #define Nv_VERB_SET_Channel_Allocation 0xF79
39 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
40 #define Nv_VERB_SET_Audio_Protection_On 0xF98
41 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
43 #define Nv_Master_Convert_nid 0x04
44 #define Nv_Master_Pin_nid 0x05
46 static hda_nid_t nvhdmi_convert_nids[4] = {
47 /*front, rear, clfe, rear_surr */
48 0x6, 0x8, 0xa, 0xc,
51 static struct hda_verb nvhdmi_basic_init[] = {
52 /* set audio protect on */
53 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
54 /* enable digital output on pin widget */
55 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
56 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
57 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
58 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
59 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
60 {} /* terminator */
64 * Controls
66 static int nvhdmi_build_controls(struct hda_codec *codec)
68 struct nvhdmi_spec *spec = codec->spec;
69 int err;
71 err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid);
72 if (err < 0)
73 return err;
75 return 0;
78 static int nvhdmi_init(struct hda_codec *codec)
80 snd_hda_sequence_write(codec, nvhdmi_basic_init);
81 return 0;
85 * Digital out
87 static int nvhdmi_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
88 struct hda_codec *codec,
89 struct snd_pcm_substream *substream)
91 struct nvhdmi_spec *spec = codec->spec;
92 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95 static int nvhdmi_dig_playback_pcm_close_8ch(struct hda_pcm_stream *hinfo,
96 struct hda_codec *codec,
97 struct snd_pcm_substream *substream)
99 struct nvhdmi_spec *spec = codec->spec;
100 int i;
102 snd_hda_codec_write(codec, Nv_Master_Convert_nid,
103 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
104 for (i = 0; i < 4; i++) {
105 /* set the stream id */
106 snd_hda_codec_write(codec, nvhdmi_convert_nids[i], 0,
107 AC_VERB_SET_CHANNEL_STREAMID, 0);
108 /* set the stream format */
109 snd_hda_codec_write(codec, nvhdmi_convert_nids[i], 0,
110 AC_VERB_SET_STREAM_FORMAT, 0);
113 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
116 static int nvhdmi_dig_playback_pcm_close_2ch(struct hda_pcm_stream *hinfo,
117 struct hda_codec *codec,
118 struct snd_pcm_substream *substream)
120 struct nvhdmi_spec *spec = codec->spec;
121 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
124 static int nvhdmi_dig_playback_pcm_prepare_8ch(struct hda_pcm_stream *hinfo,
125 struct hda_codec *codec,
126 unsigned int stream_tag,
127 unsigned int format,
128 struct snd_pcm_substream *substream)
130 int chs;
131 unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
132 int i;
134 mutex_lock(&codec->spdif_mutex);
136 chs = substream->runtime->channels;
137 chan = chs ? (chs - 1) : 1;
139 switch (chs) {
140 default:
141 case 0:
142 case 2:
143 chanmask = 0x00;
144 break;
145 case 4:
146 chanmask = 0x08;
147 break;
148 case 6:
149 chanmask = 0x0b;
150 break;
151 case 8:
152 chanmask = 0x13;
153 break;
155 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
156 dataDCC2 = 0x2;
158 /* set the Audio InforFrame Channel Allocation */
159 snd_hda_codec_write(codec, 0x1, 0,
160 Nv_VERB_SET_Channel_Allocation, chanmask);
162 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
163 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
164 snd_hda_codec_write(codec,
165 Nv_Master_Convert_nid,
167 AC_VERB_SET_DIGI_CONVERT_1,
168 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
170 /* set the stream id */
171 snd_hda_codec_write(codec, Nv_Master_Convert_nid, 0,
172 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
174 /* set the stream format */
175 snd_hda_codec_write(codec, Nv_Master_Convert_nid, 0,
176 AC_VERB_SET_STREAM_FORMAT, format);
178 /* turn on again (if needed) */
179 /* enable and set the channel status audio/data flag */
180 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
181 snd_hda_codec_write(codec,
182 Nv_Master_Convert_nid,
184 AC_VERB_SET_DIGI_CONVERT_1,
185 codec->spdif_ctls & 0xff);
186 snd_hda_codec_write(codec,
187 Nv_Master_Convert_nid,
189 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
192 for (i = 0; i < 4; i++) {
193 if (chs == 2)
194 channel_id = 0;
195 else
196 channel_id = i * 2;
198 /* turn off SPDIF once;
199 *otherwise the IEC958 bits won't be updated
201 if (codec->spdif_status_reset &&
202 (codec->spdif_ctls & AC_DIG1_ENABLE))
203 snd_hda_codec_write(codec,
204 nvhdmi_convert_nids[i],
206 AC_VERB_SET_DIGI_CONVERT_1,
207 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
208 /* set the stream id */
209 snd_hda_codec_write(codec,
210 nvhdmi_convert_nids[i],
212 AC_VERB_SET_CHANNEL_STREAMID,
213 (stream_tag << 4) | channel_id);
214 /* set the stream format */
215 snd_hda_codec_write(codec,
216 nvhdmi_convert_nids[i],
218 AC_VERB_SET_STREAM_FORMAT,
219 format);
220 /* turn on again (if needed) */
221 /* enable and set the channel status audio/data flag */
222 if (codec->spdif_status_reset &&
223 (codec->spdif_ctls & AC_DIG1_ENABLE)) {
224 snd_hda_codec_write(codec,
225 nvhdmi_convert_nids[i],
227 AC_VERB_SET_DIGI_CONVERT_1,
228 codec->spdif_ctls & 0xff);
229 snd_hda_codec_write(codec,
230 nvhdmi_convert_nids[i],
232 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
236 /* set the Audio Info Frame Checksum */
237 snd_hda_codec_write(codec, 0x1, 0,
238 Nv_VERB_SET_Info_Frame_Checksum,
239 (0x71 - chan - chanmask));
241 mutex_unlock(&codec->spdif_mutex);
242 return 0;
245 static int nvhdmi_dig_playback_pcm_prepare_2ch(struct hda_pcm_stream *hinfo,
246 struct hda_codec *codec,
247 unsigned int stream_tag,
248 unsigned int format,
249 struct snd_pcm_substream *substream)
251 struct nvhdmi_spec *spec = codec->spec;
252 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, stream_tag,
253 format, substream);
256 static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch = {
257 .substreams = 1,
258 .channels_min = 2,
259 .channels_max = 8,
260 .nid = Nv_Master_Convert_nid,
261 .rates = SNDRV_PCM_RATE_48000,
262 .maxbps = 16,
263 .formats = SNDRV_PCM_FMTBIT_S16_LE,
264 .ops = {
265 .open = nvhdmi_dig_playback_pcm_open,
266 .close = nvhdmi_dig_playback_pcm_close_8ch,
267 .prepare = nvhdmi_dig_playback_pcm_prepare_8ch
271 static struct hda_pcm_stream nvhdmi_pcm_digital_playback_2ch = {
272 .substreams = 1,
273 .channels_min = 2,
274 .channels_max = 2,
275 .nid = Nv_Master_Convert_nid,
276 .rates = SNDRV_PCM_RATE_48000,
277 .maxbps = 16,
278 .formats = SNDRV_PCM_FMTBIT_S16_LE,
279 .ops = {
280 .open = nvhdmi_dig_playback_pcm_open,
281 .close = nvhdmi_dig_playback_pcm_close_2ch,
282 .prepare = nvhdmi_dig_playback_pcm_prepare_2ch
286 static int nvhdmi_build_pcms_8ch(struct hda_codec *codec)
288 struct nvhdmi_spec *spec = codec->spec;
289 struct hda_pcm *info = &spec->pcm_rec;
291 codec->num_pcms = 1;
292 codec->pcm_info = info;
294 info->name = "NVIDIA HDMI";
295 info->pcm_type = HDA_PCM_TYPE_HDMI;
296 info->stream[SNDRV_PCM_STREAM_PLAYBACK]
297 = nvhdmi_pcm_digital_playback_8ch;
299 return 0;
302 static int nvhdmi_build_pcms_2ch(struct hda_codec *codec)
304 struct nvhdmi_spec *spec = codec->spec;
305 struct hda_pcm *info = &spec->pcm_rec;
307 codec->num_pcms = 1;
308 codec->pcm_info = info;
310 info->name = "NVIDIA HDMI";
311 info->pcm_type = HDA_PCM_TYPE_HDMI;
312 info->stream[SNDRV_PCM_STREAM_PLAYBACK]
313 = nvhdmi_pcm_digital_playback_2ch;
315 return 0;
318 static void nvhdmi_free(struct hda_codec *codec)
320 kfree(codec->spec);
323 static struct hda_codec_ops nvhdmi_patch_ops_8ch = {
324 .build_controls = nvhdmi_build_controls,
325 .build_pcms = nvhdmi_build_pcms_8ch,
326 .init = nvhdmi_init,
327 .free = nvhdmi_free,
330 static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
331 .build_controls = nvhdmi_build_controls,
332 .build_pcms = nvhdmi_build_pcms_2ch,
333 .init = nvhdmi_init,
334 .free = nvhdmi_free,
337 static int patch_nvhdmi_8ch(struct hda_codec *codec)
339 struct nvhdmi_spec *spec;
341 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
342 if (spec == NULL)
343 return -ENOMEM;
345 codec->spec = spec;
347 spec->multiout.num_dacs = 0; /* no analog */
348 spec->multiout.max_channels = 8;
349 spec->multiout.dig_out_nid = Nv_Master_Convert_nid;
351 codec->patch_ops = nvhdmi_patch_ops_8ch;
353 return 0;
356 static int patch_nvhdmi_2ch(struct hda_codec *codec)
358 struct nvhdmi_spec *spec;
360 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
361 if (spec == NULL)
362 return -ENOMEM;
364 codec->spec = spec;
366 spec->multiout.num_dacs = 0; /* no analog */
367 spec->multiout.max_channels = 2;
368 spec->multiout.dig_out_nid = Nv_Master_Convert_nid;
370 codec->patch_ops = nvhdmi_patch_ops_2ch;
372 return 0;
376 * patch entries
378 static struct hda_codec_preset snd_hda_preset_nvhdmi[] = {
379 { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
380 { .id = 0x10de0006, .name = "MCP78 HDMI", .patch = patch_nvhdmi_8ch },
381 { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi_8ch },
382 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
383 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
384 {} /* terminator */
387 MODULE_ALIAS("snd-hda-codec-id:10de0002");
388 MODULE_ALIAS("snd-hda-codec-id:10de0006");
389 MODULE_ALIAS("snd-hda-codec-id:10de0007");
390 MODULE_ALIAS("snd-hda-codec-id:10de0067");
391 MODULE_ALIAS("snd-hda-codec-id:10de8001");
393 MODULE_LICENSE("GPL");
394 MODULE_DESCRIPTION("Nvidia HDMI HD-audio codec");
396 static struct hda_codec_preset_list nvhdmi_list = {
397 .preset = snd_hda_preset_nvhdmi,
398 .owner = THIS_MODULE,
401 static int __init patch_nvhdmi_init(void)
403 return snd_hda_add_codec_preset(&nvhdmi_list);
406 static void __exit patch_nvhdmi_exit(void)
408 snd_hda_delete_codec_preset(&nvhdmi_list);
411 module_init(patch_nvhdmi_init)
412 module_exit(patch_nvhdmi_exit)