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close_port, kpacket_gen kmalloc oom, formard.c wake_sender/skb receive oom handling...
[cor_2_6_31.git] / sound / pci / rme9652 / hdsp.c
blob3da5c029f93bc763ad25322ee0cfe7e1eb356728
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/slab.h>
28 #include <linux/pci.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <linux/math64.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
63 #ifdef HDSP_FW_LOADER
64 MODULE_FIRMWARE("multiface_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
66 MODULE_FIRMWARE("digiface_firmware.bin");
67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
68 #endif
69
70 #define HDSP_MAX_CHANNELS 26
71 #define HDSP_MAX_DS_CHANNELS 14
72 #define HDSP_MAX_QS_CHANNELS 8
73 #define DIGIFACE_SS_CHANNELS 26
74 #define DIGIFACE_DS_CHANNELS 14
75 #define MULTIFACE_SS_CHANNELS 18
76 #define MULTIFACE_DS_CHANNELS 14
77 #define H9652_SS_CHANNELS 26
78 #define H9652_DS_CHANNELS 14
79 /* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
81 */
82 #define H9632_SS_CHANNELS 12
83 #define H9632_DS_CHANNELS 8
84 #define H9632_QS_CHANNELS 4
85
86 /* Write registers. These are defined as byte-offsets from the iobase value.
87 */
88 #define HDSP_resetPointer 0
89 #define HDSP_freqReg 0
90 #define HDSP_outputBufferAddress 32
91 #define HDSP_inputBufferAddress 36
92 #define HDSP_controlRegister 64
93 #define HDSP_interruptConfirmation 96
94 #define HDSP_outputEnable 128
95 #define HDSP_control2Reg 256
96 #define HDSP_midiDataOut0 352
97 #define HDSP_midiDataOut1 356
98 #define HDSP_fifoData 368
99 #define HDSP_inputEnable 384
100
101 /* Read registers. These are defined as byte-offsets from the iobase value
102 */
103
104 #define HDSP_statusRegister 0
105 #define HDSP_timecode 128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0 360
108 #define HDSP_midiDataIn1 364
109 #define HDSP_midiStatusOut0 384
110 #define HDSP_midiStatusOut1 388
111 #define HDSP_midiStatusIn0 392
112 #define HDSP_midiStatusIn1 396
113 #define HDSP_fifoStatus 400
114
115 /* the meters are regular i/o-mapped registers, but offset
116 considerably from the rest. the peak registers are reset
117 when read; the least-significant 4 bits are full-scale counters;
118 the actual peak value is in the most-significant 24 bits.
119 */
120
121 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
126
127
128 /* This is for H9652 cards
129 Peak values are read downward from the base
130 Rms values are read upward
131 There are rms values for the outputs too
132 26*3 values are read in ss mode
133 14*3 in ds mode, with no gap between values
134 */
135 #define HDSP_9652_peakBase 7164
136 #define HDSP_9652_rmsBase 4096
137
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase 4096
140
141 #define HDSP_IO_EXTENT 7168
142
143 /* control2 register bits */
144
145 #define HDSP_TMS 0x01
146 #define HDSP_TCK 0x02
147 #define HDSP_TDI 0x04
148 #define HDSP_JTAG 0x08
149 #define HDSP_PWDN 0x10
150 #define HDSP_PROGRAM 0x020
151 #define HDSP_CONFIG_MODE_0 0x040
152 #define HDSP_CONFIG_MODE_1 0x080
153 #define HDSP_VERSION_BIT 0x100
154 #define HDSP_BIGENDIAN_MODE 0x200
155 #define HDSP_RD_MULTIPLE 0x400
156 #define HDSP_9652_ENABLE_MIXER 0x800
157 #define HDSP_TDO 0x10000000
158
159 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
160 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
161
162 /* Control Register bits */
163
164 #define HDSP_Start (1<<0) /* start engine */
165 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
166 #define HDSP_Latency1 (1<<2) /* [ see above ] */
167 #define HDSP_Latency2 (1<<3) /* [ see above ] */
168 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
169 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
170 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
171 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
172 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
173 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
174 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
175 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
176 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
177 #define HDSP_SyncRef2 (1<<13)
178 #define HDSP_SPDIFInputSelect0 (1<<14)
179 #define HDSP_SPDIFInputSelect1 (1<<15)
180 #define HDSP_SyncRef0 (1<<16)
181 #define HDSP_SyncRef1 (1<<17)
182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
183 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
184 #define HDSP_Midi0InterruptEnable (1<<22)
185 #define HDSP_Midi1InterruptEnable (1<<23)
186 #define HDSP_LineOut (1<<24)
187 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
188 #define HDSP_ADGain1 (1<<26)
189 #define HDSP_DAGain0 (1<<27)
190 #define HDSP_DAGain1 (1<<28)
191 #define HDSP_PhoneGain0 (1<<29)
192 #define HDSP_PhoneGain1 (1<<30)
193 #define HDSP_QuadSpeed (1<<31)
194
195 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
196 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
197 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
198 #define HDSP_ADGainLowGain 0
199
200 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
201 #define HDSP_DAGainHighGain HDSP_DAGainMask
202 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
203 #define HDSP_DAGainMinus10dBV 0
204
205 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
206 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
207 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
208 #define HDSP_PhoneGainMinus12dB 0
209
210 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
211 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
212
213 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
214 #define HDSP_SPDIFInputADAT1 0
215 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
216 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
217 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
218
219 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
220 #define HDSP_SyncRef_ADAT1 0
221 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
222 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
223 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
224 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
225 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
226
227 /* Sample Clock Sources */
228
229 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
230 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
231 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
232 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
233 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
234 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
235 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
236 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
237 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
238 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
239
240 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
241
242 #define HDSP_SYNC_FROM_WORD 0
243 #define HDSP_SYNC_FROM_SPDIF 1
244 #define HDSP_SYNC_FROM_ADAT1 2
245 #define HDSP_SYNC_FROM_ADAT_SYNC 3
246 #define HDSP_SYNC_FROM_ADAT2 4
247 #define HDSP_SYNC_FROM_ADAT3 5
248
249 /* SyncCheck status */
250
251 #define HDSP_SYNC_CHECK_NO_LOCK 0
252 #define HDSP_SYNC_CHECK_LOCK 1
253 #define HDSP_SYNC_CHECK_SYNC 2
254
255 /* AutoSync references - used by "autosync_ref" control switch */
256
257 #define HDSP_AUTOSYNC_FROM_WORD 0
258 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
259 #define HDSP_AUTOSYNC_FROM_SPDIF 2
260 #define HDSP_AUTOSYNC_FROM_NONE 3
261 #define HDSP_AUTOSYNC_FROM_ADAT1 4
262 #define HDSP_AUTOSYNC_FROM_ADAT2 5
263 #define HDSP_AUTOSYNC_FROM_ADAT3 6
264
265 /* Possible sources of S/PDIF input */
266
267 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
268 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
269 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
270 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
271
272 #define HDSP_Frequency32KHz HDSP_Frequency0
273 #define HDSP_Frequency44_1KHz HDSP_Frequency1
274 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
275 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
276 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
277 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
278 /* For H9632 cards */
279 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
280 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
281 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
282 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
283 return 104857600000000 / rate; // 100 MHz
284 return 110100480000000 / rate; // 105 MHz
285 */
286 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
287
288 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
289 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
290
291 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
292 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
293
294 /* Status Register bits */
295
296 #define HDSP_audioIRQPending (1<<0)
297 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
298 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
299 #define HDSP_Lock1 (1<<2)
300 #define HDSP_Lock0 (1<<3)
301 #define HDSP_SPDIFSync (1<<4)
302 #define HDSP_TimecodeLock (1<<5)
303 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
304 #define HDSP_Sync2 (1<<16)
305 #define HDSP_Sync1 (1<<17)
306 #define HDSP_Sync0 (1<<18)
307 #define HDSP_DoubleSpeedStatus (1<<19)
308 #define HDSP_ConfigError (1<<20)
309 #define HDSP_DllError (1<<21)
310 #define HDSP_spdifFrequency0 (1<<22)
311 #define HDSP_spdifFrequency1 (1<<23)
312 #define HDSP_spdifFrequency2 (1<<24)
313 #define HDSP_SPDIFErrorFlag (1<<25)
314 #define HDSP_BufferID (1<<26)
315 #define HDSP_TimecodeSync (1<<27)
316 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
317 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
318 #define HDSP_midi0IRQPending (1<<30)
319 #define HDSP_midi1IRQPending (1<<31)
320
321 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
322 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
323 HDSP_spdifFrequency1|\
324 HDSP_spdifFrequency2|\
325 HDSP_spdifFrequency3)
326
327 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
328 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
329 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
330
331 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
332 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
333 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
334
335 /* This is for H9632 cards */
336 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
337 HDSP_spdifFrequency1|\
338 HDSP_spdifFrequency2)
339 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
340 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
341
342 /* Status2 Register bits */
343
344 #define HDSP_version0 (1<<0)
345 #define HDSP_version1 (1<<1)
346 #define HDSP_version2 (1<<2)
347 #define HDSP_wc_lock (1<<3)
348 #define HDSP_wc_sync (1<<4)
349 #define HDSP_inp_freq0 (1<<5)
350 #define HDSP_inp_freq1 (1<<6)
351 #define HDSP_inp_freq2 (1<<7)
352 #define HDSP_SelSyncRef0 (1<<8)
353 #define HDSP_SelSyncRef1 (1<<9)
354 #define HDSP_SelSyncRef2 (1<<10)
355
356 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
357
358 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
359 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
360 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
361 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
362 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
363 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
364 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
365 /* FIXME : more values for 9632 cards ? */
366
367 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
368 #define HDSP_SelSyncRef_ADAT1 0
369 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
370 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
371 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
372 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
373 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
374
375 /* Card state flags */
376
377 #define HDSP_InitializationComplete (1<<0)
378 #define HDSP_FirmwareLoaded (1<<1)
379 #define HDSP_FirmwareCached (1<<2)
380
381 /* FIFO wait times, defined in terms of 1/10ths of msecs */
382
383 #define HDSP_LONG_WAIT 5000
384 #define HDSP_SHORT_WAIT 30
385
386 #define UNITY_GAIN 32768
387 #define MINUS_INFINITY_GAIN 0
388
389 /* the size of a substream (1 mono data stream) */
390
391 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
392 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
393
394 /* the size of the area we need to allocate for DMA transfers. the
395 size is the same regardless of the number of channels - the
396 Multiface still uses the same memory area.
397
398 Note that we allocate 1 more channel than is apparently needed
399 because the h/w seems to write 1 byte beyond the end of the last
400 page. Sigh.
401 */
402
403 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
404 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
405
406 /* use hotplug firmware loader? */
407 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
408 #if !defined(HDSP_USE_HWDEP_LOADER)
409 #define HDSP_FW_LOADER
410 #endif
411 #endif
412
413 struct hdsp_9632_meters {
414 u32 input_peak[16];
415 u32 playback_peak[16];
416 u32 output_peak[16];
417 u32 xxx_peak[16];
418 u32 padding[64];
419 u32 input_rms_low[16];
420 u32 playback_rms_low[16];
421 u32 output_rms_low[16];
422 u32 xxx_rms_low[16];
423 u32 input_rms_high[16];
424 u32 playback_rms_high[16];
425 u32 output_rms_high[16];
426 u32 xxx_rms_high[16];
427 };
428
429 struct hdsp_midi {
430 struct hdsp *hdsp;
431 int id;
432 struct snd_rawmidi *rmidi;
433 struct snd_rawmidi_substream *input;
434 struct snd_rawmidi_substream *output;
435 char istimer; /* timer in use */
436 struct timer_list timer;
437 spinlock_t lock;
438 int pending;
439 };
440
441 struct hdsp {
442 spinlock_t lock;
443 struct snd_pcm_substream *capture_substream;
444 struct snd_pcm_substream *playback_substream;
445 struct hdsp_midi midi[2];
446 struct tasklet_struct midi_tasklet;
447 int use_midi_tasklet;
448 int precise_ptr;
449 u32 control_register; /* cached value */
450 u32 control2_register; /* cached value */
451 u32 creg_spdif;
452 u32 creg_spdif_stream;
453 int clock_source_locked;
454 char *card_name; /* digiface/multiface */
455 enum HDSP_IO_Type io_type; /* ditto, but for code use */
456 unsigned short firmware_rev;
457 unsigned short state; /* stores state bits */
458 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
459 size_t period_bytes; /* guess what this is */
460 unsigned char max_channels;
461 unsigned char qs_in_channels; /* quad speed mode for H9632 */
462 unsigned char ds_in_channels;
463 unsigned char ss_in_channels; /* different for multiface/digiface */
464 unsigned char qs_out_channels;
465 unsigned char ds_out_channels;
466 unsigned char ss_out_channels;
467
468 struct snd_dma_buffer capture_dma_buf;
469 struct snd_dma_buffer playback_dma_buf;
470 unsigned char *capture_buffer; /* suitably aligned address */
471 unsigned char *playback_buffer; /* suitably aligned address */
472
473 pid_t capture_pid;
474 pid_t playback_pid;
475 int running;
476 int system_sample_rate;
477 char *channel_map;
478 int dev;
479 int irq;
480 unsigned long port;
481 void __iomem *iobase;
482 struct snd_card *card;
483 struct snd_pcm *pcm;
484 struct snd_hwdep *hwdep;
485 struct pci_dev *pci;
486 struct snd_kcontrol *spdif_ctl;
487 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
488 unsigned int dds_value; /* last value written to freq register */
489 };
490
491 /* These tables map the ALSA channels 1..N to the channels that we
492 need to use in order to find the relevant channel buffer. RME
493 refer to this kind of mapping as between "the ADAT channel and
494 the DMA channel." We index it using the logical audio channel,
495 and the value is the DMA channel (i.e. channel buffer number)
496 where the data for that channel can be read/written from/to.
497 */
498
499 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
500 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
501 18, 19, 20, 21, 22, 23, 24, 25
502 };
503
504 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
505 /* Analog */
506 0, 1, 2, 3, 4, 5, 6, 7,
507 /* ADAT 2 */
508 16, 17, 18, 19, 20, 21, 22, 23,
509 /* SPDIF */
510 24, 25,
511 -1, -1, -1, -1, -1, -1, -1, -1
512 };
513
514 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
515 /* ADAT channels are remapped */
516 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
517 /* channels 12 and 13 are S/PDIF */
518 24, 25,
519 /* others don't exist */
520 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
521 };
522
523 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
524 /* ADAT channels */
525 0, 1, 2, 3, 4, 5, 6, 7,
526 /* SPDIF */
527 8, 9,
528 /* Analog */
529 10, 11,
530 /* AO4S-192 and AI4S-192 extension boards */
531 12, 13, 14, 15,
532 /* others don't exist */
533 -1, -1, -1, -1, -1, -1, -1, -1,
534 -1, -1
535 };
536
537 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
538 /* ADAT */
539 1, 3, 5, 7,
540 /* SPDIF */
541 8, 9,
542 /* Analog */
543 10, 11,
544 /* AO4S-192 and AI4S-192 extension boards */
545 12, 13, 14, 15,
546 /* others don't exist */
547 -1, -1, -1, -1, -1, -1, -1, -1,
548 -1, -1, -1, -1, -1, -1
549 };
550
551 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
552 /* ADAT is disabled in this mode */
553 /* SPDIF */
554 8, 9,
555 /* Analog */
556 10, 11,
557 /* AO4S-192 and AI4S-192 extension boards */
558 12, 13, 14, 15,
559 /* others don't exist */
560 -1, -1, -1, -1, -1, -1, -1, -1,
561 -1, -1, -1, -1, -1, -1, -1, -1,
562 -1, -1
563 };
564
565 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
566 {
567 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
568 dmab->dev.dev = snd_dma_pci_data(pci);
569 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
570 if (dmab->bytes >= size)
571 return 0;
572 }
573 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
574 size, dmab) < 0)
575 return -ENOMEM;
576 return 0;
577 }
578
579 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
580 {
581 if (dmab->area) {
582 dmab->dev.dev = NULL; /* make it anonymous */
583 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
584 }
585 }
586
587
588 static struct pci_device_id snd_hdsp_ids[] = {
589 {
590 .vendor = PCI_VENDOR_ID_XILINX,
591 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
592 .subvendor = PCI_ANY_ID,
593 .subdevice = PCI_ANY_ID,
594 }, /* RME Hammerfall-DSP */
595 { 0, },
596 };
597
598 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
599
600 /* prototypes */
601 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
602 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
603 static int snd_hdsp_enable_io (struct hdsp *hdsp);
604 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
605 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
606 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
607 static int hdsp_autosync_ref(struct hdsp *hdsp);
608 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
609 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
610
611 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
612 {
613 switch (hdsp->io_type) {
614 case Multiface:
615 case Digiface:
616 default:
617 if (hdsp->firmware_rev == 0xa)
618 return (64 * out) + (32 + (in));
619 else
620 return (52 * out) + (26 + (in));
621 case H9632:
622 return (32 * out) + (16 + (in));
623 case H9652:
624 return (52 * out) + (26 + (in));
625 }
626 }
627
628 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
629 {
630 switch (hdsp->io_type) {
631 case Multiface:
632 case Digiface:
633 default:
634 if (hdsp->firmware_rev == 0xa)
635 return (64 * out) + in;
636 else
637 return (52 * out) + in;
638 case H9632:
639 return (32 * out) + in;
640 case H9652:
641 return (52 * out) + in;
642 }
643 }
644
645 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
646 {
647 writel(val, hdsp->iobase + reg);
648 }
649
650 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
651 {
652 return readl (hdsp->iobase + reg);
653 }
654
655 static int hdsp_check_for_iobox (struct hdsp *hdsp)
656 {
657 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
658 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
659 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
660 hdsp->state &= ~HDSP_FirmwareLoaded;
661 return -EIO;
662 }
663 return 0;
664 }
665
666 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
667 unsigned int delay)
668 {
669 unsigned int i;
670
671 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
672 return 0;
673
674 for (i = 0; i != loops; ++i) {
675 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
676 msleep(delay);
677 else {
678 snd_printd("Hammerfall-DSP: iobox found after %ums!\n",
679 i * delay);
680 return 0;
681 }
682 }
683
684 snd_printk("Hammerfall-DSP: no Digiface or Multiface connected!\n");
685 hdsp->state &= ~HDSP_FirmwareLoaded;
686 return -EIO;
687 }
688
689 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
690
691 int i;
692 unsigned long flags;
693
694 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
695
696 snd_printk ("Hammerfall-DSP: loading firmware\n");
697
698 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
699 hdsp_write (hdsp, HDSP_fifoData, 0);
700
701 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
702 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
703 return -EIO;
704 }
705
706 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
707
708 for (i = 0; i < 24413; ++i) {
709 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
710 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
711 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
712 return -EIO;
713 }
714 }
715
716 ssleep(3);
717
718 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
719 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
720 return -EIO;
721 }
722
723 #ifdef SNDRV_BIG_ENDIAN
724 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
725 #else
726 hdsp->control2_register = 0;
727 #endif
728 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
729 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
730
731 }
732 if (hdsp->state & HDSP_InitializationComplete) {
733 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
734 spin_lock_irqsave(&hdsp->lock, flags);
735 snd_hdsp_set_defaults(hdsp);
736 spin_unlock_irqrestore(&hdsp->lock, flags);
737 }
738
739 hdsp->state |= HDSP_FirmwareLoaded;
740
741 return 0;
742 }
743
744 static int hdsp_get_iobox_version (struct hdsp *hdsp)
745 {
746 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
747
748 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
749 hdsp_write (hdsp, HDSP_fifoData, 0);
750 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
751 return -EIO;
752
753 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
754 hdsp_write (hdsp, HDSP_fifoData, 0);
755
756 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
757 hdsp->io_type = Multiface;
758 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
759 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
760 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
761 } else {
762 hdsp->io_type = Digiface;
763 }
764 } else {
765 /* firmware was already loaded, get iobox type */
766 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
767 hdsp->io_type = Multiface;
768 else
769 hdsp->io_type = Digiface;
770 }
771 return 0;
772 }
773
774
775 #ifdef HDSP_FW_LOADER
776 static int hdsp_request_fw_loader(struct hdsp *hdsp);
777 #endif
778
779 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
780 {
781 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
782 return 0;
783 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
784 hdsp->state &= ~HDSP_FirmwareLoaded;
785 if (! load_on_demand)
786 return -EIO;
787 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
788 /* try to load firmware */
789 if (! (hdsp->state & HDSP_FirmwareCached)) {
790 #ifdef HDSP_FW_LOADER
791 if (! hdsp_request_fw_loader(hdsp))
792 return 0;
793 #endif
794 snd_printk(KERN_ERR
795 "Hammerfall-DSP: No firmware loaded nor "
796 "cached, please upload firmware.\n");
797 return -EIO;
798 }
799 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
800 snd_printk(KERN_ERR
801 "Hammerfall-DSP: Firmware loading from "
802 "cache failed, please upload manually.\n");
803 return -EIO;
804 }
805 }
806 return 0;
807 }
808
809
810 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
811 {
812 int i;
813
814 /* the fifoStatus registers reports on how many words
815 are available in the command FIFO.
816 */
817
818 for (i = 0; i < timeout; i++) {
819
820 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
821 return 0;
822
823 /* not very friendly, but we only do this during a firmware
824 load and changing the mixer, so we just put up with it.
825 */
826
827 udelay (100);
828 }
829
830 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
831 count, timeout);
832 return -1;
833 }
834
835 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
836 {
837 if (addr >= HDSP_MATRIX_MIXER_SIZE)
838 return 0;
839
840 return hdsp->mixer_matrix[addr];
841 }
842
843 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
844 {
845 unsigned int ad;
846
847 if (addr >= HDSP_MATRIX_MIXER_SIZE)
848 return -1;
849
850 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
851
852 /* from martin bjornsen:
853
854 "You can only write dwords to the
855 mixer memory which contain two
856 mixer values in the low and high
857 word. So if you want to change
858 value 0 you have to read value 1
859 from the cache and write both to
860 the first dword in the mixer
861 memory."
862 */
863
864 if (hdsp->io_type == H9632 && addr >= 512)
865 return 0;
866
867 if (hdsp->io_type == H9652 && addr >= 1352)
868 return 0;
869
870 hdsp->mixer_matrix[addr] = data;
871
872
873 /* `addr' addresses a 16-bit wide address, but
874 the address space accessed via hdsp_write
875 uses byte offsets. put another way, addr
876 varies from 0 to 1351, but to access the
877 corresponding memory location, we need
878 to access 0 to 2703 ...
879 */
880 ad = addr/2;
881
882 hdsp_write (hdsp, 4096 + (ad*4),
883 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
884 hdsp->mixer_matrix[addr&0x7fe]);
885
886 return 0;
887
888 } else {
889
890 ad = (addr << 16) + data;
891
892 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
893 return -1;
894
895 hdsp_write (hdsp, HDSP_fifoData, ad);
896 hdsp->mixer_matrix[addr] = data;
897
898 }
899
900 return 0;
901 }
902
903 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
904 {
905 unsigned long flags;
906 int ret = 1;
907
908 spin_lock_irqsave(&hdsp->lock, flags);
909 if ((hdsp->playback_pid != hdsp->capture_pid) &&
910 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
911 ret = 0;
912 spin_unlock_irqrestore(&hdsp->lock, flags);
913 return ret;
914 }
915
916 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
917 {
918 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
919 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
920
921 /* For the 9632, the mask is different */
922 if (hdsp->io_type == H9632)
923 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
924
925 if (status & HDSP_SPDIFErrorFlag)
926 return 0;
927
928 switch (rate_bits) {
929 case HDSP_spdifFrequency32KHz: return 32000;
930 case HDSP_spdifFrequency44_1KHz: return 44100;
931 case HDSP_spdifFrequency48KHz: return 48000;
932 case HDSP_spdifFrequency64KHz: return 64000;
933 case HDSP_spdifFrequency88_2KHz: return 88200;
934 case HDSP_spdifFrequency96KHz: return 96000;
935 case HDSP_spdifFrequency128KHz:
936 if (hdsp->io_type == H9632) return 128000;
937 break;
938 case HDSP_spdifFrequency176_4KHz:
939 if (hdsp->io_type == H9632) return 176400;
940 break;
941 case HDSP_spdifFrequency192KHz:
942 if (hdsp->io_type == H9632) return 192000;
943 break;
944 default:
945 break;
946 }
947 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
948 return 0;
949 }
950
951 static int hdsp_external_sample_rate(struct hdsp *hdsp)
952 {
953 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
954 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
955
956 /* For the 9632 card, there seems to be no bit for indicating external
957 * sample rate greater than 96kHz. The card reports the corresponding
958 * single speed. So the best means seems to get spdif rate when
959 * autosync reference is spdif */
960 if (hdsp->io_type == H9632 &&
961 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
962 return hdsp_spdif_sample_rate(hdsp);
963
964 switch (rate_bits) {
965 case HDSP_systemFrequency32: return 32000;
966 case HDSP_systemFrequency44_1: return 44100;
967 case HDSP_systemFrequency48: return 48000;
968 case HDSP_systemFrequency64: return 64000;
969 case HDSP_systemFrequency88_2: return 88200;
970 case HDSP_systemFrequency96: return 96000;
971 default:
972 return 0;
973 }
974 }
975
976 static void hdsp_compute_period_size(struct hdsp *hdsp)
977 {
978 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
979 }
980
981 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
982 {
983 int position;
984
985 position = hdsp_read(hdsp, HDSP_statusRegister);
986
987 if (!hdsp->precise_ptr)
988 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
989
990 position &= HDSP_BufferPositionMask;
991 position /= 4;
992 position &= (hdsp->period_bytes/2) - 1;
993 return position;
994 }
995
996 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
997 {
998 hdsp_write (hdsp, HDSP_resetPointer, 0);
999 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1000 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1001 * requires (?) to write again DDS value after a reset pointer
1002 * (at least, it works like this) */
1003 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1004 }
1005
1006 static void hdsp_start_audio(struct hdsp *s)
1007 {
1008 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1009 hdsp_write(s, HDSP_controlRegister, s->control_register);
1010 }
1011
1012 static void hdsp_stop_audio(struct hdsp *s)
1013 {
1014 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1015 hdsp_write(s, HDSP_controlRegister, s->control_register);
1016 }
1017
1018 static void hdsp_silence_playback(struct hdsp *hdsp)
1019 {
1020 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1021 }
1022
1023 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1024 {
1025 int n;
1026
1027 spin_lock_irq(&s->lock);
1028
1029 frames >>= 7;
1030 n = 0;
1031 while (frames) {
1032 n++;
1033 frames >>= 1;
1034 }
1035
1036 s->control_register &= ~HDSP_LatencyMask;
1037 s->control_register |= hdsp_encode_latency(n);
1038
1039 hdsp_write(s, HDSP_controlRegister, s->control_register);
1040
1041 hdsp_compute_period_size(s);
1042
1043 spin_unlock_irq(&s->lock);
1044
1045 return 0;
1046 }
1047
1048 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1049 {
1050 u64 n;
1051
1052 if (rate >= 112000)
1053 rate /= 4;
1054 else if (rate >= 56000)
1055 rate /= 2;
1056
1057 n = DDS_NUMERATOR;
1058 n = div_u64(n, rate);
1059 /* n should be less than 2^32 for being written to FREQ register */
1060 snd_BUG_ON(n >> 32);
1061 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1062 value to write it after a reset */
1063 hdsp->dds_value = n;
1064 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1065 }
1066
1067 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1068 {
1069 int reject_if_open = 0;
1070 int current_rate;
1071 int rate_bits;
1072
1073 /* ASSUMPTION: hdsp->lock is either held, or
1074 there is no need for it (e.g. during module
1075 initialization).
1076 */
1077
1078 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1079 if (called_internally) {
1080 /* request from ctl or card initialization */
1081 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1082 return -1;
1083 } else {
1084 /* hw_param request while in AutoSync mode */
1085 int external_freq = hdsp_external_sample_rate(hdsp);
1086 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1087
1088 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1089 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1090 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1091 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1092 else if (rate != external_freq) {
1093 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1094 return -1;
1095 }
1096 }
1097 }
1098
1099 current_rate = hdsp->system_sample_rate;
1100
1101 /* Changing from a "single speed" to a "double speed" rate is
1102 not allowed if any substreams are open. This is because
1103 such a change causes a shift in the location of
1104 the DMA buffers and a reduction in the number of available
1105 buffers.
1106
1107 Note that a similar but essentially insoluble problem
1108 exists for externally-driven rate changes. All we can do
1109 is to flag rate changes in the read/write routines. */
1110
1111 if (rate > 96000 && hdsp->io_type != H9632)
1112 return -EINVAL;
1113
1114 switch (rate) {
1115 case 32000:
1116 if (current_rate > 48000)
1117 reject_if_open = 1;
1118 rate_bits = HDSP_Frequency32KHz;
1119 break;
1120 case 44100:
1121 if (current_rate > 48000)
1122 reject_if_open = 1;
1123 rate_bits = HDSP_Frequency44_1KHz;
1124 break;
1125 case 48000:
1126 if (current_rate > 48000)
1127 reject_if_open = 1;
1128 rate_bits = HDSP_Frequency48KHz;
1129 break;
1130 case 64000:
1131 if (current_rate <= 48000 || current_rate > 96000)
1132 reject_if_open = 1;
1133 rate_bits = HDSP_Frequency64KHz;
1134 break;
1135 case 88200:
1136 if (current_rate <= 48000 || current_rate > 96000)
1137 reject_if_open = 1;
1138 rate_bits = HDSP_Frequency88_2KHz;
1139 break;
1140 case 96000:
1141 if (current_rate <= 48000 || current_rate > 96000)
1142 reject_if_open = 1;
1143 rate_bits = HDSP_Frequency96KHz;
1144 break;
1145 case 128000:
1146 if (current_rate < 128000)
1147 reject_if_open = 1;
1148 rate_bits = HDSP_Frequency128KHz;
1149 break;
1150 case 176400:
1151 if (current_rate < 128000)
1152 reject_if_open = 1;
1153 rate_bits = HDSP_Frequency176_4KHz;
1154 break;
1155 case 192000:
1156 if (current_rate < 128000)
1157 reject_if_open = 1;
1158 rate_bits = HDSP_Frequency192KHz;
1159 break;
1160 default:
1161 return -EINVAL;
1162 }
1163
1164 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1165 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1166 hdsp->capture_pid,
1167 hdsp->playback_pid);
1168 return -EBUSY;
1169 }
1170
1171 hdsp->control_register &= ~HDSP_FrequencyMask;
1172 hdsp->control_register |= rate_bits;
1173 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1174
1175 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1176 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1177 hdsp_set_dds_value(hdsp, rate);
1178
1179 if (rate >= 128000) {
1180 hdsp->channel_map = channel_map_H9632_qs;
1181 } else if (rate > 48000) {
1182 if (hdsp->io_type == H9632)
1183 hdsp->channel_map = channel_map_H9632_ds;
1184 else
1185 hdsp->channel_map = channel_map_ds;
1186 } else {
1187 switch (hdsp->io_type) {
1188 case Multiface:
1189 hdsp->channel_map = channel_map_mf_ss;
1190 break;
1191 case Digiface:
1192 case H9652:
1193 hdsp->channel_map = channel_map_df_ss;
1194 break;
1195 case H9632:
1196 hdsp->channel_map = channel_map_H9632_ss;
1197 break;
1198 default:
1199 /* should never happen */
1200 break;
1201 }
1202 }
1203
1204 hdsp->system_sample_rate = rate;
1205
1206 return 0;
1207 }
1208
1209 /*----------------------------------------------------------------------------
1210 MIDI
1211 ----------------------------------------------------------------------------*/
1212
1213 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1214 {
1215 /* the hardware already does the relevant bit-mask with 0xff */
1216 if (id)
1217 return hdsp_read(hdsp, HDSP_midiDataIn1);
1218 else
1219 return hdsp_read(hdsp, HDSP_midiDataIn0);
1220 }
1221
1222 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1223 {
1224 /* the hardware already does the relevant bit-mask with 0xff */
1225 if (id)
1226 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1227 else
1228 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1229 }
1230
1231 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1232 {
1233 if (id)
1234 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1235 else
1236 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1237 }
1238
1239 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1240 {
1241 int fifo_bytes_used;
1242
1243 if (id)
1244 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1245 else
1246 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1247
1248 if (fifo_bytes_used < 128)
1249 return 128 - fifo_bytes_used;
1250 else
1251 return 0;
1252 }
1253
1254 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1255 {
1256 while (snd_hdsp_midi_input_available (hdsp, id))
1257 snd_hdsp_midi_read_byte (hdsp, id);
1258 }
1259
1260 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1261 {
1262 unsigned long flags;
1263 int n_pending;
1264 int to_write;
1265 int i;
1266 unsigned char buf[128];
1267
1268 /* Output is not interrupt driven */
1269
1270 spin_lock_irqsave (&hmidi->lock, flags);
1271 if (hmidi->output) {
1272 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1273 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1274 if (n_pending > (int)sizeof (buf))
1275 n_pending = sizeof (buf);
1276
1277 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1278 for (i = 0; i < to_write; ++i)
1279 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1280 }
1281 }
1282 }
1283 }
1284 spin_unlock_irqrestore (&hmidi->lock, flags);
1285 return 0;
1286 }
1287
1288 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1289 {
1290 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1291 unsigned long flags;
1292 int n_pending;
1293 int i;
1294
1295 spin_lock_irqsave (&hmidi->lock, flags);
1296 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1297 if (hmidi->input) {
1298 if (n_pending > (int)sizeof (buf))
1299 n_pending = sizeof (buf);
1300 for (i = 0; i < n_pending; ++i)
1301 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1302 if (n_pending)
1303 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1304 } else {
1305 /* flush the MIDI input FIFO */
1306 while (--n_pending)
1307 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1308 }
1309 }
1310 hmidi->pending = 0;
1311 if (hmidi->id)
1312 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1313 else
1314 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1315 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1316 spin_unlock_irqrestore (&hmidi->lock, flags);
1317 return snd_hdsp_midi_output_write (hmidi);
1318 }
1319
1320 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1321 {
1322 struct hdsp *hdsp;
1323 struct hdsp_midi *hmidi;
1324 unsigned long flags;
1325 u32 ie;
1326
1327 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1328 hdsp = hmidi->hdsp;
1329 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1330 spin_lock_irqsave (&hdsp->lock, flags);
1331 if (up) {
1332 if (!(hdsp->control_register & ie)) {
1333 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1334 hdsp->control_register |= ie;
1335 }
1336 } else {
1337 hdsp->control_register &= ~ie;
1338 tasklet_kill(&hdsp->midi_tasklet);
1339 }
1340
1341 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1342 spin_unlock_irqrestore (&hdsp->lock, flags);
1343 }
1344
1345 static void snd_hdsp_midi_output_timer(unsigned long data)
1346 {
1347 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1348 unsigned long flags;
1349
1350 snd_hdsp_midi_output_write(hmidi);
1351 spin_lock_irqsave (&hmidi->lock, flags);
1352
1353 /* this does not bump hmidi->istimer, because the
1354 kernel automatically removed the timer when it
1355 expired, and we are now adding it back, thus
1356 leaving istimer wherever it was set before.
1357 */
1358
1359 if (hmidi->istimer) {
1360 hmidi->timer.expires = 1 + jiffies;
1361 add_timer(&hmidi->timer);
1362 }
1363
1364 spin_unlock_irqrestore (&hmidi->lock, flags);
1365 }
1366
1367 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1368 {
1369 struct hdsp_midi *hmidi;
1370 unsigned long flags;
1371
1372 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1373 spin_lock_irqsave (&hmidi->lock, flags);
1374 if (up) {
1375 if (!hmidi->istimer) {
1376 init_timer(&hmidi->timer);
1377 hmidi->timer.function = snd_hdsp_midi_output_timer;
1378 hmidi->timer.data = (unsigned long) hmidi;
1379 hmidi->timer.expires = 1 + jiffies;
1380 add_timer(&hmidi->timer);
1381 hmidi->istimer++;
1382 }
1383 } else {
1384 if (hmidi->istimer && --hmidi->istimer <= 0)
1385 del_timer (&hmidi->timer);
1386 }
1387 spin_unlock_irqrestore (&hmidi->lock, flags);
1388 if (up)
1389 snd_hdsp_midi_output_write(hmidi);
1390 }
1391
1392 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1393 {
1394 struct hdsp_midi *hmidi;
1395
1396 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1397 spin_lock_irq (&hmidi->lock);
1398 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1399 hmidi->input = substream;
1400 spin_unlock_irq (&hmidi->lock);
1401
1402 return 0;
1403 }
1404
1405 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1406 {
1407 struct hdsp_midi *hmidi;
1408
1409 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1410 spin_lock_irq (&hmidi->lock);
1411 hmidi->output = substream;
1412 spin_unlock_irq (&hmidi->lock);
1413
1414 return 0;
1415 }
1416
1417 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1418 {
1419 struct hdsp_midi *hmidi;
1420
1421 snd_hdsp_midi_input_trigger (substream, 0);
1422
1423 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1424 spin_lock_irq (&hmidi->lock);
1425 hmidi->input = NULL;
1426 spin_unlock_irq (&hmidi->lock);
1427
1428 return 0;
1429 }
1430
1431 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1432 {
1433 struct hdsp_midi *hmidi;
1434
1435 snd_hdsp_midi_output_trigger (substream, 0);
1436
1437 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1438 spin_lock_irq (&hmidi->lock);
1439 hmidi->output = NULL;
1440 spin_unlock_irq (&hmidi->lock);
1441
1442 return 0;
1443 }
1444
1445 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1446 {
1447 .open = snd_hdsp_midi_output_open,
1448 .close = snd_hdsp_midi_output_close,
1449 .trigger = snd_hdsp_midi_output_trigger,
1450 };
1451
1452 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1453 {
1454 .open = snd_hdsp_midi_input_open,
1455 .close = snd_hdsp_midi_input_close,
1456 .trigger = snd_hdsp_midi_input_trigger,
1457 };
1458
1459 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1460 {
1461 char buf[32];
1462
1463 hdsp->midi[id].id = id;
1464 hdsp->midi[id].rmidi = NULL;
1465 hdsp->midi[id].input = NULL;
1466 hdsp->midi[id].output = NULL;
1467 hdsp->midi[id].hdsp = hdsp;
1468 hdsp->midi[id].istimer = 0;
1469 hdsp->midi[id].pending = 0;
1470 spin_lock_init (&hdsp->midi[id].lock);
1471
1472 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1473 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1474 return -1;
1475
1476 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1477 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1478
1479 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1480 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1481
1482 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1483 SNDRV_RAWMIDI_INFO_INPUT |
1484 SNDRV_RAWMIDI_INFO_DUPLEX;
1485
1486 return 0;
1487 }
1488
1489 /*-----------------------------------------------------------------------------
1490 Control Interface
1491 ----------------------------------------------------------------------------*/
1492
1493 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1494 {
1495 u32 val = 0;
1496 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1497 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1498 if (val & HDSP_SPDIFProfessional)
1499 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1500 else
1501 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1502 return val;
1503 }
1504
1505 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1506 {
1507 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1508 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1509 if (val & HDSP_SPDIFProfessional)
1510 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1511 else
1512 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1513 }
1514
1515 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1516 {
1517 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1518 uinfo->count = 1;
1519 return 0;
1520 }
1521
1522 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1523 {
1524 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1525
1526 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1527 return 0;
1528 }
1529
1530 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1531 {
1532 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1533 int change;
1534 u32 val;
1535
1536 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1537 spin_lock_irq(&hdsp->lock);
1538 change = val != hdsp->creg_spdif;
1539 hdsp->creg_spdif = val;
1540 spin_unlock_irq(&hdsp->lock);
1541 return change;
1542 }
1543
1544 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1545 {
1546 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1547 uinfo->count = 1;
1548 return 0;
1549 }
1550
1551 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1552 {
1553 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1554
1555 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1556 return 0;
1557 }
1558
1559 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1560 {
1561 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1562 int change;
1563 u32 val;
1564
1565 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1566 spin_lock_irq(&hdsp->lock);
1567 change = val != hdsp->creg_spdif_stream;
1568 hdsp->creg_spdif_stream = val;
1569 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1570 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1571 spin_unlock_irq(&hdsp->lock);
1572 return change;
1573 }
1574
1575 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1576 {
1577 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1578 uinfo->count = 1;
1579 return 0;
1580 }
1581
1582 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1583 {
1584 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1585 return 0;
1586 }
1587
1588 #define HDSP_SPDIF_IN(xname, xindex) \
1589 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1590 .name = xname, \
1591 .index = xindex, \
1592 .info = snd_hdsp_info_spdif_in, \
1593 .get = snd_hdsp_get_spdif_in, \
1594 .put = snd_hdsp_put_spdif_in }
1595
1596 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1597 {
1598 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1599 }
1600
1601 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1602 {
1603 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1604 hdsp->control_register |= hdsp_encode_spdif_in(in);
1605 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1606 return 0;
1607 }
1608
1609 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1610 {
1611 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1612 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1613
1614 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1615 uinfo->count = 1;
1616 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1617 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1618 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1619 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1620 return 0;
1621 }
1622
1623 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1624 {
1625 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1626
1627 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1628 return 0;
1629 }
1630
1631 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1632 {
1633 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1634 int change;
1635 unsigned int val;
1636
1637 if (!snd_hdsp_use_is_exclusive(hdsp))
1638 return -EBUSY;
1639 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1640 spin_lock_irq(&hdsp->lock);
1641 change = val != hdsp_spdif_in(hdsp);
1642 if (change)
1643 hdsp_set_spdif_input(hdsp, val);
1644 spin_unlock_irq(&hdsp->lock);
1645 return change;
1646 }
1647
1648 #define HDSP_SPDIF_OUT(xname, xindex) \
1649 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1650 .info = snd_hdsp_info_spdif_bits, \
1651 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1652
1653 static int hdsp_spdif_out(struct hdsp *hdsp)
1654 {
1655 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1656 }
1657
1658 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1659 {
1660 if (out)
1661 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1662 else
1663 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1664 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1665 return 0;
1666 }
1667
1668 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
1669
1670 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1671 {
1672 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1673
1674 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1675 return 0;
1676 }
1677
1678 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1679 {
1680 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1681 int change;
1682 unsigned int val;
1683
1684 if (!snd_hdsp_use_is_exclusive(hdsp))
1685 return -EBUSY;
1686 val = ucontrol->value.integer.value[0] & 1;
1687 spin_lock_irq(&hdsp->lock);
1688 change = (int)val != hdsp_spdif_out(hdsp);
1689 hdsp_set_spdif_output(hdsp, val);
1690 spin_unlock_irq(&hdsp->lock);
1691 return change;
1692 }
1693
1694 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1695 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1696 .info = snd_hdsp_info_spdif_bits, \
1697 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1698
1699 static int hdsp_spdif_professional(struct hdsp *hdsp)
1700 {
1701 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1702 }
1703
1704 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1705 {
1706 if (val)
1707 hdsp->control_register |= HDSP_SPDIFProfessional;
1708 else
1709 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1711 return 0;
1712 }
1713
1714 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1715 {
1716 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1717
1718 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1719 return 0;
1720 }
1721
1722 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1723 {
1724 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1725 int change;
1726 unsigned int val;
1727
1728 if (!snd_hdsp_use_is_exclusive(hdsp))
1729 return -EBUSY;
1730 val = ucontrol->value.integer.value[0] & 1;
1731 spin_lock_irq(&hdsp->lock);
1732 change = (int)val != hdsp_spdif_professional(hdsp);
1733 hdsp_set_spdif_professional(hdsp, val);
1734 spin_unlock_irq(&hdsp->lock);
1735 return change;
1736 }
1737
1738 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1739 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1740 .info = snd_hdsp_info_spdif_bits, \
1741 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1742
1743 static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1744 {
1745 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1746 }
1747
1748 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1749 {
1750 if (val)
1751 hdsp->control_register |= HDSP_SPDIFEmphasis;
1752 else
1753 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1754 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1755 return 0;
1756 }
1757
1758 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1759 {
1760 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1761
1762 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1763 return 0;
1764 }
1765
1766 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1767 {
1768 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1769 int change;
1770 unsigned int val;
1771
1772 if (!snd_hdsp_use_is_exclusive(hdsp))
1773 return -EBUSY;
1774 val = ucontrol->value.integer.value[0] & 1;
1775 spin_lock_irq(&hdsp->lock);
1776 change = (int)val != hdsp_spdif_emphasis(hdsp);
1777 hdsp_set_spdif_emphasis(hdsp, val);
1778 spin_unlock_irq(&hdsp->lock);
1779 return change;
1780 }
1781
1782 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1783 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1784 .info = snd_hdsp_info_spdif_bits, \
1785 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1786
1787 static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1788 {
1789 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1790 }
1791
1792 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1793 {
1794 if (val)
1795 hdsp->control_register |= HDSP_SPDIFNonAudio;
1796 else
1797 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1798 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1799 return 0;
1800 }
1801
1802 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1803 {
1804 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1805
1806 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1807 return 0;
1808 }
1809
1810 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1811 {
1812 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1813 int change;
1814 unsigned int val;
1815
1816 if (!snd_hdsp_use_is_exclusive(hdsp))
1817 return -EBUSY;
1818 val = ucontrol->value.integer.value[0] & 1;
1819 spin_lock_irq(&hdsp->lock);
1820 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1821 hdsp_set_spdif_nonaudio(hdsp, val);
1822 spin_unlock_irq(&hdsp->lock);
1823 return change;
1824 }
1825
1826 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1827 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1828 .name = xname, \
1829 .index = xindex, \
1830 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1831 .info = snd_hdsp_info_spdif_sample_rate, \
1832 .get = snd_hdsp_get_spdif_sample_rate \
1833 }
1834
1835 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1836 {
1837 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1838 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1839
1840 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1841 uinfo->count = 1;
1842 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1843 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1844 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1845 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1846 return 0;
1847 }
1848
1849 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1850 {
1851 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1852
1853 switch (hdsp_spdif_sample_rate(hdsp)) {
1854 case 32000:
1855 ucontrol->value.enumerated.item[0] = 0;
1856 break;
1857 case 44100:
1858 ucontrol->value.enumerated.item[0] = 1;
1859 break;
1860 case 48000:
1861 ucontrol->value.enumerated.item[0] = 2;
1862 break;
1863 case 64000:
1864 ucontrol->value.enumerated.item[0] = 3;
1865 break;
1866 case 88200:
1867 ucontrol->value.enumerated.item[0] = 4;
1868 break;
1869 case 96000:
1870 ucontrol->value.enumerated.item[0] = 5;
1871 break;
1872 case 128000:
1873 ucontrol->value.enumerated.item[0] = 7;
1874 break;
1875 case 176400:
1876 ucontrol->value.enumerated.item[0] = 8;
1877 break;
1878 case 192000:
1879 ucontrol->value.enumerated.item[0] = 9;
1880 break;
1881 default:
1882 ucontrol->value.enumerated.item[0] = 6;
1883 }
1884 return 0;
1885 }
1886
1887 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1888 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1889 .name = xname, \
1890 .index = xindex, \
1891 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1892 .info = snd_hdsp_info_system_sample_rate, \
1893 .get = snd_hdsp_get_system_sample_rate \
1894 }
1895
1896 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1897 {
1898 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1899 uinfo->count = 1;
1900 return 0;
1901 }
1902
1903 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1904 {
1905 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1906
1907 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1908 return 0;
1909 }
1910
1911 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1912 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1913 .name = xname, \
1914 .index = xindex, \
1915 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1916 .info = snd_hdsp_info_autosync_sample_rate, \
1917 .get = snd_hdsp_get_autosync_sample_rate \
1918 }
1919
1920 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1921 {
1922 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1923 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1924 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1925 uinfo->count = 1;
1926 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1927 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1928 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1929 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1930 return 0;
1931 }
1932
1933 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1934 {
1935 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1936
1937 switch (hdsp_external_sample_rate(hdsp)) {
1938 case 32000:
1939 ucontrol->value.enumerated.item[0] = 0;
1940 break;
1941 case 44100:
1942 ucontrol->value.enumerated.item[0] = 1;
1943 break;
1944 case 48000:
1945 ucontrol->value.enumerated.item[0] = 2;
1946 break;
1947 case 64000:
1948 ucontrol->value.enumerated.item[0] = 3;
1949 break;
1950 case 88200:
1951 ucontrol->value.enumerated.item[0] = 4;
1952 break;
1953 case 96000:
1954 ucontrol->value.enumerated.item[0] = 5;
1955 break;
1956 case 128000:
1957 ucontrol->value.enumerated.item[0] = 7;
1958 break;
1959 case 176400:
1960 ucontrol->value.enumerated.item[0] = 8;
1961 break;
1962 case 192000:
1963 ucontrol->value.enumerated.item[0] = 9;
1964 break;
1965 default:
1966 ucontrol->value.enumerated.item[0] = 6;
1967 }
1968 return 0;
1969 }
1970
1971 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1972 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1973 .name = xname, \
1974 .index = xindex, \
1975 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1976 .info = snd_hdsp_info_system_clock_mode, \
1977 .get = snd_hdsp_get_system_clock_mode \
1978 }
1979
1980 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1981 {
1982 if (hdsp->control_register & HDSP_ClockModeMaster)
1983 return 0;
1984 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1985 return 0;
1986 return 1;
1987 }
1988
1989 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1990 {
1991 static char *texts[] = {"Master", "Slave" };
1992
1993 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1994 uinfo->count = 1;
1995 uinfo->value.enumerated.items = 2;
1996 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1997 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1998 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1999 return 0;
2000 }
2001
2002 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2003 {
2004 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2005
2006 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2007 return 0;
2008 }
2009
2010 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2011 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2012 .name = xname, \
2013 .index = xindex, \
2014 .info = snd_hdsp_info_clock_source, \
2015 .get = snd_hdsp_get_clock_source, \
2016 .put = snd_hdsp_put_clock_source \
2017 }
2018
2019 static int hdsp_clock_source(struct hdsp *hdsp)
2020 {
2021 if (hdsp->control_register & HDSP_ClockModeMaster) {
2022 switch (hdsp->system_sample_rate) {
2023 case 32000:
2024 return 1;
2025 case 44100:
2026 return 2;
2027 case 48000:
2028 return 3;
2029 case 64000:
2030 return 4;
2031 case 88200:
2032 return 5;
2033 case 96000:
2034 return 6;
2035 case 128000:
2036 return 7;
2037 case 176400:
2038 return 8;
2039 case 192000:
2040 return 9;
2041 default:
2042 return 3;
2043 }
2044 } else {
2045 return 0;
2046 }
2047 }
2048
2049 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2050 {
2051 int rate;
2052 switch (mode) {
2053 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2054 if (hdsp_external_sample_rate(hdsp) != 0) {
2055 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2056 hdsp->control_register &= ~HDSP_ClockModeMaster;
2057 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2058 return 0;
2059 }
2060 }
2061 return -1;
2062 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2063 rate = 32000;
2064 break;
2065 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2066 rate = 44100;
2067 break;
2068 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2069 rate = 48000;
2070 break;
2071 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2072 rate = 64000;
2073 break;
2074 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2075 rate = 88200;
2076 break;
2077 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2078 rate = 96000;
2079 break;
2080 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2081 rate = 128000;
2082 break;
2083 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2084 rate = 176400;
2085 break;
2086 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2087 rate = 192000;
2088 break;
2089 default:
2090 rate = 48000;
2091 }
2092 hdsp->control_register |= HDSP_ClockModeMaster;
2093 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2094 hdsp_set_rate(hdsp, rate, 1);
2095 return 0;
2096 }
2097
2098 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2099 {
2100 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2101 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2102
2103 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2104 uinfo->count = 1;
2105 if (hdsp->io_type == H9632)
2106 uinfo->value.enumerated.items = 10;
2107 else
2108 uinfo->value.enumerated.items = 7;
2109 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2110 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2111 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2112 return 0;
2113 }
2114
2115 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2116 {
2117 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2118
2119 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2120 return 0;
2121 }
2122
2123 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2124 {
2125 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2126 int change;
2127 int val;
2128
2129 if (!snd_hdsp_use_is_exclusive(hdsp))
2130 return -EBUSY;
2131 val = ucontrol->value.enumerated.item[0];
2132 if (val < 0) val = 0;
2133 if (hdsp->io_type == H9632) {
2134 if (val > 9)
2135 val = 9;
2136 } else {
2137 if (val > 6)
2138 val = 6;
2139 }
2140 spin_lock_irq(&hdsp->lock);
2141 if (val != hdsp_clock_source(hdsp))
2142 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2143 else
2144 change = 0;
2145 spin_unlock_irq(&hdsp->lock);
2146 return change;
2147 }
2148
2149 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2150
2151 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2152 {
2153 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2154
2155 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2156 return 0;
2157 }
2158
2159 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2160 {
2161 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2162 int change;
2163
2164 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2165 if (change)
2166 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2167 return change;
2168 }
2169
2170 #define HDSP_DA_GAIN(xname, xindex) \
2171 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2172 .name = xname, \
2173 .index = xindex, \
2174 .info = snd_hdsp_info_da_gain, \
2175 .get = snd_hdsp_get_da_gain, \
2176 .put = snd_hdsp_put_da_gain \
2177 }
2178
2179 static int hdsp_da_gain(struct hdsp *hdsp)
2180 {
2181 switch (hdsp->control_register & HDSP_DAGainMask) {
2182 case HDSP_DAGainHighGain:
2183 return 0;
2184 case HDSP_DAGainPlus4dBu:
2185 return 1;
2186 case HDSP_DAGainMinus10dBV:
2187 return 2;
2188 default:
2189 return 1;
2190 }
2191 }
2192
2193 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2194 {
2195 hdsp->control_register &= ~HDSP_DAGainMask;
2196 switch (mode) {
2197 case 0:
2198 hdsp->control_register |= HDSP_DAGainHighGain;
2199 break;
2200 case 1:
2201 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2202 break;
2203 case 2:
2204 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2205 break;
2206 default:
2207 return -1;
2208
2209 }
2210 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2211 return 0;
2212 }
2213
2214 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2215 {
2216 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2217
2218 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2219 uinfo->count = 1;
2220 uinfo->value.enumerated.items = 3;
2221 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2222 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2223 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2224 return 0;
2225 }
2226
2227 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2228 {
2229 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2230
2231 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2232 return 0;
2233 }
2234
2235 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2236 {
2237 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2238 int change;
2239 int val;
2240
2241 if (!snd_hdsp_use_is_exclusive(hdsp))
2242 return -EBUSY;
2243 val = ucontrol->value.enumerated.item[0];
2244 if (val < 0) val = 0;
2245 if (val > 2) val = 2;
2246 spin_lock_irq(&hdsp->lock);
2247 if (val != hdsp_da_gain(hdsp))
2248 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2249 else
2250 change = 0;
2251 spin_unlock_irq(&hdsp->lock);
2252 return change;
2253 }
2254
2255 #define HDSP_AD_GAIN(xname, xindex) \
2256 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2257 .name = xname, \
2258 .index = xindex, \
2259 .info = snd_hdsp_info_ad_gain, \
2260 .get = snd_hdsp_get_ad_gain, \
2261 .put = snd_hdsp_put_ad_gain \
2262 }
2263
2264 static int hdsp_ad_gain(struct hdsp *hdsp)
2265 {
2266 switch (hdsp->control_register & HDSP_ADGainMask) {
2267 case HDSP_ADGainMinus10dBV:
2268 return 0;
2269 case HDSP_ADGainPlus4dBu:
2270 return 1;
2271 case HDSP_ADGainLowGain:
2272 return 2;
2273 default:
2274 return 1;
2275 }
2276 }
2277
2278 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2279 {
2280 hdsp->control_register &= ~HDSP_ADGainMask;
2281 switch (mode) {
2282 case 0:
2283 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2284 break;
2285 case 1:
2286 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2287 break;
2288 case 2:
2289 hdsp->control_register |= HDSP_ADGainLowGain;
2290 break;
2291 default:
2292 return -1;
2293
2294 }
2295 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2296 return 0;
2297 }
2298
2299 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2300 {
2301 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2302
2303 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2304 uinfo->count = 1;
2305 uinfo->value.enumerated.items = 3;
2306 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2307 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2308 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2309 return 0;
2310 }
2311
2312 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2313 {
2314 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2315
2316 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2317 return 0;
2318 }
2319
2320 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2321 {
2322 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2323 int change;
2324 int val;
2325
2326 if (!snd_hdsp_use_is_exclusive(hdsp))
2327 return -EBUSY;
2328 val = ucontrol->value.enumerated.item[0];
2329 if (val < 0) val = 0;
2330 if (val > 2) val = 2;
2331 spin_lock_irq(&hdsp->lock);
2332 if (val != hdsp_ad_gain(hdsp))
2333 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2334 else
2335 change = 0;
2336 spin_unlock_irq(&hdsp->lock);
2337 return change;
2338 }
2339
2340 #define HDSP_PHONE_GAIN(xname, xindex) \
2341 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2342 .name = xname, \
2343 .index = xindex, \
2344 .info = snd_hdsp_info_phone_gain, \
2345 .get = snd_hdsp_get_phone_gain, \
2346 .put = snd_hdsp_put_phone_gain \
2347 }
2348
2349 static int hdsp_phone_gain(struct hdsp *hdsp)
2350 {
2351 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2352 case HDSP_PhoneGain0dB:
2353 return 0;
2354 case HDSP_PhoneGainMinus6dB:
2355 return 1;
2356 case HDSP_PhoneGainMinus12dB:
2357 return 2;
2358 default:
2359 return 0;
2360 }
2361 }
2362
2363 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2364 {
2365 hdsp->control_register &= ~HDSP_PhoneGainMask;
2366 switch (mode) {
2367 case 0:
2368 hdsp->control_register |= HDSP_PhoneGain0dB;
2369 break;
2370 case 1:
2371 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2372 break;
2373 case 2:
2374 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2375 break;
2376 default:
2377 return -1;
2378
2379 }
2380 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2381 return 0;
2382 }
2383
2384 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2385 {
2386 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2387
2388 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2389 uinfo->count = 1;
2390 uinfo->value.enumerated.items = 3;
2391 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2392 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2393 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2394 return 0;
2395 }
2396
2397 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2398 {
2399 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2400
2401 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2402 return 0;
2403 }
2404
2405 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2406 {
2407 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2408 int change;
2409 int val;
2410
2411 if (!snd_hdsp_use_is_exclusive(hdsp))
2412 return -EBUSY;
2413 val = ucontrol->value.enumerated.item[0];
2414 if (val < 0) val = 0;
2415 if (val > 2) val = 2;
2416 spin_lock_irq(&hdsp->lock);
2417 if (val != hdsp_phone_gain(hdsp))
2418 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2419 else
2420 change = 0;
2421 spin_unlock_irq(&hdsp->lock);
2422 return change;
2423 }
2424
2425 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2427 .name = xname, \
2428 .index = xindex, \
2429 .info = snd_hdsp_info_xlr_breakout_cable, \
2430 .get = snd_hdsp_get_xlr_breakout_cable, \
2431 .put = snd_hdsp_put_xlr_breakout_cable \
2432 }
2433
2434 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
2435 {
2436 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2437 return 1;
2438 return 0;
2439 }
2440
2441 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
2442 {
2443 if (mode)
2444 hdsp->control_register |= HDSP_XLRBreakoutCable;
2445 else
2446 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2447 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2448 return 0;
2449 }
2450
2451 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
2452
2453 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2454 {
2455 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2456
2457 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2458 return 0;
2459 }
2460
2461 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2462 {
2463 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2464 int change;
2465 int val;
2466
2467 if (!snd_hdsp_use_is_exclusive(hdsp))
2468 return -EBUSY;
2469 val = ucontrol->value.integer.value[0] & 1;
2470 spin_lock_irq(&hdsp->lock);
2471 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2472 hdsp_set_xlr_breakout_cable(hdsp, val);
2473 spin_unlock_irq(&hdsp->lock);
2474 return change;
2475 }
2476
2477 /* (De)activates old RME Analog Extension Board
2478 These are connected to the internal ADAT connector
2479 Switching this on desactivates external ADAT
2480 */
2481 #define HDSP_AEB(xname, xindex) \
2482 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2483 .name = xname, \
2484 .index = xindex, \
2485 .info = snd_hdsp_info_aeb, \
2486 .get = snd_hdsp_get_aeb, \
2487 .put = snd_hdsp_put_aeb \
2488 }
2489
2490 static int hdsp_aeb(struct hdsp *hdsp)
2491 {
2492 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2493 return 1;
2494 return 0;
2495 }
2496
2497 static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
2498 {
2499 if (mode)
2500 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2501 else
2502 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2503 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2504 return 0;
2505 }
2506
2507 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
2508
2509 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2510 {
2511 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2512
2513 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2514 return 0;
2515 }
2516
2517 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2518 {
2519 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2520 int change;
2521 int val;
2522
2523 if (!snd_hdsp_use_is_exclusive(hdsp))
2524 return -EBUSY;
2525 val = ucontrol->value.integer.value[0] & 1;
2526 spin_lock_irq(&hdsp->lock);
2527 change = (int)val != hdsp_aeb(hdsp);
2528 hdsp_set_aeb(hdsp, val);
2529 spin_unlock_irq(&hdsp->lock);
2530 return change;
2531 }
2532
2533 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2534 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2535 .name = xname, \
2536 .index = xindex, \
2537 .info = snd_hdsp_info_pref_sync_ref, \
2538 .get = snd_hdsp_get_pref_sync_ref, \
2539 .put = snd_hdsp_put_pref_sync_ref \
2540 }
2541
2542 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2543 {
2544 /* Notice that this looks at the requested sync source,
2545 not the one actually in use.
2546 */
2547
2548 switch (hdsp->control_register & HDSP_SyncRefMask) {
2549 case HDSP_SyncRef_ADAT1:
2550 return HDSP_SYNC_FROM_ADAT1;
2551 case HDSP_SyncRef_ADAT2:
2552 return HDSP_SYNC_FROM_ADAT2;
2553 case HDSP_SyncRef_ADAT3:
2554 return HDSP_SYNC_FROM_ADAT3;
2555 case HDSP_SyncRef_SPDIF:
2556 return HDSP_SYNC_FROM_SPDIF;
2557 case HDSP_SyncRef_WORD:
2558 return HDSP_SYNC_FROM_WORD;
2559 case HDSP_SyncRef_ADAT_SYNC:
2560 return HDSP_SYNC_FROM_ADAT_SYNC;
2561 default:
2562 return HDSP_SYNC_FROM_WORD;
2563 }
2564 return 0;
2565 }
2566
2567 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2568 {
2569 hdsp->control_register &= ~HDSP_SyncRefMask;
2570 switch (pref) {
2571 case HDSP_SYNC_FROM_ADAT1:
2572 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2573 break;
2574 case HDSP_SYNC_FROM_ADAT2:
2575 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2576 break;
2577 case HDSP_SYNC_FROM_ADAT3:
2578 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2579 break;
2580 case HDSP_SYNC_FROM_SPDIF:
2581 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2582 break;
2583 case HDSP_SYNC_FROM_WORD:
2584 hdsp->control_register |= HDSP_SyncRef_WORD;
2585 break;
2586 case HDSP_SYNC_FROM_ADAT_SYNC:
2587 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2588 break;
2589 default:
2590 return -1;
2591 }
2592 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2593 return 0;
2594 }
2595
2596 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2597 {
2598 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2599 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2600
2601 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2602 uinfo->count = 1;
2603
2604 switch (hdsp->io_type) {
2605 case Digiface:
2606 case H9652:
2607 uinfo->value.enumerated.items = 6;
2608 break;
2609 case Multiface:
2610 uinfo->value.enumerated.items = 4;
2611 break;
2612 case H9632:
2613 uinfo->value.enumerated.items = 3;
2614 break;
2615 default:
2616 uinfo->value.enumerated.items = 0;
2617 break;
2618 }
2619
2620 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2621 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2622 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2623 return 0;
2624 }
2625
2626 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2627 {
2628 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2629
2630 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2631 return 0;
2632 }
2633
2634 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2635 {
2636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2637 int change, max;
2638 unsigned int val;
2639
2640 if (!snd_hdsp_use_is_exclusive(hdsp))
2641 return -EBUSY;
2642
2643 switch (hdsp->io_type) {
2644 case Digiface:
2645 case H9652:
2646 max = 6;
2647 break;
2648 case Multiface:
2649 max = 4;
2650 break;
2651 case H9632:
2652 max = 3;
2653 break;
2654 default:
2655 return -EIO;
2656 }
2657
2658 val = ucontrol->value.enumerated.item[0] % max;
2659 spin_lock_irq(&hdsp->lock);
2660 change = (int)val != hdsp_pref_sync_ref(hdsp);
2661 hdsp_set_pref_sync_ref(hdsp, val);
2662 spin_unlock_irq(&hdsp->lock);
2663 return change;
2664 }
2665
2666 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2667 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2668 .name = xname, \
2669 .index = xindex, \
2670 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2671 .info = snd_hdsp_info_autosync_ref, \
2672 .get = snd_hdsp_get_autosync_ref, \
2673 }
2674
2675 static int hdsp_autosync_ref(struct hdsp *hdsp)
2676 {
2677 /* This looks at the autosync selected sync reference */
2678 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2679
2680 switch (status2 & HDSP_SelSyncRefMask) {
2681 case HDSP_SelSyncRef_WORD:
2682 return HDSP_AUTOSYNC_FROM_WORD;
2683 case HDSP_SelSyncRef_ADAT_SYNC:
2684 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2685 case HDSP_SelSyncRef_SPDIF:
2686 return HDSP_AUTOSYNC_FROM_SPDIF;
2687 case HDSP_SelSyncRefMask:
2688 return HDSP_AUTOSYNC_FROM_NONE;
2689 case HDSP_SelSyncRef_ADAT1:
2690 return HDSP_AUTOSYNC_FROM_ADAT1;
2691 case HDSP_SelSyncRef_ADAT2:
2692 return HDSP_AUTOSYNC_FROM_ADAT2;
2693 case HDSP_SelSyncRef_ADAT3:
2694 return HDSP_AUTOSYNC_FROM_ADAT3;
2695 default:
2696 return HDSP_AUTOSYNC_FROM_WORD;
2697 }
2698 return 0;
2699 }
2700
2701 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2702 {
2703 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2704
2705 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2706 uinfo->count = 1;
2707 uinfo->value.enumerated.items = 7;
2708 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2709 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2710 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2711 return 0;
2712 }
2713
2714 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2715 {
2716 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2717
2718 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2719 return 0;
2720 }
2721
2722 #define HDSP_LINE_OUT(xname, xindex) \
2723 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2724 .name = xname, \
2725 .index = xindex, \
2726 .info = snd_hdsp_info_line_out, \
2727 .get = snd_hdsp_get_line_out, \
2728 .put = snd_hdsp_put_line_out \
2729 }
2730
2731 static int hdsp_line_out(struct hdsp *hdsp)
2732 {
2733 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2734 }
2735
2736 static int hdsp_set_line_output(struct hdsp *hdsp, int out)
2737 {
2738 if (out)
2739 hdsp->control_register |= HDSP_LineOut;
2740 else
2741 hdsp->control_register &= ~HDSP_LineOut;
2742 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2743 return 0;
2744 }
2745
2746 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
2747
2748 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2749 {
2750 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2751
2752 spin_lock_irq(&hdsp->lock);
2753 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2754 spin_unlock_irq(&hdsp->lock);
2755 return 0;
2756 }
2757
2758 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2759 {
2760 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2761 int change;
2762 unsigned int val;
2763
2764 if (!snd_hdsp_use_is_exclusive(hdsp))
2765 return -EBUSY;
2766 val = ucontrol->value.integer.value[0] & 1;
2767 spin_lock_irq(&hdsp->lock);
2768 change = (int)val != hdsp_line_out(hdsp);
2769 hdsp_set_line_output(hdsp, val);
2770 spin_unlock_irq(&hdsp->lock);
2771 return change;
2772 }
2773
2774 #define HDSP_PRECISE_POINTER(xname, xindex) \
2775 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2776 .name = xname, \
2777 .index = xindex, \
2778 .info = snd_hdsp_info_precise_pointer, \
2779 .get = snd_hdsp_get_precise_pointer, \
2780 .put = snd_hdsp_put_precise_pointer \
2781 }
2782
2783 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2784 {
2785 if (precise)
2786 hdsp->precise_ptr = 1;
2787 else
2788 hdsp->precise_ptr = 0;
2789 return 0;
2790 }
2791
2792 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2793
2794 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2795 {
2796 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2797
2798 spin_lock_irq(&hdsp->lock);
2799 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2800 spin_unlock_irq(&hdsp->lock);
2801 return 0;
2802 }
2803
2804 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2805 {
2806 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2807 int change;
2808 unsigned int val;
2809
2810 if (!snd_hdsp_use_is_exclusive(hdsp))
2811 return -EBUSY;
2812 val = ucontrol->value.integer.value[0] & 1;
2813 spin_lock_irq(&hdsp->lock);
2814 change = (int)val != hdsp->precise_ptr;
2815 hdsp_set_precise_pointer(hdsp, val);
2816 spin_unlock_irq(&hdsp->lock);
2817 return change;
2818 }
2819
2820 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2821 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2822 .name = xname, \
2823 .index = xindex, \
2824 .info = snd_hdsp_info_use_midi_tasklet, \
2825 .get = snd_hdsp_get_use_midi_tasklet, \
2826 .put = snd_hdsp_put_use_midi_tasklet \
2827 }
2828
2829 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2830 {
2831 if (use_tasklet)
2832 hdsp->use_midi_tasklet = 1;
2833 else
2834 hdsp->use_midi_tasklet = 0;
2835 return 0;
2836 }
2837
2838 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2839
2840 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2841 {
2842 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2843
2844 spin_lock_irq(&hdsp->lock);
2845 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2846 spin_unlock_irq(&hdsp->lock);
2847 return 0;
2848 }
2849
2850 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2851 {
2852 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2853 int change;
2854 unsigned int val;
2855
2856 if (!snd_hdsp_use_is_exclusive(hdsp))
2857 return -EBUSY;
2858 val = ucontrol->value.integer.value[0] & 1;
2859 spin_lock_irq(&hdsp->lock);
2860 change = (int)val != hdsp->use_midi_tasklet;
2861 hdsp_set_use_midi_tasklet(hdsp, val);
2862 spin_unlock_irq(&hdsp->lock);
2863 return change;
2864 }
2865
2866 #define HDSP_MIXER(xname, xindex) \
2867 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2868 .name = xname, \
2869 .index = xindex, \
2870 .device = 0, \
2871 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2872 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2873 .info = snd_hdsp_info_mixer, \
2874 .get = snd_hdsp_get_mixer, \
2875 .put = snd_hdsp_put_mixer \
2876 }
2877
2878 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2879 {
2880 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2881 uinfo->count = 3;
2882 uinfo->value.integer.min = 0;
2883 uinfo->value.integer.max = 65536;
2884 uinfo->value.integer.step = 1;
2885 return 0;
2886 }
2887
2888 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2889 {
2890 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2891 int source;
2892 int destination;
2893 int addr;
2894
2895 source = ucontrol->value.integer.value[0];
2896 destination = ucontrol->value.integer.value[1];
2897
2898 if (source >= hdsp->max_channels)
2899 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2900 else
2901 addr = hdsp_input_to_output_key(hdsp,source, destination);
2902
2903 spin_lock_irq(&hdsp->lock);
2904 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2905 spin_unlock_irq(&hdsp->lock);
2906 return 0;
2907 }
2908
2909 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2910 {
2911 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2912 int change;
2913 int source;
2914 int destination;
2915 int gain;
2916 int addr;
2917
2918 if (!snd_hdsp_use_is_exclusive(hdsp))
2919 return -EBUSY;
2920
2921 source = ucontrol->value.integer.value[0];
2922 destination = ucontrol->value.integer.value[1];
2923
2924 if (source >= hdsp->max_channels)
2925 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2926 else
2927 addr = hdsp_input_to_output_key(hdsp,source, destination);
2928
2929 gain = ucontrol->value.integer.value[2];
2930
2931 spin_lock_irq(&hdsp->lock);
2932 change = gain != hdsp_read_gain(hdsp, addr);
2933 if (change)
2934 hdsp_write_gain(hdsp, addr, gain);
2935 spin_unlock_irq(&hdsp->lock);
2936 return change;
2937 }
2938
2939 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2940 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2941 .name = xname, \
2942 .index = xindex, \
2943 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2944 .info = snd_hdsp_info_sync_check, \
2945 .get = snd_hdsp_get_wc_sync_check \
2946 }
2947
2948 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2949 {
2950 static char *texts[] = {"No Lock", "Lock", "Sync" };
2951 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2952 uinfo->count = 1;
2953 uinfo->value.enumerated.items = 3;
2954 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2955 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2956 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2957 return 0;
2958 }
2959
2960 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2961 {
2962 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2963 if (status2 & HDSP_wc_lock) {
2964 if (status2 & HDSP_wc_sync)
2965 return 2;
2966 else
2967 return 1;
2968 } else
2969 return 0;
2970 return 0;
2971 }
2972
2973 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2974 {
2975 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2976
2977 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2978 return 0;
2979 }
2980
2981 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2982 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2983 .name = xname, \
2984 .index = xindex, \
2985 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2986 .info = snd_hdsp_info_sync_check, \
2987 .get = snd_hdsp_get_spdif_sync_check \
2988 }
2989
2990 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2991 {
2992 int status = hdsp_read(hdsp, HDSP_statusRegister);
2993 if (status & HDSP_SPDIFErrorFlag)
2994 return 0;
2995 else {
2996 if (status & HDSP_SPDIFSync)
2997 return 2;
2998 else
2999 return 1;
3000 }
3001 return 0;
3002 }
3003
3004 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3005 {
3006 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3007
3008 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3009 return 0;
3010 }
3011
3012 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3014 .name = xname, \
3015 .index = xindex, \
3016 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3017 .info = snd_hdsp_info_sync_check, \
3018 .get = snd_hdsp_get_adatsync_sync_check \
3019 }
3020
3021 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
3022 {
3023 int status = hdsp_read(hdsp, HDSP_statusRegister);
3024 if (status & HDSP_TimecodeLock) {
3025 if (status & HDSP_TimecodeSync)
3026 return 2;
3027 else
3028 return 1;
3029 } else
3030 return 0;
3031 }
3032
3033 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3034 {
3035 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3036
3037 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3038 return 0;
3039 }
3040
3041 #define HDSP_ADAT_SYNC_CHECK \
3042 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3043 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3044 .info = snd_hdsp_info_sync_check, \
3045 .get = snd_hdsp_get_adat_sync_check \
3046 }
3047
3048 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
3049 {
3050 int status = hdsp_read(hdsp, HDSP_statusRegister);
3051
3052 if (status & (HDSP_Lock0>>idx)) {
3053 if (status & (HDSP_Sync0>>idx))
3054 return 2;
3055 else
3056 return 1;
3057 } else
3058 return 0;
3059 }
3060
3061 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3062 {
3063 int offset;
3064 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3065
3066 offset = ucontrol->id.index - 1;
3067 snd_BUG_ON(offset < 0);
3068
3069 switch (hdsp->io_type) {
3070 case Digiface:
3071 case H9652:
3072 if (offset >= 3)
3073 return -EINVAL;
3074 break;
3075 case Multiface:
3076 case H9632:
3077 if (offset >= 1)
3078 return -EINVAL;
3079 break;
3080 default:
3081 return -EIO;
3082 }
3083
3084 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3085 return 0;
3086 }
3087
3088 #define HDSP_DDS_OFFSET(xname, xindex) \
3089 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3090 .name = xname, \
3091 .index = xindex, \
3092 .info = snd_hdsp_info_dds_offset, \
3093 .get = snd_hdsp_get_dds_offset, \
3094 .put = snd_hdsp_put_dds_offset \
3095 }
3096
3097 static int hdsp_dds_offset(struct hdsp *hdsp)
3098 {
3099 u64 n;
3100 unsigned int dds_value = hdsp->dds_value;
3101 int system_sample_rate = hdsp->system_sample_rate;
3102
3103 if (!dds_value)
3104 return 0;
3105
3106 n = DDS_NUMERATOR;
3107 /*
3108 * dds_value = n / rate
3109 * rate = n / dds_value
3110 */
3111 n = div_u64(n, dds_value);
3112 if (system_sample_rate >= 112000)
3113 n *= 4;
3114 else if (system_sample_rate >= 56000)
3115 n *= 2;
3116 return ((int)n) - system_sample_rate;
3117 }
3118
3119 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
3120 {
3121 int rate = hdsp->system_sample_rate + offset_hz;
3122 hdsp_set_dds_value(hdsp, rate);
3123 return 0;
3124 }
3125
3126 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3127 {
3128 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3129 uinfo->count = 1;
3130 uinfo->value.integer.min = -5000;
3131 uinfo->value.integer.max = 5000;
3132 return 0;
3133 }
3134
3135 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3136 {
3137 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3138
3139 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
3140 return 0;
3141 }
3142
3143 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3144 {
3145 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3146 int change;
3147 int val;
3148
3149 if (!snd_hdsp_use_is_exclusive(hdsp))
3150 return -EBUSY;
3151 val = ucontrol->value.enumerated.item[0];
3152 spin_lock_irq(&hdsp->lock);
3153 if (val != hdsp_dds_offset(hdsp))
3154 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
3155 else
3156 change = 0;
3157 spin_unlock_irq(&hdsp->lock);
3158 return change;
3159 }
3160
3161 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
3162 HDSP_DA_GAIN("DA Gain", 0),
3163 HDSP_AD_GAIN("AD Gain", 0),
3164 HDSP_PHONE_GAIN("Phones Gain", 0),
3165 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
3166 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
3167 };
3168
3169 static struct snd_kcontrol_new snd_hdsp_controls[] = {
3170 {
3171 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3172 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3173 .info = snd_hdsp_control_spdif_info,
3174 .get = snd_hdsp_control_spdif_get,
3175 .put = snd_hdsp_control_spdif_put,
3176 },
3177 {
3178 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3179 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3180 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3181 .info = snd_hdsp_control_spdif_stream_info,
3182 .get = snd_hdsp_control_spdif_stream_get,
3183 .put = snd_hdsp_control_spdif_stream_put,
3184 },
3185 {
3186 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3187 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3188 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3189 .info = snd_hdsp_control_spdif_mask_info,
3190 .get = snd_hdsp_control_spdif_mask_get,
3191 .private_value = IEC958_AES0_NONAUDIO |
3192 IEC958_AES0_PROFESSIONAL |
3193 IEC958_AES0_CON_EMPHASIS,
3194 },
3195 {
3196 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3197 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3198 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3199 .info = snd_hdsp_control_spdif_mask_info,
3200 .get = snd_hdsp_control_spdif_mask_get,
3201 .private_value = IEC958_AES0_NONAUDIO |
3202 IEC958_AES0_PROFESSIONAL |
3203 IEC958_AES0_PRO_EMPHASIS,
3204 },
3205 HDSP_MIXER("Mixer", 0),
3206 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3207 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3208 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3209 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3210 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3211 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3212 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3213 {
3214 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3215 .name = "Sample Clock Source Locking",
3216 .info = snd_hdsp_info_clock_source_lock,
3217 .get = snd_hdsp_get_clock_source_lock,
3218 .put = snd_hdsp_put_clock_source_lock,
3219 },
3220 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3221 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3222 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3223 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3224 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3225 /* 'External Rate' complies with the alsa control naming scheme */
3226 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3227 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3228 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3229 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3230 HDSP_LINE_OUT("Line Out", 0),
3231 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3232 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3233 };
3234
3235 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3236 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3237
3238 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3239 {
3240 unsigned int idx;
3241 int err;
3242 struct snd_kcontrol *kctl;
3243
3244 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3245 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3246 return err;
3247 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3248 hdsp->spdif_ctl = kctl;
3249 }
3250
3251 /* ADAT SyncCheck status */
3252 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3253 snd_hdsp_adat_sync_check.index = 1;
3254 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3255 return err;
3256 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3257 for (idx = 1; idx < 3; ++idx) {
3258 snd_hdsp_adat_sync_check.index = idx+1;
3259 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3260 return err;
3261 }
3262 }
3263
3264 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3265 if (hdsp->io_type == H9632) {
3266 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3267 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3268 return err;
3269 }
3270 }
3271
3272 /* AEB control for H96xx card */
3273 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3274 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3275 return err;
3276 }
3277
3278 return 0;
3279 }
3280
3281 /*------------------------------------------------------------
3282 /proc interface
3283 ------------------------------------------------------------*/
3284
3285 static void
3286 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3287 {
3288 struct hdsp *hdsp = (struct hdsp *) entry->private_data;
3289 unsigned int status;
3290 unsigned int status2;
3291 char *pref_sync_ref;
3292 char *autosync_ref;
3293 char *system_clock_mode;
3294 char *clock_source;
3295 int x;
3296
3297 if (hdsp_check_for_iobox (hdsp)) {
3298 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3299 return;
3300 }
3301
3302 if (hdsp_check_for_firmware(hdsp, 0)) {
3303 if (hdsp->state & HDSP_FirmwareCached) {
3304 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3305 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3306 return;
3307 }
3308 } else {
3309 int err = -EINVAL;
3310 #ifdef HDSP_FW_LOADER
3311 err = hdsp_request_fw_loader(hdsp);
3312 #endif
3313 if (err < 0) {
3314 snd_iprintf(buffer,
3315 "No firmware loaded nor cached, "
3316 "please upload firmware.\n");
3317 return;
3318 }
3319 }
3320 }
3321
3322 status = hdsp_read(hdsp, HDSP_statusRegister);
3323 status2 = hdsp_read(hdsp, HDSP_status2Register);
3324
3325 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3326 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3327 hdsp->capture_buffer, hdsp->playback_buffer);
3328 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3329 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3330 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3331 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3332 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3333 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3334 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3335 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3336 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3337 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3338 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3339 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3340
3341 snd_iprintf(buffer, "\n");
3342
3343 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3344
3345 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3346 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3347 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3348 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3349
3350 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3351
3352 snd_iprintf(buffer, "\n");
3353
3354
3355 switch (hdsp_clock_source(hdsp)) {
3356 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3357 clock_source = "AutoSync";
3358 break;
3359 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3360 clock_source = "Internal 32 kHz";
3361 break;
3362 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3363 clock_source = "Internal 44.1 kHz";
3364 break;
3365 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3366 clock_source = "Internal 48 kHz";
3367 break;
3368 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3369 clock_source = "Internal 64 kHz";
3370 break;
3371 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3372 clock_source = "Internal 88.2 kHz";
3373 break;
3374 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3375 clock_source = "Internal 96 kHz";
3376 break;
3377 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3378 clock_source = "Internal 128 kHz";
3379 break;
3380 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3381 clock_source = "Internal 176.4 kHz";
3382 break;
3383 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3384 clock_source = "Internal 192 kHz";
3385 break;
3386 default:
3387 clock_source = "Error";
3388 }
3389 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3390
3391 if (hdsp_system_clock_mode(hdsp))
3392 system_clock_mode = "Slave";
3393 else
3394 system_clock_mode = "Master";
3395
3396 switch (hdsp_pref_sync_ref (hdsp)) {
3397 case HDSP_SYNC_FROM_WORD:
3398 pref_sync_ref = "Word Clock";
3399 break;
3400 case HDSP_SYNC_FROM_ADAT_SYNC:
3401 pref_sync_ref = "ADAT Sync";
3402 break;
3403 case HDSP_SYNC_FROM_SPDIF:
3404 pref_sync_ref = "SPDIF";
3405 break;
3406 case HDSP_SYNC_FROM_ADAT1:
3407 pref_sync_ref = "ADAT1";
3408 break;
3409 case HDSP_SYNC_FROM_ADAT2:
3410 pref_sync_ref = "ADAT2";
3411 break;
3412 case HDSP_SYNC_FROM_ADAT3:
3413 pref_sync_ref = "ADAT3";
3414 break;
3415 default:
3416 pref_sync_ref = "Word Clock";
3417 break;
3418 }
3419 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3420
3421 switch (hdsp_autosync_ref (hdsp)) {
3422 case HDSP_AUTOSYNC_FROM_WORD:
3423 autosync_ref = "Word Clock";
3424 break;
3425 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3426 autosync_ref = "ADAT Sync";
3427 break;
3428 case HDSP_AUTOSYNC_FROM_SPDIF:
3429 autosync_ref = "SPDIF";
3430 break;
3431 case HDSP_AUTOSYNC_FROM_NONE:
3432 autosync_ref = "None";
3433 break;
3434 case HDSP_AUTOSYNC_FROM_ADAT1:
3435 autosync_ref = "ADAT1";
3436 break;
3437 case HDSP_AUTOSYNC_FROM_ADAT2:
3438 autosync_ref = "ADAT2";
3439 break;
3440 case HDSP_AUTOSYNC_FROM_ADAT3:
3441 autosync_ref = "ADAT3";
3442 break;
3443 default:
3444 autosync_ref = "---";
3445 break;
3446 }
3447 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3448
3449 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3450
3451 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3452
3453 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3454 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3455
3456 snd_iprintf(buffer, "\n");
3457
3458 switch (hdsp_spdif_in(hdsp)) {
3459 case HDSP_SPDIFIN_OPTICAL:
3460 snd_iprintf(buffer, "IEC958 input: Optical\n");
3461 break;
3462 case HDSP_SPDIFIN_COAXIAL:
3463 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3464 break;
3465 case HDSP_SPDIFIN_INTERNAL:
3466 snd_iprintf(buffer, "IEC958 input: Internal\n");
3467 break;
3468 case HDSP_SPDIFIN_AES:
3469 snd_iprintf(buffer, "IEC958 input: AES\n");
3470 break;
3471 default:
3472 snd_iprintf(buffer, "IEC958 input: ???\n");
3473 break;
3474 }
3475
3476 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3477 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3478 else
3479 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3480
3481 if (hdsp->control_register & HDSP_SPDIFProfessional)
3482 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3483 else
3484 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3485
3486 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3487 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3488 else
3489 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3490
3491 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3492 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3493 else
3494 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3495 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
3496 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3497 else
3498 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3499
3500 snd_iprintf(buffer, "\n");
3501
3502 /* Sync Check */
3503 x = status & HDSP_Sync0;
3504 if (status & HDSP_Lock0)
3505 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3506 else
3507 snd_iprintf(buffer, "ADAT1: No Lock\n");
3508
3509 switch (hdsp->io_type) {
3510 case Digiface:
3511 case H9652:
3512 x = status & HDSP_Sync1;
3513 if (status & HDSP_Lock1)
3514 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3515 else
3516 snd_iprintf(buffer, "ADAT2: No Lock\n");
3517 x = status & HDSP_Sync2;
3518 if (status & HDSP_Lock2)
3519 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3520 else
3521 snd_iprintf(buffer, "ADAT3: No Lock\n");
3522 break;
3523 default:
3524 /* relax */
3525 break;
3526 }
3527
3528 x = status & HDSP_SPDIFSync;
3529 if (status & HDSP_SPDIFErrorFlag)
3530 snd_iprintf (buffer, "SPDIF: No Lock\n");
3531 else
3532 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3533
3534 x = status2 & HDSP_wc_sync;
3535 if (status2 & HDSP_wc_lock)
3536 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3537 else
3538 snd_iprintf (buffer, "Word Clock: No Lock\n");
3539
3540 x = status & HDSP_TimecodeSync;
3541 if (status & HDSP_TimecodeLock)
3542 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3543 else
3544 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3545
3546 snd_iprintf(buffer, "\n");
3547
3548 /* Informations about H9632 specific controls */
3549 if (hdsp->io_type == H9632) {
3550 char *tmp;
3551
3552 switch (hdsp_ad_gain(hdsp)) {
3553 case 0:
3554 tmp = "-10 dBV";
3555 break;
3556 case 1:
3557 tmp = "+4 dBu";
3558 break;
3559 default:
3560 tmp = "Lo Gain";
3561 break;
3562 }
3563 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3564
3565 switch (hdsp_da_gain(hdsp)) {
3566 case 0:
3567 tmp = "Hi Gain";
3568 break;
3569 case 1:
3570 tmp = "+4 dBu";
3571 break;
3572 default:
3573 tmp = "-10 dBV";
3574 break;
3575 }
3576 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3577
3578 switch (hdsp_phone_gain(hdsp)) {
3579 case 0:
3580 tmp = "0 dB";
3581 break;
3582 case 1:
3583 tmp = "-6 dB";
3584 break;
3585 default:
3586 tmp = "-12 dB";
3587 break;
3588 }
3589 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3590
3591 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3592
3593 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3594 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3595 else
3596 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3597 snd_iprintf(buffer, "\n");
3598 }
3599
3600 }
3601
3602 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3603 {
3604 struct snd_info_entry *entry;
3605
3606 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3607 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3608 }
3609
3610 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3611 {
3612 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3613 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3614 }
3615
3616 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
3617 {
3618 unsigned long pb_bus, cb_bus;
3619
3620 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3621 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3622 if (hdsp->capture_dma_buf.area)
3623 snd_dma_free_pages(&hdsp->capture_dma_buf);
3624 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3625 return -ENOMEM;
3626 }
3627
3628 /* Align to bus-space 64K boundary */
3629
3630 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3631 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3632
3633 /* Tell the card where it is */
3634
3635 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3636 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3637
3638 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3639 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3640
3641 return 0;
3642 }
3643
3644 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3645 {
3646 unsigned int i;
3647
3648 /* ASSUMPTION: hdsp->lock is either held, or
3649 there is no need to hold it (e.g. during module
3650 initialization).
3651 */
3652
3653 /* set defaults:
3654
3655 SPDIF Input via Coax
3656 Master clock mode
3657 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3658 which implies 2 4096 sample, 32Kbyte periods).
3659 Enable line out.
3660 */
3661
3662 hdsp->control_register = HDSP_ClockModeMaster |
3663 HDSP_SPDIFInputCoaxial |
3664 hdsp_encode_latency(7) |
3665 HDSP_LineOut;
3666
3667
3668 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3669
3670 #ifdef SNDRV_BIG_ENDIAN
3671 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3672 #else
3673 hdsp->control2_register = 0;
3674 #endif
3675 if (hdsp->io_type == H9652)
3676 snd_hdsp_9652_enable_mixer (hdsp);
3677 else
3678 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3679
3680 hdsp_reset_hw_pointer(hdsp);
3681 hdsp_compute_period_size(hdsp);
3682
3683 /* silence everything */
3684
3685 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3686 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3687
3688 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3689 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3690 return -EIO;
3691 }
3692
3693 /* H9632 specific defaults */
3694 if (hdsp->io_type == H9632) {
3695 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3696 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3697 }
3698
3699 /* set a default rate so that the channel map is set up.
3700 */
3701
3702 hdsp_set_rate(hdsp, 48000, 1);
3703
3704 return 0;
3705 }
3706
3707 static void hdsp_midi_tasklet(unsigned long arg)
3708 {
3709 struct hdsp *hdsp = (struct hdsp *)arg;
3710
3711 if (hdsp->midi[0].pending)
3712 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3713 if (hdsp->midi[1].pending)
3714 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3715 }
3716
3717 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3718 {
3719 struct hdsp *hdsp = (struct hdsp *) dev_id;
3720 unsigned int status;
3721 int audio;
3722 int midi0;
3723 int midi1;
3724 unsigned int midi0status;
3725 unsigned int midi1status;
3726 int schedule = 0;
3727
3728 status = hdsp_read(hdsp, HDSP_statusRegister);
3729
3730 audio = status & HDSP_audioIRQPending;
3731 midi0 = status & HDSP_midi0IRQPending;
3732 midi1 = status & HDSP_midi1IRQPending;
3733
3734 if (!audio && !midi0 && !midi1)
3735 return IRQ_NONE;
3736
3737 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3738
3739 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3740 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3741
3742 if (!(hdsp->state & HDSP_InitializationComplete))
3743 return IRQ_HANDLED;
3744
3745 if (audio) {
3746 if (hdsp->capture_substream)
3747 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3748
3749 if (hdsp->playback_substream)
3750 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3751 }
3752
3753 if (midi0 && midi0status) {
3754 if (hdsp->use_midi_tasklet) {
3755 /* we disable interrupts for this input until processing is done */
3756 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3757 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3758 hdsp->midi[0].pending = 1;
3759 schedule = 1;
3760 } else {
3761 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3762 }
3763 }
3764 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3765 if (hdsp->use_midi_tasklet) {
3766 /* we disable interrupts for this input until processing is done */
3767 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3768 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3769 hdsp->midi[1].pending = 1;
3770 schedule = 1;
3771 } else {
3772 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3773 }
3774 }
3775 if (hdsp->use_midi_tasklet && schedule)
3776 tasklet_schedule(&hdsp->midi_tasklet);
3777 return IRQ_HANDLED;
3778 }
3779
3780 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3781 {
3782 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3783 return hdsp_hw_pointer(hdsp);
3784 }
3785
3786 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3787 int stream,
3788 int channel)
3789
3790 {
3791 int mapped_channel;
3792
3793 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3794 return NULL;
3795
3796 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3797 return NULL;
3798
3799 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3800 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3801 else
3802 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3803 }
3804
3805 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3806 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3807 {
3808 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3809 char *channel_buf;
3810
3811 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3812 return -EINVAL;
3813
3814 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3815 if (snd_BUG_ON(!channel_buf))
3816 return -EIO;
3817 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3818 return -EFAULT;
3819 return count;
3820 }
3821
3822 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3823 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3824 {
3825 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3826 char *channel_buf;
3827
3828 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3829 return -EINVAL;
3830
3831 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3832 if (snd_BUG_ON(!channel_buf))
3833 return -EIO;
3834 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3835 return -EFAULT;
3836 return count;
3837 }
3838
3839 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3840 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3841 {
3842 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3843 char *channel_buf;
3844
3845 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3846 if (snd_BUG_ON(!channel_buf))
3847 return -EIO;
3848 memset(channel_buf + pos * 4, 0, count * 4);
3849 return count;
3850 }
3851
3852 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3853 {
3854 struct snd_pcm_runtime *runtime = substream->runtime;
3855 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3856 struct snd_pcm_substream *other;
3857 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3858 other = hdsp->capture_substream;
3859 else
3860 other = hdsp->playback_substream;
3861 if (hdsp->running)
3862 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3863 else
3864 runtime->status->hw_ptr = 0;
3865 if (other) {
3866 struct snd_pcm_substream *s;
3867 struct snd_pcm_runtime *oruntime = other->runtime;
3868 snd_pcm_group_for_each_entry(s, substream) {
3869 if (s == other) {
3870 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3871 break;
3872 }
3873 }
3874 }
3875 return 0;
3876 }
3877
3878 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3879 struct snd_pcm_hw_params *params)
3880 {
3881 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3882 int err;
3883 pid_t this_pid;
3884 pid_t other_pid;
3885
3886 if (hdsp_check_for_iobox (hdsp))
3887 return -EIO;
3888
3889 if (hdsp_check_for_firmware(hdsp, 1))
3890 return -EIO;
3891
3892 spin_lock_irq(&hdsp->lock);
3893
3894 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3895 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3896 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3897 this_pid = hdsp->playback_pid;
3898 other_pid = hdsp->capture_pid;
3899 } else {
3900 this_pid = hdsp->capture_pid;
3901 other_pid = hdsp->playback_pid;
3902 }
3903
3904 if ((other_pid > 0) && (this_pid != other_pid)) {
3905
3906 /* The other stream is open, and not by the same
3907 task as this one. Make sure that the parameters
3908 that matter are the same.
3909 */
3910
3911 if (params_rate(params) != hdsp->system_sample_rate) {
3912 spin_unlock_irq(&hdsp->lock);
3913 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3914 return -EBUSY;
3915 }
3916
3917 if (params_period_size(params) != hdsp->period_bytes / 4) {
3918 spin_unlock_irq(&hdsp->lock);
3919 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3920 return -EBUSY;
3921 }
3922
3923 /* We're fine. */
3924
3925 spin_unlock_irq(&hdsp->lock);
3926 return 0;
3927
3928 } else {
3929 spin_unlock_irq(&hdsp->lock);
3930 }
3931
3932 /* how to make sure that the rate matches an externally-set one ?
3933 */
3934
3935 spin_lock_irq(&hdsp->lock);
3936 if (! hdsp->clock_source_locked) {
3937 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3938 spin_unlock_irq(&hdsp->lock);
3939 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3940 return err;
3941 }
3942 }
3943 spin_unlock_irq(&hdsp->lock);
3944
3945 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3946 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3947 return err;
3948 }
3949
3950 return 0;
3951 }
3952
3953 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
3954 struct snd_pcm_channel_info *info)
3955 {
3956 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3957 int mapped_channel;
3958
3959 if (snd_BUG_ON(info->channel >= hdsp->max_channels))
3960 return -EINVAL;
3961
3962 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
3963 return -EINVAL;
3964
3965 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3966 info->first = 0;
3967 info->step = 32;
3968 return 0;
3969 }
3970
3971 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
3972 unsigned int cmd, void *arg)
3973 {
3974 switch (cmd) {
3975 case SNDRV_PCM_IOCTL1_RESET:
3976 return snd_hdsp_reset(substream);
3977 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3978 return snd_hdsp_channel_info(substream, arg);
3979 default:
3980 break;
3981 }
3982
3983 return snd_pcm_lib_ioctl(substream, cmd, arg);
3984 }
3985
3986 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
3987 {
3988 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3989 struct snd_pcm_substream *other;
3990 int running;
3991
3992 if (hdsp_check_for_iobox (hdsp))
3993 return -EIO;
3994
3995 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
3996 return -EIO;
3997
3998 spin_lock(&hdsp->lock);
3999 running = hdsp->running;
4000 switch (cmd) {
4001 case SNDRV_PCM_TRIGGER_START:
4002 running |= 1 << substream->stream;
4003 break;
4004 case SNDRV_PCM_TRIGGER_STOP:
4005 running &= ~(1 << substream->stream);
4006 break;
4007 default:
4008 snd_BUG();
4009 spin_unlock(&hdsp->lock);
4010 return -EINVAL;
4011 }
4012 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4013 other = hdsp->capture_substream;
4014 else
4015 other = hdsp->playback_substream;
4016
4017 if (other) {
4018 struct snd_pcm_substream *s;
4019 snd_pcm_group_for_each_entry(s, substream) {
4020 if (s == other) {
4021 snd_pcm_trigger_done(s, substream);
4022 if (cmd == SNDRV_PCM_TRIGGER_START)
4023 running |= 1 << s->stream;
4024 else
4025 running &= ~(1 << s->stream);
4026 goto _ok;
4027 }
4028 }
4029 if (cmd == SNDRV_PCM_TRIGGER_START) {
4030 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4031 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4032 hdsp_silence_playback(hdsp);
4033 } else {
4034 if (running &&
4035 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4036 hdsp_silence_playback(hdsp);
4037 }
4038 } else {
4039 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4040 hdsp_silence_playback(hdsp);
4041 }
4042 _ok:
4043 snd_pcm_trigger_done(substream, substream);
4044 if (!hdsp->running && running)
4045 hdsp_start_audio(hdsp);
4046 else if (hdsp->running && !running)
4047 hdsp_stop_audio(hdsp);
4048 hdsp->running = running;
4049 spin_unlock(&hdsp->lock);
4050
4051 return 0;
4052 }
4053
4054 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4055 {
4056 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4057 int result = 0;
4058
4059 if (hdsp_check_for_iobox (hdsp))
4060 return -EIO;
4061
4062 if (hdsp_check_for_firmware(hdsp, 1))
4063 return -EIO;
4064
4065 spin_lock_irq(&hdsp->lock);
4066 if (!hdsp->running)
4067 hdsp_reset_hw_pointer(hdsp);
4068 spin_unlock_irq(&hdsp->lock);
4069 return result;
4070 }
4071
4072 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4073 {
4074 .info = (SNDRV_PCM_INFO_MMAP |
4075 SNDRV_PCM_INFO_MMAP_VALID |
4076 SNDRV_PCM_INFO_NONINTERLEAVED |
4077 SNDRV_PCM_INFO_SYNC_START |
4078 SNDRV_PCM_INFO_DOUBLE),
4079 #ifdef SNDRV_BIG_ENDIAN
4080 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4081 #else
4082 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4083 #endif
4084 .rates = (SNDRV_PCM_RATE_32000 |
4085 SNDRV_PCM_RATE_44100 |
4086 SNDRV_PCM_RATE_48000 |
4087 SNDRV_PCM_RATE_64000 |
4088 SNDRV_PCM_RATE_88200 |
4089 SNDRV_PCM_RATE_96000),
4090 .rate_min = 32000,
4091 .rate_max = 96000,
4092 .channels_min = 14,
4093 .channels_max = HDSP_MAX_CHANNELS,
4094 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4095 .period_bytes_min = (64 * 4) * 10,
4096 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4097 .periods_min = 2,
4098 .periods_max = 2,
4099 .fifo_size = 0
4100 };
4101
4102 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4103 {
4104 .info = (SNDRV_PCM_INFO_MMAP |
4105 SNDRV_PCM_INFO_MMAP_VALID |
4106 SNDRV_PCM_INFO_NONINTERLEAVED |
4107 SNDRV_PCM_INFO_SYNC_START),
4108 #ifdef SNDRV_BIG_ENDIAN
4109 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4110 #else
4111 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4112 #endif
4113 .rates = (SNDRV_PCM_RATE_32000 |
4114 SNDRV_PCM_RATE_44100 |
4115 SNDRV_PCM_RATE_48000 |
4116 SNDRV_PCM_RATE_64000 |
4117 SNDRV_PCM_RATE_88200 |
4118 SNDRV_PCM_RATE_96000),
4119 .rate_min = 32000,
4120 .rate_max = 96000,
4121 .channels_min = 14,
4122 .channels_max = HDSP_MAX_CHANNELS,
4123 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4124 .period_bytes_min = (64 * 4) * 10,
4125 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4126 .periods_min = 2,
4127 .periods_max = 2,
4128 .fifo_size = 0
4129 };
4130
4131 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4132
4133 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4134 .count = ARRAY_SIZE(hdsp_period_sizes),
4135 .list = hdsp_period_sizes,
4136 .mask = 0
4137 };
4138
4139 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4140
4141 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4142 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4143 .list = hdsp_9632_sample_rates,
4144 .mask = 0
4145 };
4146
4147 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4148 struct snd_pcm_hw_rule *rule)
4149 {
4150 struct hdsp *hdsp = rule->private;
4151 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4152 if (hdsp->io_type == H9632) {
4153 unsigned int list[3];
4154 list[0] = hdsp->qs_in_channels;
4155 list[1] = hdsp->ds_in_channels;
4156 list[2] = hdsp->ss_in_channels;
4157 return snd_interval_list(c, 3, list, 0);
4158 } else {
4159 unsigned int list[2];
4160 list[0] = hdsp->ds_in_channels;
4161 list[1] = hdsp->ss_in_channels;
4162 return snd_interval_list(c, 2, list, 0);
4163 }
4164 }
4165
4166 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4167 struct snd_pcm_hw_rule *rule)
4168 {
4169 unsigned int list[3];
4170 struct hdsp *hdsp = rule->private;
4171 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4172 if (hdsp->io_type == H9632) {
4173 list[0] = hdsp->qs_out_channels;
4174 list[1] = hdsp->ds_out_channels;
4175 list[2] = hdsp->ss_out_channels;
4176 return snd_interval_list(c, 3, list, 0);
4177 } else {
4178 list[0] = hdsp->ds_out_channels;
4179 list[1] = hdsp->ss_out_channels;
4180 }
4181 return snd_interval_list(c, 2, list, 0);
4182 }
4183
4184 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4185 struct snd_pcm_hw_rule *rule)
4186 {
4187 struct hdsp *hdsp = rule->private;
4188 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4189 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4190 if (r->min > 96000 && hdsp->io_type == H9632) {
4191 struct snd_interval t = {
4192 .min = hdsp->qs_in_channels,
4193 .max = hdsp->qs_in_channels,
4194 .integer = 1,
4195 };
4196 return snd_interval_refine(c, &t);
4197 } else if (r->min > 48000 && r->max <= 96000) {
4198 struct snd_interval t = {
4199 .min = hdsp->ds_in_channels,
4200 .max = hdsp->ds_in_channels,
4201 .integer = 1,
4202 };
4203 return snd_interval_refine(c, &t);
4204 } else if (r->max < 64000) {
4205 struct snd_interval t = {
4206 .min = hdsp->ss_in_channels,
4207 .max = hdsp->ss_in_channels,
4208 .integer = 1,
4209 };
4210 return snd_interval_refine(c, &t);
4211 }
4212 return 0;
4213 }
4214
4215 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4216 struct snd_pcm_hw_rule *rule)
4217 {
4218 struct hdsp *hdsp = rule->private;
4219 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4220 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4221 if (r->min > 96000 && hdsp->io_type == H9632) {
4222 struct snd_interval t = {
4223 .min = hdsp->qs_out_channels,
4224 .max = hdsp->qs_out_channels,
4225 .integer = 1,
4226 };
4227 return snd_interval_refine(c, &t);
4228 } else if (r->min > 48000 && r->max <= 96000) {
4229 struct snd_interval t = {
4230 .min = hdsp->ds_out_channels,
4231 .max = hdsp->ds_out_channels,
4232 .integer = 1,
4233 };
4234 return snd_interval_refine(c, &t);
4235 } else if (r->max < 64000) {
4236 struct snd_interval t = {
4237 .min = hdsp->ss_out_channels,
4238 .max = hdsp->ss_out_channels,
4239 .integer = 1,
4240 };
4241 return snd_interval_refine(c, &t);
4242 }
4243 return 0;
4244 }
4245
4246 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4247 struct snd_pcm_hw_rule *rule)
4248 {
4249 struct hdsp *hdsp = rule->private;
4250 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4251 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4252 if (c->min >= hdsp->ss_out_channels) {
4253 struct snd_interval t = {
4254 .min = 32000,
4255 .max = 48000,
4256 .integer = 1,
4257 };
4258 return snd_interval_refine(r, &t);
4259 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4260 struct snd_interval t = {
4261 .min = 128000,
4262 .max = 192000,
4263 .integer = 1,
4264 };
4265 return snd_interval_refine(r, &t);
4266 } else if (c->max <= hdsp->ds_out_channels) {
4267 struct snd_interval t = {
4268 .min = 64000,
4269 .max = 96000,
4270 .integer = 1,
4271 };
4272 return snd_interval_refine(r, &t);
4273 }
4274 return 0;
4275 }
4276
4277 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4278 struct snd_pcm_hw_rule *rule)
4279 {
4280 struct hdsp *hdsp = rule->private;
4281 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4282 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4283 if (c->min >= hdsp->ss_in_channels) {
4284 struct snd_interval t = {
4285 .min = 32000,
4286 .max = 48000,
4287 .integer = 1,
4288 };
4289 return snd_interval_refine(r, &t);
4290 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4291 struct snd_interval t = {
4292 .min = 128000,
4293 .max = 192000,
4294 .integer = 1,
4295 };
4296 return snd_interval_refine(r, &t);
4297 } else if (c->max <= hdsp->ds_in_channels) {
4298 struct snd_interval t = {
4299 .min = 64000,
4300 .max = 96000,
4301 .integer = 1,
4302 };
4303 return snd_interval_refine(r, &t);
4304 }
4305 return 0;
4306 }
4307
4308 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4309 {
4310 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4311 struct snd_pcm_runtime *runtime = substream->runtime;
4312
4313 if (hdsp_check_for_iobox (hdsp))
4314 return -EIO;
4315
4316 if (hdsp_check_for_firmware(hdsp, 1))
4317 return -EIO;
4318
4319 spin_lock_irq(&hdsp->lock);
4320
4321 snd_pcm_set_sync(substream);
4322
4323 runtime->hw = snd_hdsp_playback_subinfo;
4324 runtime->dma_area = hdsp->playback_buffer;
4325 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4326
4327 hdsp->playback_pid = current->pid;
4328 hdsp->playback_substream = substream;
4329
4330 spin_unlock_irq(&hdsp->lock);
4331
4332 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4333 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4334 if (hdsp->clock_source_locked) {
4335 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4336 } else if (hdsp->io_type == H9632) {
4337 runtime->hw.rate_max = 192000;
4338 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4339 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4340 }
4341 if (hdsp->io_type == H9632) {
4342 runtime->hw.channels_min = hdsp->qs_out_channels;
4343 runtime->hw.channels_max = hdsp->ss_out_channels;
4344 }
4345
4346 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4347 snd_hdsp_hw_rule_out_channels, hdsp,
4348 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4349 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4350 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4351 SNDRV_PCM_HW_PARAM_RATE, -1);
4352 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4353 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4354 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4355
4356 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4357 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4358 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4359 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4360 return 0;
4361 }
4362
4363 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4364 {
4365 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4366
4367 spin_lock_irq(&hdsp->lock);
4368
4369 hdsp->playback_pid = -1;
4370 hdsp->playback_substream = NULL;
4371
4372 spin_unlock_irq(&hdsp->lock);
4373
4374 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4375 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4376 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4377 return 0;
4378 }
4379
4380
4381 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4382 {
4383 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4384 struct snd_pcm_runtime *runtime = substream->runtime;
4385
4386 if (hdsp_check_for_iobox (hdsp))
4387 return -EIO;
4388
4389 if (hdsp_check_for_firmware(hdsp, 1))
4390 return -EIO;
4391
4392 spin_lock_irq(&hdsp->lock);
4393
4394 snd_pcm_set_sync(substream);
4395
4396 runtime->hw = snd_hdsp_capture_subinfo;
4397 runtime->dma_area = hdsp->capture_buffer;
4398 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4399
4400 hdsp->capture_pid = current->pid;
4401 hdsp->capture_substream = substream;
4402
4403 spin_unlock_irq(&hdsp->lock);
4404
4405 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4406 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4407 if (hdsp->io_type == H9632) {
4408 runtime->hw.channels_min = hdsp->qs_in_channels;
4409 runtime->hw.channels_max = hdsp->ss_in_channels;
4410 runtime->hw.rate_max = 192000;
4411 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4412 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4413 }
4414 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4415 snd_hdsp_hw_rule_in_channels, hdsp,
4416 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4417 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4418 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4419 SNDRV_PCM_HW_PARAM_RATE, -1);
4420 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4421 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4422 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4423 return 0;
4424 }
4425
4426 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4427 {
4428 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4429
4430 spin_lock_irq(&hdsp->lock);
4431
4432 hdsp->capture_pid = -1;
4433 hdsp->capture_substream = NULL;
4434
4435 spin_unlock_irq(&hdsp->lock);
4436 return 0;
4437 }
4438
4439 /* helper functions for copying meter values */
4440 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4441 {
4442 u32 val = readl(src);
4443 return copy_to_user(dest, &val, 4);
4444 }
4445
4446 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4447 {
4448 u32 rms_low, rms_high;
4449 u64 rms;
4450 rms_low = readl(src_low);
4451 rms_high = readl(src_high);
4452 rms = ((u64)rms_high << 32) | rms_low;
4453 return copy_to_user(dest, &rms, 8);
4454 }
4455
4456 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4457 {
4458 u32 rms_low, rms_high;
4459 u64 rms;
4460 rms_low = readl(src_low) & 0xffffff00;
4461 rms_high = readl(src_high) & 0xffffff00;
4462 rms = ((u64)rms_high << 32) | rms_low;
4463 return copy_to_user(dest, &rms, 8);
4464 }
4465
4466 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4467 {
4468 int doublespeed = 0;
4469 int i, j, channels, ofs;
4470
4471 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4472 doublespeed = 1;
4473 channels = doublespeed ? 14 : 26;
4474 for (i = 0, j = 0; i < 26; ++i) {
4475 if (doublespeed && (i & 4))
4476 continue;
4477 ofs = HDSP_9652_peakBase - j * 4;
4478 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4479 return -EFAULT;
4480 ofs -= channels * 4;
4481 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4482 return -EFAULT;
4483 ofs -= channels * 4;
4484 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4485 return -EFAULT;
4486 ofs = HDSP_9652_rmsBase + j * 8;
4487 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4488 hdsp->iobase + ofs + 4))
4489 return -EFAULT;
4490 ofs += channels * 8;
4491 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4492 hdsp->iobase + ofs + 4))
4493 return -EFAULT;
4494 ofs += channels * 8;
4495 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4496 hdsp->iobase + ofs + 4))
4497 return -EFAULT;
4498 j++;
4499 }
4500 return 0;
4501 }
4502
4503 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4504 {
4505 int i, j;
4506 struct hdsp_9632_meters __iomem *m;
4507 int doublespeed = 0;
4508
4509 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4510 doublespeed = 1;
4511 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4512 for (i = 0, j = 0; i < 16; ++i, ++j) {
4513 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4514 return -EFAULT;
4515 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4516 return -EFAULT;
4517 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4518 return -EFAULT;
4519 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4520 &m->input_rms_high[j]))
4521 return -EFAULT;
4522 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4523 &m->playback_rms_high[j]))
4524 return -EFAULT;
4525 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4526 &m->output_rms_high[j]))
4527 return -EFAULT;
4528 if (doublespeed && i == 3) i += 4;
4529 }
4530 return 0;
4531 }
4532
4533 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4534 {
4535 int i;
4536
4537 for (i = 0; i < 26; i++) {
4538 if (copy_u32_le(&peak_rms->playback_peaks[i],
4539 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4540 return -EFAULT;
4541 if (copy_u32_le(&peak_rms->input_peaks[i],
4542 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4543 return -EFAULT;
4544 }
4545 for (i = 0; i < 28; i++) {
4546 if (copy_u32_le(&peak_rms->output_peaks[i],
4547 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4548 return -EFAULT;
4549 }
4550 for (i = 0; i < 26; ++i) {
4551 if (copy_u64_le(&peak_rms->playback_rms[i],
4552 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4553 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4554 return -EFAULT;
4555 if (copy_u64_le(&peak_rms->input_rms[i],
4556 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4557 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4558 return -EFAULT;
4559 }
4560 return 0;
4561 }
4562
4563 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4564 {
4565 struct hdsp *hdsp = (struct hdsp *)hw->private_data;
4566 void __user *argp = (void __user *)arg;
4567 int err;
4568
4569 switch (cmd) {
4570 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4571 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4572
4573 err = hdsp_check_for_iobox(hdsp);
4574 if (err < 0)
4575 return err;
4576
4577 err = hdsp_check_for_firmware(hdsp, 1);
4578 if (err < 0)
4579 return err;
4580
4581 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4582 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4583 return -EINVAL;
4584 }
4585
4586 switch (hdsp->io_type) {
4587 case H9652:
4588 return hdsp_9652_get_peak(hdsp, peak_rms);
4589 case H9632:
4590 return hdsp_9632_get_peak(hdsp, peak_rms);
4591 default:
4592 return hdsp_get_peak(hdsp, peak_rms);
4593 }
4594 }
4595 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4596 struct hdsp_config_info info;
4597 unsigned long flags;
4598 int i;
4599
4600 err = hdsp_check_for_iobox(hdsp);
4601 if (err < 0)
4602 return err;
4603
4604 err = hdsp_check_for_firmware(hdsp, 1);
4605 if (err < 0)
4606 return err;
4607
4608 spin_lock_irqsave(&hdsp->lock, flags);
4609 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4610 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4611 if (hdsp->io_type != H9632)
4612 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4613 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4614 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
4615 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4616 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4617 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4618 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4619 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4620 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4621 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4622 info.system_sample_rate = hdsp->system_sample_rate;
4623 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4624 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4625 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4626 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4627 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4628 if (hdsp->io_type == H9632) {
4629 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4630 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4631 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4632 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4633
4634 }
4635 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4636 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4637 spin_unlock_irqrestore(&hdsp->lock, flags);
4638 if (copy_to_user(argp, &info, sizeof(info)))
4639 return -EFAULT;
4640 break;
4641 }
4642 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4643 struct hdsp_9632_aeb h9632_aeb;
4644
4645 if (hdsp->io_type != H9632) return -EINVAL;
4646 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4647 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4648 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4649 return -EFAULT;
4650 break;
4651 }
4652 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4653 struct hdsp_version hdsp_version;
4654 int err;
4655
4656 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4657 if (hdsp->io_type == Undefined) {
4658 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4659 return err;
4660 }
4661 hdsp_version.io_type = hdsp->io_type;
4662 hdsp_version.firmware_rev = hdsp->firmware_rev;
4663 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4664 return -EFAULT;
4665 break;
4666 }
4667 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4668 struct hdsp_firmware __user *firmware;
4669 u32 __user *firmware_data;
4670 int err;
4671
4672 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4673 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4674 if (hdsp->io_type == Undefined) return -EINVAL;
4675
4676 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4677 return -EBUSY;
4678
4679 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
4680 firmware = (struct hdsp_firmware __user *)argp;
4681
4682 if (get_user(firmware_data, &firmware->firmware_data))
4683 return -EFAULT;
4684
4685 if (hdsp_check_for_iobox (hdsp))
4686 return -EIO;
4687
4688 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
4689 return -EFAULT;
4690
4691 hdsp->state |= HDSP_FirmwareCached;
4692
4693 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4694 return err;
4695
4696 if (!(hdsp->state & HDSP_InitializationComplete)) {
4697 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4698 return err;
4699
4700 snd_hdsp_initialize_channels(hdsp);
4701 snd_hdsp_initialize_midi_flush(hdsp);
4702
4703 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4704 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4705 return err;
4706 }
4707 }
4708 break;
4709 }
4710 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4711 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4712 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4713 return -EFAULT;
4714 break;
4715 }
4716 default:
4717 return -EINVAL;
4718 }
4719 return 0;
4720 }
4721
4722 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4723 .open = snd_hdsp_playback_open,
4724 .close = snd_hdsp_playback_release,
4725 .ioctl = snd_hdsp_ioctl,
4726 .hw_params = snd_hdsp_hw_params,
4727 .prepare = snd_hdsp_prepare,
4728 .trigger = snd_hdsp_trigger,
4729 .pointer = snd_hdsp_hw_pointer,
4730 .copy = snd_hdsp_playback_copy,
4731 .silence = snd_hdsp_hw_silence,
4732 };
4733
4734 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4735 .open = snd_hdsp_capture_open,
4736 .close = snd_hdsp_capture_release,
4737 .ioctl = snd_hdsp_ioctl,
4738 .hw_params = snd_hdsp_hw_params,
4739 .prepare = snd_hdsp_prepare,
4740 .trigger = snd_hdsp_trigger,
4741 .pointer = snd_hdsp_hw_pointer,
4742 .copy = snd_hdsp_capture_copy,
4743 };
4744
4745 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4746 {
4747 struct snd_hwdep *hw;
4748 int err;
4749
4750 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4751 return err;
4752
4753 hdsp->hwdep = hw;
4754 hw->private_data = hdsp;
4755 strcpy(hw->name, "HDSP hwdep interface");
4756
4757 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4758
4759 return 0;
4760 }
4761
4762 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4763 {
4764 struct snd_pcm *pcm;
4765 int err;
4766
4767 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4768 return err;
4769
4770 hdsp->pcm = pcm;
4771 pcm->private_data = hdsp;
4772 strcpy(pcm->name, hdsp->card_name);
4773
4774 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4775 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4776
4777 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4778
4779 return 0;
4780 }
4781
4782 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4783 {
4784 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4785 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4786 }
4787
4788 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4789 {
4790 int i;
4791
4792 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4793 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
4794 return -EIO;
4795 }
4796
4797 for (i = 0; i < hdsp->max_channels; ++i) {
4798 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4799 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4800 }
4801
4802 return 0;
4803 }
4804
4805 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4806 {
4807 int status, aebi_channels, aebo_channels;
4808
4809 switch (hdsp->io_type) {
4810 case Digiface:
4811 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4812 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4813 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4814 break;
4815
4816 case H9652:
4817 hdsp->card_name = "RME Hammerfall HDSP 9652";
4818 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4819 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4820 break;
4821
4822 case H9632:
4823 status = hdsp_read(hdsp, HDSP_statusRegister);
4824 /* HDSP_AEBx bits are low when AEB are connected */
4825 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4826 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4827 hdsp->card_name = "RME Hammerfall HDSP 9632";
4828 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4829 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4830 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4831 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4832 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4833 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4834 break;
4835
4836 case Multiface:
4837 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4838 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4839 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4840 break;
4841
4842 default:
4843 /* should never get here */
4844 break;
4845 }
4846 }
4847
4848 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
4849 {
4850 snd_hdsp_flush_midi_input (hdsp, 0);
4851 snd_hdsp_flush_midi_input (hdsp, 1);
4852 }
4853
4854 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
4855 {
4856 int err;
4857
4858 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4859 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
4860 return err;
4861 }
4862
4863
4864 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4865 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
4866 return err;
4867 }
4868
4869 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4870 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4871 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
4872 return err;
4873 }
4874 }
4875
4876 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4877 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
4878 return err;
4879 }
4880
4881 snd_hdsp_proc_init(hdsp);
4882
4883 hdsp->system_sample_rate = -1;
4884 hdsp->playback_pid = -1;
4885 hdsp->capture_pid = -1;
4886 hdsp->capture_substream = NULL;
4887 hdsp->playback_substream = NULL;
4888
4889 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4890 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
4891 return err;
4892 }
4893
4894 if (!(hdsp->state & HDSP_InitializationComplete)) {
4895 strcpy(card->shortname, "Hammerfall DSP");
4896 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4897 hdsp->port, hdsp->irq);
4898
4899 if ((err = snd_card_register(card)) < 0) {
4900 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
4901 return err;
4902 }
4903 hdsp->state |= HDSP_InitializationComplete;
4904 }
4905
4906 return 0;
4907 }
4908
4909 #ifdef HDSP_FW_LOADER
4910 /* load firmware via hotplug fw loader */
4911 static int hdsp_request_fw_loader(struct hdsp *hdsp)
4912 {
4913 const char *fwfile;
4914 const struct firmware *fw;
4915 int err;
4916
4917 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4918 return 0;
4919 if (hdsp->io_type == Undefined) {
4920 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4921 return err;
4922 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4923 return 0;
4924 }
4925
4926 /* caution: max length of firmware filename is 30! */
4927 switch (hdsp->io_type) {
4928 case Multiface:
4929 if (hdsp->firmware_rev == 0xa)
4930 fwfile = "multiface_firmware.bin";
4931 else
4932 fwfile = "multiface_firmware_rev11.bin";
4933 break;
4934 case Digiface:
4935 if (hdsp->firmware_rev == 0xa)
4936 fwfile = "digiface_firmware.bin";
4937 else
4938 fwfile = "digiface_firmware_rev11.bin";
4939 break;
4940 default:
4941 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4942 return -EINVAL;
4943 }
4944
4945 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4946 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4947 return -ENOENT;
4948 }
4949 if (fw->size < sizeof(hdsp->firmware_cache)) {
4950 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4951 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4952 release_firmware(fw);
4953 return -EINVAL;
4954 }
4955
4956 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4957
4958 release_firmware(fw);
4959
4960 hdsp->state |= HDSP_FirmwareCached;
4961
4962 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4963 return err;
4964
4965 if (!(hdsp->state & HDSP_InitializationComplete)) {
4966 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4967 return err;
4968
4969 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4970 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
4971 return err;
4972 }
4973 snd_hdsp_initialize_channels(hdsp);
4974 snd_hdsp_initialize_midi_flush(hdsp);
4975 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4976 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4977 return err;
4978 }
4979 }
4980 return 0;
4981 }
4982 #endif
4983
4984 static int __devinit snd_hdsp_create(struct snd_card *card,
4985 struct hdsp *hdsp)
4986 {
4987 struct pci_dev *pci = hdsp->pci;
4988 int err;
4989 int is_9652 = 0;
4990 int is_9632 = 0;
4991
4992 hdsp->irq = -1;
4993 hdsp->state = 0;
4994 hdsp->midi[0].rmidi = NULL;
4995 hdsp->midi[1].rmidi = NULL;
4996 hdsp->midi[0].input = NULL;
4997 hdsp->midi[1].input = NULL;
4998 hdsp->midi[0].output = NULL;
4999 hdsp->midi[1].output = NULL;
5000 hdsp->midi[0].pending = 0;
5001 hdsp->midi[1].pending = 0;
5002 spin_lock_init(&hdsp->midi[0].lock);
5003 spin_lock_init(&hdsp->midi[1].lock);
5004 hdsp->iobase = NULL;
5005 hdsp->control_register = 0;
5006 hdsp->control2_register = 0;
5007 hdsp->io_type = Undefined;
5008 hdsp->max_channels = 26;
5009
5010 hdsp->card = card;
5011
5012 spin_lock_init(&hdsp->lock);
5013
5014 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5015
5016 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5017 hdsp->firmware_rev &= 0xff;
5018
5019 /* From Martin Bjoernsen :
5020 "It is important that the card's latency timer register in
5021 the PCI configuration space is set to a value much larger
5022 than 0 by the computer's BIOS or the driver.
5023 The windows driver always sets this 8 bit register [...]
5024 to its maximum 255 to avoid problems with some computers."
5025 */
5026 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5027
5028 strcpy(card->driver, "H-DSP");
5029 strcpy(card->mixername, "Xilinx FPGA");
5030
5031 if (hdsp->firmware_rev < 0xa)
5032 return -ENODEV;
5033 else if (hdsp->firmware_rev < 0x64)
5034 hdsp->card_name = "RME Hammerfall DSP";
5035 else if (hdsp->firmware_rev < 0x96) {
5036 hdsp->card_name = "RME HDSP 9652";
5037 is_9652 = 1;
5038 } else {
5039 hdsp->card_name = "RME HDSP 9632";
5040 hdsp->max_channels = 16;
5041 is_9632 = 1;
5042 }
5043
5044 if ((err = pci_enable_device(pci)) < 0)
5045 return err;
5046
5047 pci_set_master(hdsp->pci);
5048
5049 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5050 return err;
5051 hdsp->port = pci_resource_start(pci, 0);
5052 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5053 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5054 return -EBUSY;
5055 }
5056
5057 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5058 "hdsp", hdsp)) {
5059 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5060 return -EBUSY;
5061 }
5062
5063 hdsp->irq = pci->irq;
5064 hdsp->precise_ptr = 0;
5065 hdsp->use_midi_tasklet = 1;
5066 hdsp->dds_value = 0;
5067
5068 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5069 return err;
5070
5071 if (!is_9652 && !is_9632) {
5072 /* we wait a maximum of 10 seconds to let freshly
5073 * inserted cardbus cards do their hardware init */
5074 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5075
5076 if (err < 0)
5077 return err;
5078
5079 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5080 #ifdef HDSP_FW_LOADER
5081 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5082 /* we don't fail as this can happen
5083 if userspace is not ready for
5084 firmware upload
5085 */
5086 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5087 else
5088 /* init is complete, we return */
5089 return 0;
5090 #endif
5091 /* we defer initialization */
5092 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5093 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5094 return err;
5095 return 0;
5096 } else {
5097 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5098 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5099 hdsp->io_type = Multiface;
5100 else
5101 hdsp->io_type = Digiface;
5102 }
5103 }
5104
5105 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5106 return err;
5107
5108 if (is_9652)
5109 hdsp->io_type = H9652;
5110
5111 if (is_9632)
5112 hdsp->io_type = H9632;
5113
5114 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5115 return err;
5116
5117 snd_hdsp_initialize_channels(hdsp);
5118 snd_hdsp_initialize_midi_flush(hdsp);
5119
5120 hdsp->state |= HDSP_FirmwareLoaded;
5121
5122 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5123 return err;
5124
5125 return 0;
5126 }
5127
5128 static int snd_hdsp_free(struct hdsp *hdsp)
5129 {
5130 if (hdsp->port) {
5131 /* stop the audio, and cancel all interrupts */
5132 tasklet_kill(&hdsp->midi_tasklet);
5133 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5134 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5135 }
5136
5137 if (hdsp->irq >= 0)
5138 free_irq(hdsp->irq, (void *)hdsp);
5139
5140 snd_hdsp_free_buffers(hdsp);
5141
5142 if (hdsp->iobase)
5143 iounmap(hdsp->iobase);
5144
5145 if (hdsp->port)
5146 pci_release_regions(hdsp->pci);
5147
5148 pci_disable_device(hdsp->pci);
5149 return 0;
5150 }
5151
5152 static void snd_hdsp_card_free(struct snd_card *card)
5153 {
5154 struct hdsp *hdsp = (struct hdsp *) card->private_data;
5155
5156 if (hdsp)
5157 snd_hdsp_free(hdsp);
5158 }
5159
5160 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5161 const struct pci_device_id *pci_id)
5162 {
5163 static int dev;
5164 struct hdsp *hdsp;
5165 struct snd_card *card;
5166 int err;
5167
5168 if (dev >= SNDRV_CARDS)
5169 return -ENODEV;
5170 if (!enable[dev]) {
5171 dev++;
5172 return -ENOENT;
5173 }
5174
5175 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
5176 sizeof(struct hdsp), &card);
5177 if (err < 0)
5178 return err;
5179
5180 hdsp = (struct hdsp *) card->private_data;
5181 card->private_free = snd_hdsp_card_free;
5182 hdsp->dev = dev;
5183 hdsp->pci = pci;
5184 snd_card_set_dev(card, &pci->dev);
5185
5186 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5187 snd_card_free(card);
5188 return err;
5189 }
5190
5191 strcpy(card->shortname, "Hammerfall DSP");
5192 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5193 hdsp->port, hdsp->irq);
5194
5195 if ((err = snd_card_register(card)) < 0) {
5196 snd_card_free(card);
5197 return err;
5198 }
5199 pci_set_drvdata(pci, card);
5200 dev++;
5201 return 0;
5202 }
5203
5204 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5205 {
5206 snd_card_free(pci_get_drvdata(pci));
5207 pci_set_drvdata(pci, NULL);
5208 }
5209
5210 static struct pci_driver driver = {
5211 .name = "RME Hammerfall DSP",
5212 .id_table = snd_hdsp_ids,
5213 .probe = snd_hdsp_probe,
5214 .remove = __devexit_p(snd_hdsp_remove),
5215 };
5216
5217 static int __init alsa_card_hdsp_init(void)
5218 {
5219 return pci_register_driver(&driver);
5220 }
5221
5222 static void __exit alsa_card_hdsp_exit(void)
5223 {
5224 pci_unregister_driver(&driver);
5225 }
5226
5227 module_init(alsa_card_hdsp_init)
5228 module_exit(alsa_card_hdsp_exit)
connection oriented routing - ARCHIVE NO UPDATES HERE