arch/arm/mach-ixp4xx/ixp4xx_npe.c

   1 /*
   2  * Intel IXP4xx Network Processor Engine driver for Linux
   3  *
   4  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * The code is based on publicly available information:
  11  * - Intel IXP4xx Developer's Manual and other e-papers
  12  * - Intel IXP400 Access Library Software (BSD license)
  13  * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
  14  *   Thanks, Christian.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/firmware.h>
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <mach/npe.h>
  25
  26 #define DEBUG_MSG                       0
  27 #define DEBUG_FW                        0
  28
  29 #define NPE_COUNT                       3
  30 #define MAX_RETRIES                     1000    /* microseconds */
  31 #define NPE_42X_DATA_SIZE               0x800   /* in dwords */
  32 #define NPE_46X_DATA_SIZE               0x1000
  33 #define NPE_A_42X_INSTR_SIZE            0x1000
  34 #define NPE_B_AND_C_42X_INSTR_SIZE      0x800
  35 #define NPE_46X_INSTR_SIZE              0x1000
  36 #define REGS_SIZE                       0x1000
  37
  38 #define NPE_PHYS_REG                    32
  39
  40 #define FW_MAGIC                        0xFEEDF00D
  41 #define FW_BLOCK_TYPE_INSTR             0x0
  42 #define FW_BLOCK_TYPE_DATA              0x1
  43 #define FW_BLOCK_TYPE_EOF               0xF
  44
  45 /* NPE exec status (read) and command (write) */
  46 #define CMD_NPE_STEP                    0x01
  47 #define CMD_NPE_START                   0x02
  48 #define CMD_NPE_STOP                    0x03
  49 #define CMD_NPE_CLR_PIPE                0x04
  50 #define CMD_CLR_PROFILE_CNT             0x0C
  51 #define CMD_RD_INS_MEM                  0x10 /* instruction memory */
  52 #define CMD_WR_INS_MEM                  0x11
  53 #define CMD_RD_DATA_MEM                 0x12 /* data memory */
  54 #define CMD_WR_DATA_MEM                 0x13
  55 #define CMD_RD_ECS_REG                  0x14 /* exec access register */
  56 #define CMD_WR_ECS_REG                  0x15
  57
  58 #define STAT_RUN                        0x80000000
  59 #define STAT_STOP                       0x40000000
  60 #define STAT_CLEAR                      0x20000000
  61 #define STAT_ECS_K                      0x00800000 /* pipeline clean */
  62
  63 #define NPE_STEVT                       0x1B
  64 #define NPE_STARTPC                     0x1C
  65 #define NPE_REGMAP                      0x1E
  66 #define NPE_CINDEX                      0x1F
  67
  68 #define INSTR_WR_REG_SHORT              0x0000C000
  69 #define INSTR_WR_REG_BYTE               0x00004000
  70 #define INSTR_RD_FIFO                   0x0F888220
  71 #define INSTR_RESET_MBOX                0x0FAC8210
  72
  73 #define ECS_BG_CTXT_REG_0               0x00 /* Background Executing Context */
  74 #define ECS_BG_CTXT_REG_1               0x01 /*         Stack level */
  75 #define ECS_BG_CTXT_REG_2               0x02
  76 #define ECS_PRI_1_CTXT_REG_0            0x04 /* Priority 1 Executing Context */
  77 #define ECS_PRI_1_CTXT_REG_1            0x05 /*         Stack level */
  78 #define ECS_PRI_1_CTXT_REG_2            0x06
  79 #define ECS_PRI_2_CTXT_REG_0            0x08 /* Priority 2 Executing Context */
  80 #define ECS_PRI_2_CTXT_REG_1            0x09 /*         Stack level */
  81 #define ECS_PRI_2_CTXT_REG_2            0x0A
  82 #define ECS_DBG_CTXT_REG_0              0x0C /* Debug Executing Context */
  83 #define ECS_DBG_CTXT_REG_1              0x0D /*         Stack level */
  84 #define ECS_DBG_CTXT_REG_2              0x0E
  85 #define ECS_INSTRUCT_REG                0x11 /* NPE Instruction Register */
  86
  87 #define ECS_REG_0_ACTIVE                0x80000000 /* all levels */
  88 #define ECS_REG_0_NEXTPC_MASK           0x1FFF0000 /* BG/PRI1/PRI2 levels */
  89 #define ECS_REG_0_LDUR_BITS             8
  90 #define ECS_REG_0_LDUR_MASK             0x00000700 /* all levels */
  91 #define ECS_REG_1_CCTXT_BITS            16
  92 #define ECS_REG_1_CCTXT_MASK            0x000F0000 /* all levels */
  93 #define ECS_REG_1_SELCTXT_BITS          0
  94 #define ECS_REG_1_SELCTXT_MASK          0x0000000F /* all levels */
  95 #define ECS_DBG_REG_2_IF                0x00100000 /* debug level */
  96 #define ECS_DBG_REG_2_IE                0x00080000 /* debug level */
  97
  98 /* NPE watchpoint_fifo register bit */
  99 #define WFIFO_VALID                     0x80000000
 100
 101 /* NPE messaging_status register bit definitions */
 102 #define MSGSTAT_OFNE    0x00010000 /* OutFifoNotEmpty */
 103 #define MSGSTAT_IFNF    0x00020000 /* InFifoNotFull */
 104 #define MSGSTAT_OFNF    0x00040000 /* OutFifoNotFull */
 105 #define MSGSTAT_IFNE    0x00080000 /* InFifoNotEmpty */
 106 #define MSGSTAT_MBINT   0x00100000 /* Mailbox interrupt */
 107 #define MSGSTAT_IFINT   0x00200000 /* InFifo interrupt */
 108 #define MSGSTAT_OFINT   0x00400000 /* OutFifo interrupt */
 109 #define MSGSTAT_WFINT   0x00800000 /* WatchFifo interrupt */
 110
 111 /* NPE messaging_control register bit definitions */
 112 #define MSGCTL_OUT_FIFO                 0x00010000 /* enable output FIFO */
 113 #define MSGCTL_IN_FIFO                  0x00020000 /* enable input FIFO */
 114 #define MSGCTL_OUT_FIFO_WRITE           0x01000000 /* enable FIFO + WRITE */
 115 #define MSGCTL_IN_FIFO_WRITE            0x02000000
 116
 117 /* NPE mailbox_status value for reset */
 118 #define RESET_MBOX_STAT                 0x0000F0F0
 119
 120 const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
 121
 122 #define print_npe(pri, npe, fmt, ...)                                   \
 123         printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
 124
 125 #if DEBUG_MSG
 126 #define debug_msg(npe, fmt, ...)                                        \
 127         print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
 128 #else
 129 #define debug_msg(npe, fmt, ...)
 130 #endif
 131
 132 static struct {
 133         u32 reg, val;
 134 } ecs_reset[] = {
 135         { ECS_BG_CTXT_REG_0,    0xA0000000 },
 136         { ECS_BG_CTXT_REG_1,    0x01000000 },
 137         { ECS_BG_CTXT_REG_2,    0x00008000 },
 138         { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
 139         { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
 140         { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
 141         { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
 142         { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
 143         { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
 144         { ECS_DBG_CTXT_REG_0,   0x20000000 },
 145         { ECS_DBG_CTXT_REG_1,   0x00000000 },
 146         { ECS_DBG_CTXT_REG_2,   0x001E0000 },
 147         { ECS_INSTRUCT_REG,     0x1003C00F },
 148 };
 149
 150 static struct npe npe_tab[NPE_COUNT] = {
 151         {
 152                 .id     = 0,
 153                 .regs   = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
 154                 .regs_phys = IXP4XX_NPEA_BASE_PHYS,
 155         }, {
 156                 .id     = 1,
 157                 .regs   = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
 158                 .regs_phys = IXP4XX_NPEB_BASE_PHYS,
 159         }, {
 160                 .id     = 2,
 161                 .regs   = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
 162                 .regs_phys = IXP4XX_NPEC_BASE_PHYS,
 163         }
 164 };
 165
 166 int npe_running(struct npe *npe)
 167 {
 168         return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
 169 }
 170
 171 static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
 172 {
 173         __raw_writel(data, &npe->regs->exec_data);
 174         __raw_writel(addr, &npe->regs->exec_addr);
 175         __raw_writel(cmd, &npe->regs->exec_status_cmd);
 176 }
 177
 178 static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
 179 {
 180         __raw_writel(addr, &npe->regs->exec_addr);
 181         __raw_writel(cmd, &npe->regs->exec_status_cmd);
 182         /* Iintroduce extra read cycles after issuing read command to NPE
 183            so that we read the register after the NPE has updated it.
 184            This is to overcome race condition between XScale and NPE */
 185         __raw_readl(&npe->regs->exec_data);
 186         __raw_readl(&npe->regs->exec_data);
 187         return __raw_readl(&npe->regs->exec_data);
 188 }
 189
 190 static void npe_clear_active(struct npe *npe, u32 reg)
 191 {
 192         u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
 193         npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
 194 }
 195
 196 static void npe_start(struct npe *npe)
 197 {
 198         /* ensure only Background Context Stack Level is active */
 199         npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
 200         npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
 201         npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
 202
 203         __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
 204         __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
 205 }
 206
 207 static void npe_stop(struct npe *npe)
 208 {
 209         __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
 210         __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
 211 }
 212
 213 static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
 214                                         u32 ldur)
 215 {
 216         u32 wc;
 217         int i;
 218
 219         /* set the Active bit, and the LDUR, in the debug level */
 220         npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
 221                       ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
 222
 223         /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
 224            the instruction, and set SELCTXT at ECS DEBUG Level to specify
 225            which context store to access.
 226            Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
 227         */
 228         npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
 229                       (ctx << ECS_REG_1_CCTXT_BITS) |
 230                       (ctx << ECS_REG_1_SELCTXT_BITS));
 231
 232         /* clear the pipeline */
 233         __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
 234
 235         /* load NPE instruction into the instruction register */
 236         npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
 237
 238         /* we need this value later to wait for completion of NPE execution
 239            step */
 240         wc = __raw_readl(&npe->regs->watch_count);
 241
 242         /* issue a Step One command via the Execution Control register */
 243         __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
 244
 245         /* Watch Count register increments when NPE completes an instruction */
 246         for (i = 0; i < MAX_RETRIES; i++) {
 247                 if (wc != __raw_readl(&npe->regs->watch_count))
 248                         return 0;
 249                 udelay(1);
 250         }
 251
 252         print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
 253         return -ETIMEDOUT;
 254 }
 255
 256 static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
 257                                                u8 val, u32 ctx)
 258 {
 259         /* here we build the NPE assembler instruction: mov8 d0, #0 */
 260         u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
 261                 addr << 9 |             /* base Operand */
 262                 (val & 0x1F) << 4 |     /* lower 5 bits to immediate data */
 263                 (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
 264         return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
 265 }
 266
 267 static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
 268                                                 u16 val, u32 ctx)
 269 {
 270         /* here we build the NPE assembler instruction: mov16 d0, #0 */
 271         u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
 272                 addr << 9 |             /* base Operand */
 273                 (val & 0x1F) << 4 |     /* lower 5 bits to immediate data */
 274                 (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
 275         return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
 276 }
 277
 278 static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
 279                                                 u32 val, u32 ctx)
 280 {
 281         /* write in 16 bit steps first the high and then the low value */
 282         if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
 283                 return -ETIMEDOUT;
 284         return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
 285 }
 286
 287 static int npe_reset(struct npe *npe)
 288 {
 289         u32 val, ctl, exec_count, ctx_reg2;
 290         int i;
 291
 292         ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
 293                 0x3F3FFFFF;
 294
 295         /* disable parity interrupt */
 296         __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
 297
 298         /* pre exec - debug instruction */
 299         /* turn off the halt bit by clearing Execution Count register. */
 300         exec_count = __raw_readl(&npe->regs->exec_count);
 301         __raw_writel(0, &npe->regs->exec_count);
 302         /* ensure that IF and IE are on (temporarily), so that we don't end up
 303            stepping forever */
 304         ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
 305         npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
 306                       ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
 307
 308         /* clear the FIFOs */
 309         while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
 310                 ;
 311         while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
 312                 /* read from the outFIFO until empty */
 313                 print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
 314                           __raw_readl(&npe->regs->in_out_fifo));
 315
 316         while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
 317                 /* step execution of the NPE intruction to read inFIFO using
 318                    the Debug Executing Context stack */
 319                 if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
 320                         return -ETIMEDOUT;
 321
 322         /* reset the mailbox reg from the XScale side */
 323         __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
 324         /* from NPE side */
 325         if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
 326                 return -ETIMEDOUT;
 327
 328         /* Reset the physical registers in the NPE register file */
 329         for (val = 0; val < NPE_PHYS_REG; val++) {
 330                 if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
 331                         return -ETIMEDOUT;
 332                 /* address is either 0 or 4 */
 333                 if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
 334                         return -ETIMEDOUT;
 335         }
 336
 337         /* Reset the context store = each context's Context Store registers */
 338
 339         /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
 340            for Background ECS, to set where NPE starts executing code */
 341         val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
 342         val &= ~ECS_REG_0_NEXTPC_MASK;
 343         val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
 344         npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
 345
 346         for (i = 0; i < 16; i++) {
 347                 if (i) {        /* Context 0 has no STEVT nor STARTPC */
 348                         /* STEVT = off, 0x80 */
 349                         if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
 350                                 return -ETIMEDOUT;
 351                         if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
 352                                 return -ETIMEDOUT;
 353                 }
 354                 /* REGMAP = d0->p0, d8->p2, d16->p4 */
 355                 if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
 356                         return -ETIMEDOUT;
 357                 if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
 358                         return -ETIMEDOUT;
 359         }
 360
 361         /* post exec */
 362         /* clear active bit in debug level */
 363         npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
 364         /* clear the pipeline */
 365         __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
 366         /* restore previous values */
 367         __raw_writel(exec_count, &npe->regs->exec_count);
 368         npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
 369
 370         /* write reset values to Execution Context Stack registers */
 371         for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
 372                 npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
 373                               ecs_reset[val].val);
 374
 375         /* clear the profile counter */
 376         __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
 377
 378         __raw_writel(0, &npe->regs->exec_count);
 379         __raw_writel(0, &npe->regs->action_points[0]);
 380         __raw_writel(0, &npe->regs->action_points[1]);
 381         __raw_writel(0, &npe->regs->action_points[2]);
 382         __raw_writel(0, &npe->regs->action_points[3]);
 383         __raw_writel(0, &npe->regs->watch_count);
 384
 385         val = ixp4xx_read_feature_bits();
 386         /* reset the NPE */
 387         ixp4xx_write_feature_bits(val &
 388                                   ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
 389         /* deassert reset */
 390         ixp4xx_write_feature_bits(val |
 391                                   (IXP4XX_FEATURE_RESET_NPEA << npe->id));
 392         for (i = 0; i < MAX_RETRIES; i++) {
 393                 if (ixp4xx_read_feature_bits() &
 394                     (IXP4XX_FEATURE_RESET_NPEA << npe->id))
 395                         break;  /* NPE is back alive */
 396                 udelay(1);
 397         }
 398         if (i == MAX_RETRIES)
 399                 return -ETIMEDOUT;
 400
 401         npe_stop(npe);
 402
 403         /* restore NPE configuration bus Control Register - parity settings */
 404         __raw_writel(ctl, &npe->regs->messaging_control);
 405         return 0;
 406 }
 407
 408
 409 int npe_send_message(struct npe *npe, const void *msg, const char *what)
 410 {
 411         const u32 *send = msg;
 412         int cycles = 0;
 413
 414         debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
 415                   what, send[0], send[1]);
 416
 417         if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
 418                 debug_msg(npe, "NPE input FIFO not empty\n");
 419                 return -EIO;
 420         }
 421
 422         __raw_writel(send[0], &npe->regs->in_out_fifo);
 423
 424         if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
 425                 debug_msg(npe, "NPE input FIFO full\n");
 426                 return -EIO;
 427         }
 428
 429         __raw_writel(send[1], &npe->regs->in_out_fifo);
 430
 431         while ((cycles < MAX_RETRIES) &&
 432                (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
 433                 udelay(1);
 434                 cycles++;
 435         }
 436
 437         if (cycles == MAX_RETRIES) {
 438                 debug_msg(npe, "Timeout sending message\n");
 439                 return -ETIMEDOUT;
 440         }
 441
 442 #if DEBUG_MSG > 1
 443         debug_msg(npe, "Sending a message took %i cycles\n", cycles);
 444 #endif
 445         return 0;
 446 }
 447
 448 int npe_recv_message(struct npe *npe, void *msg, const char *what)
 449 {
 450         u32 *recv = msg;
 451         int cycles = 0, cnt = 0;
 452
 453         debug_msg(npe, "Trying to receive message %s\n", what);
 454
 455         while (cycles < MAX_RETRIES) {
 456                 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
 457                         recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
 458                         if (cnt == 2)
 459                                 break;
 460                 } else {
 461                         udelay(1);
 462                         cycles++;
 463                 }
 464         }
 465
 466         switch(cnt) {
 467         case 1:
 468                 debug_msg(npe, "Received [%08X]\n", recv[0]);
 469                 break;
 470         case 2:
 471                 debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
 472                 break;
 473         }
 474
 475         if (cycles == MAX_RETRIES) {
 476                 debug_msg(npe, "Timeout waiting for message\n");
 477                 return -ETIMEDOUT;
 478         }
 479
 480 #if DEBUG_MSG > 1
 481         debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
 482 #endif
 483         return 0;
 484 }
 485
 486 int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
 487 {
 488         int result;
 489         u32 *send = msg, recv[2];
 490
 491         if ((result = npe_send_message(npe, msg, what)) != 0)
 492                 return result;
 493         if ((result = npe_recv_message(npe, recv, what)) != 0)
 494                 return result;
 495
 496         if ((recv[0] != send[0]) || (recv[1] != send[1])) {
 497                 debug_msg(npe, "Message %s: unexpected message received\n",
 498                           what);
 499                 return -EIO;
 500         }
 501         return 0;
 502 }
 503
 504
 505 int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
 506 {
 507         const struct firmware *fw_entry;
 508
 509         struct dl_block {
 510                 u32 type;
 511                 u32 offset;
 512         } *blk;
 513
 514         struct dl_image {
 515                 u32 magic;
 516                 u32 id;
 517                 u32 size;
 518                 union {
 519                         u32 data[0];
 520                         struct dl_block blocks[0];
 521                 };
 522         } *image;
 523
 524         struct dl_codeblock {
 525                 u32 npe_addr;
 526                 u32 size;
 527                 u32 data[0];
 528         } *cb;
 529
 530         int i, j, err, data_size, instr_size, blocks, table_end;
 531         u32 cmd;
 532
 533         if ((err = request_firmware(&fw_entry, name, dev)) != 0)
 534                 return err;
 535
 536         err = -EINVAL;
 537         if (fw_entry->size < sizeof(struct dl_image)) {
 538                 print_npe(KERN_ERR, npe, "incomplete firmware file\n");
 539                 goto err;
 540         }
 541         image = (struct dl_image*)fw_entry->data;
 542
 543 #if DEBUG_FW
 544         print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
 545                   image->magic, image->id, image->size, image->size * 4);
 546 #endif
 547
 548         if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
 549                 image->id = swab32(image->id);
 550                 image->size = swab32(image->size);
 551         } else if (image->magic != FW_MAGIC) {
 552                 print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
 553                           image->magic);
 554                 goto err;
 555         }
 556         if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
 557                 print_npe(KERN_ERR, npe,
 558                           "inconsistent size of firmware file\n");
 559                 goto err;
 560         }
 561         if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
 562                 print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
 563                 goto err;
 564         }
 565         if (image->magic == swab32(FW_MAGIC))
 566                 for (i = 0; i < image->size; i++)
 567                         image->data[i] = swab32(image->data[i]);
 568
 569         if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
 570                 print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
 571                           "IXP42x\n");
 572                 goto err;
 573         }
 574
 575         if (npe_running(npe)) {
 576                 print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
 577                           "already running\n");
 578                 err = -EBUSY;
 579                 goto err;
 580         }
 581 #if 0
 582         npe_stop(npe);
 583         npe_reset(npe);
 584 #endif
 585
 586         print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
 587                   "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
 588                   (image->id >> 8) & 0xFF, image->id & 0xFF);
 589
 590         if (cpu_is_ixp42x()) {
 591                 if (!npe->id)
 592                         instr_size = NPE_A_42X_INSTR_SIZE;
 593                 else
 594                         instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
 595                 data_size = NPE_42X_DATA_SIZE;
 596         } else {
 597                 instr_size = NPE_46X_INSTR_SIZE;
 598                 data_size = NPE_46X_DATA_SIZE;
 599         }
 600
 601         for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
 602              blocks++)
 603                 if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
 604                         break;
 605         if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
 606                 print_npe(KERN_INFO, npe, "firmware EOF block marker not "
 607                           "found\n");
 608                 goto err;
 609         }
 610
 611 #if DEBUG_FW
 612         print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
 613 #endif
 614
 615         table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
 616         for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
 617                 if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
 618                     || blk->offset < table_end) {
 619                         print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
 620                                   "firmware block #%i\n", blk->offset, i);
 621                         goto err;
 622                 }
 623
 624                 cb = (struct dl_codeblock*)&image->data[blk->offset];
 625                 if (blk->type == FW_BLOCK_TYPE_INSTR) {
 626                         if (cb->npe_addr + cb->size > instr_size)
 627                                 goto too_big;
 628                         cmd = CMD_WR_INS_MEM;
 629                 } else if (blk->type == FW_BLOCK_TYPE_DATA) {
 630                         if (cb->npe_addr + cb->size > data_size)
 631                                 goto too_big;
 632                         cmd = CMD_WR_DATA_MEM;
 633                 } else {
 634                         print_npe(KERN_INFO, npe, "invalid firmware block #%i "
 635                                   "type 0x%X\n", i, blk->type);
 636                         goto err;
 637                 }
 638                 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
 639                         print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
 640                                   "fit in firmware image: type %c, start 0x%X,"
 641                                   " length 0x%X\n", i,
 642                                   blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
 643                                   cb->npe_addr, cb->size);
 644                         goto err;
 645                 }
 646
 647                 for (j = 0; j < cb->size; j++)
 648                         npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
 649         }
 650
 651         npe_start(npe);
 652         if (!npe_running(npe))
 653                 print_npe(KERN_ERR, npe, "unable to start\n");
 654         release_firmware(fw_entry);
 655         return 0;
 656
 657 too_big:
 658         print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
 659                   "memory: type %c, start 0x%X, length 0x%X\n", i,
 660                   blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
 661                   cb->npe_addr, cb->size);
 662 err:
 663         release_firmware(fw_entry);
 664         return err;
 665 }
 666
 667
 668 struct npe *npe_request(int id)
 669 {
 670         if (id < NPE_COUNT)
 671                 if (npe_tab[id].valid)
 672                         if (try_module_get(THIS_MODULE))
 673                                 return &npe_tab[id];
 674         return NULL;
 675 }
 676
 677 void npe_release(struct npe *npe)
 678 {
 679         module_put(THIS_MODULE);
 680 }
 681
 682
 683 static int __init npe_init_module(void)
 684 {
 685
 686         int i, found = 0;
 687
 688         for (i = 0; i < NPE_COUNT; i++) {
 689                 struct npe *npe = &npe_tab[i];
 690                 if (!(ixp4xx_read_feature_bits() &
 691                       (IXP4XX_FEATURE_RESET_NPEA << i)))
 692                         continue; /* NPE already disabled or not present */
 693                 if (!(npe->mem_res = request_mem_region(npe->regs_phys,
 694                                                         REGS_SIZE,
 695                                                         npe_name(npe)))) {
 696                         print_npe(KERN_ERR, npe,
 697                                   "failed to request memory region\n");
 698                         continue;
 699                 }
 700
 701                 if (npe_reset(npe))
 702                         continue;
 703                 npe->valid = 1;
 704                 found++;
 705         }
 706
 707         if (!found)
 708                 return -ENODEV;
 709         return 0;
 710 }
 711
 712 static void __exit npe_cleanup_module(void)
 713 {
 714         int i;
 715
 716         for (i = 0; i < NPE_COUNT; i++)
 717                 if (npe_tab[i].mem_res) {
 718                         npe_reset(&npe_tab[i]);
 719                         release_resource(npe_tab[i].mem_res);
 720                 }
 721 }
 722
 723 module_init(npe_init_module);
 724 module_exit(npe_cleanup_module);
 725
 726 MODULE_AUTHOR("Krzysztof Halasa");
 727 MODULE_LICENSE("GPL v2");
 728
 729 EXPORT_SYMBOL(npe_names);
 730 EXPORT_SYMBOL(npe_running);
 731 EXPORT_SYMBOL(npe_request);
 732 EXPORT_SYMBOL(npe_release);
 733 EXPORT_SYMBOL(npe_load_firmware);
 734 EXPORT_SYMBOL(npe_send_message);
 735 EXPORT_SYMBOL(npe_recv_message);
 736 EXPORT_SYMBOL(npe_send_recv_message);