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[cor_2_6_31.git] / arch / blackfin / mach-bf561 / coreb.c
blob93635a766f9cded6c93e8cc011e47e35e62da0c1
1 /* Load firmware into Core B on a BF561
3 * Copyright 2004-2009 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
5 */
7 /* The Core B reset func requires code in the application that is loaded into
8 * Core B. In order to reset, the application needs to install an interrupt
9 * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
10 * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
11 * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
12 * 0xff600000 when COREB_SRAM_INIT is cleared.
15 #include <linux/device.h>
16 #include <linux/fs.h>
17 #include <linux/kernel.h>
18 #include <linux/miscdevice.h>
19 #include <linux/module.h>
21 #define CMD_COREB_START 2
22 #define CMD_COREB_STOP 3
23 #define CMD_COREB_RESET 4
25 static int
26 coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
28 int ret = 0;
30 switch (cmd) {
31 case CMD_COREB_START:
32 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
33 break;
34 case CMD_COREB_STOP:
35 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
37 break;
38 case CMD_COREB_RESET:
39 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
40 break;
41 default:
42 ret = -EINVAL;
43 break;
46 CSYNC();
48 return ret;
51 static struct file_operations coreb_fops = {
52 .owner = THIS_MODULE,
53 .ioctl = coreb_ioctl,
56 static struct miscdevice coreb_dev = {
57 .minor = MISC_DYNAMIC_MINOR,
58 .name = "coreb",
59 .fops = &coreb_fops,
62 static int __init bf561_coreb_init(void)
64 return misc_register(&coreb_dev);
66 module_init(bf561_coreb_init);
68 static void __exit bf561_coreb_exit(void)
70 misc_deregister(&coreb_dev);
72 module_exit(bf561_coreb_exit);
74 MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
75 MODULE_DESCRIPTION("BF561 Core B Support");