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warning removal
[cor_2_6_31.git] / arch / x86 / kernel / amd_iommu.c
blob6c99f5037801302fc60da447ce414a3179fad3eb
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
33
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
35
36 #define EXIT_LOOP_COUNT 10000000
37
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
39
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
43
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
46 #endif
47
48 /*
49 * general struct to manage commands send to an IOMMU
50 */
51 struct iommu_cmd {
52 u32 data[4];
53 };
54
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
63 unsigned int pages);
64
65 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
66 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
67 #endif
68
69 #ifdef CONFIG_AMD_IOMMU_STATS
70
71 /*
72 * Initialization code for statistics collection
73 */
74
75 DECLARE_STATS_COUNTER(compl_wait);
76 DECLARE_STATS_COUNTER(cnt_map_single);
77 DECLARE_STATS_COUNTER(cnt_unmap_single);
78 DECLARE_STATS_COUNTER(cnt_map_sg);
79 DECLARE_STATS_COUNTER(cnt_unmap_sg);
80 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
81 DECLARE_STATS_COUNTER(cnt_free_coherent);
82 DECLARE_STATS_COUNTER(cross_page);
83 DECLARE_STATS_COUNTER(domain_flush_single);
84 DECLARE_STATS_COUNTER(domain_flush_all);
85 DECLARE_STATS_COUNTER(alloced_io_mem);
86 DECLARE_STATS_COUNTER(total_map_requests);
87
88 static struct dentry *stats_dir;
89 static struct dentry *de_isolate;
90 static struct dentry *de_fflush;
91
92 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
93 {
94 if (stats_dir == NULL)
95 return;
96
97 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
98 &cnt->value);
99 }
100
101 static void amd_iommu_stats_init(void)
102 {
103 stats_dir = debugfs_create_dir("amd-iommu", NULL);
104 if (stats_dir == NULL)
105 return;
106
107 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
108 (u32 *)&amd_iommu_isolate);
109
110 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
111 (u32 *)&amd_iommu_unmap_flush);
112
113 amd_iommu_stats_add(&compl_wait);
114 amd_iommu_stats_add(&cnt_map_single);
115 amd_iommu_stats_add(&cnt_unmap_single);
116 amd_iommu_stats_add(&cnt_map_sg);
117 amd_iommu_stats_add(&cnt_unmap_sg);
118 amd_iommu_stats_add(&cnt_alloc_coherent);
119 amd_iommu_stats_add(&cnt_free_coherent);
120 amd_iommu_stats_add(&cross_page);
121 amd_iommu_stats_add(&domain_flush_single);
122 amd_iommu_stats_add(&domain_flush_all);
123 amd_iommu_stats_add(&alloced_io_mem);
124 amd_iommu_stats_add(&total_map_requests);
125 }
126
127 #endif
128
129 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
130 static int iommu_has_npcache(struct amd_iommu *iommu)
131 {
132 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
133 }
134
135 /****************************************************************************
136 *
137 * Interrupt handling functions
138 *
139 ****************************************************************************/
140
141 static void iommu_print_event(void *__evt)
142 {
143 u32 *event = __evt;
144 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
145 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
146 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
147 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
148 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
149
150 printk(KERN_ERR "AMD IOMMU: Event logged [");
151
152 switch (type) {
153 case EVENT_TYPE_ILL_DEV:
154 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
155 "address=0x%016llx flags=0x%04x]\n",
156 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
157 address, flags);
158 break;
159 case EVENT_TYPE_IO_FAULT:
160 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
161 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
162 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
163 domid, address, flags);
164 break;
165 case EVENT_TYPE_DEV_TAB_ERR:
166 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
167 "address=0x%016llx flags=0x%04x]\n",
168 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
169 address, flags);
170 break;
171 case EVENT_TYPE_PAGE_TAB_ERR:
172 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
173 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
174 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
175 domid, address, flags);
176 break;
177 case EVENT_TYPE_ILL_CMD:
178 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
179 break;
180 case EVENT_TYPE_CMD_HARD_ERR:
181 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
182 "flags=0x%04x]\n", address, flags);
183 break;
184 case EVENT_TYPE_IOTLB_INV_TO:
185 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
186 "address=0x%016llx]\n",
187 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
188 address);
189 break;
190 case EVENT_TYPE_INV_DEV_REQ:
191 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
192 "address=0x%016llx flags=0x%04x]\n",
193 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
194 address, flags);
195 break;
196 default:
197 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
198 }
199 }
200
201 static void iommu_poll_events(struct amd_iommu *iommu)
202 {
203 u32 head, tail;
204 unsigned long flags;
205
206 spin_lock_irqsave(&iommu->lock, flags);
207
208 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
209 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
210
211 while (head != tail) {
212 iommu_print_event(iommu->evt_buf + head);
213 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
214 }
215
216 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
217
218 spin_unlock_irqrestore(&iommu->lock, flags);
219 }
220
221 irqreturn_t amd_iommu_int_handler(int irq, void *data)
222 {
223 struct amd_iommu *iommu;
224
225 for_each_iommu(iommu)
226 iommu_poll_events(iommu);
227
228 return IRQ_HANDLED;
229 }
230
231 /****************************************************************************
232 *
233 * IOMMU command queuing functions
234 *
235 ****************************************************************************/
236
237 /*
238 * Writes the command to the IOMMUs command buffer and informs the
239 * hardware about the new command. Must be called with iommu->lock held.
240 */
241 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
242 {
243 u32 tail, head;
244 u8 *target;
245
246 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
247 target = iommu->cmd_buf + tail;
248 memcpy_toio(target, cmd, sizeof(*cmd));
249 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
250 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
251 if (tail == head)
252 return -ENOMEM;
253 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
254
255 return 0;
256 }
257
258 /*
259 * General queuing function for commands. Takes iommu->lock and calls
260 * __iommu_queue_command().
261 */
262 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
263 {
264 unsigned long flags;
265 int ret;
266
267 spin_lock_irqsave(&iommu->lock, flags);
268 ret = __iommu_queue_command(iommu, cmd);
269 if (!ret)
270 iommu->need_sync = true;
271 spin_unlock_irqrestore(&iommu->lock, flags);
272
273 return ret;
274 }
275
276 /*
277 * This function waits until an IOMMU has completed a completion
278 * wait command
279 */
280 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
281 {
282 int ready = 0;
283 unsigned status = 0;
284 unsigned long i = 0;
285
286 INC_STATS_COUNTER(compl_wait);
287
288 while (!ready && (i < EXIT_LOOP_COUNT)) {
289 ++i;
290 /* wait for the bit to become one */
291 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
292 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
293 }
294
295 /* set bit back to zero */
296 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
297 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
298
299 if (unlikely(i == EXIT_LOOP_COUNT))
300 panic("AMD IOMMU: Completion wait loop failed\n");
301 }
302
303 /*
304 * This function queues a completion wait command into the command
305 * buffer of an IOMMU
306 */
307 static int __iommu_completion_wait(struct amd_iommu *iommu)
308 {
309 struct iommu_cmd cmd;
310
311 memset(&cmd, 0, sizeof(cmd));
312 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
313 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
314
315 return __iommu_queue_command(iommu, &cmd);
316 }
317
318 /*
319 * This function is called whenever we need to ensure that the IOMMU has
320 * completed execution of all commands we sent. It sends a
321 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
322 * us about that by writing a value to a physical address we pass with
323 * the command.
324 */
325 static int iommu_completion_wait(struct amd_iommu *iommu)
326 {
327 int ret = 0;
328 unsigned long flags;
329
330 spin_lock_irqsave(&iommu->lock, flags);
331
332 if (!iommu->need_sync)
333 goto out;
334
335 ret = __iommu_completion_wait(iommu);
336
337 iommu->need_sync = false;
338
339 if (ret)
340 goto out;
341
342 __iommu_wait_for_completion(iommu);
343
344 out:
345 spin_unlock_irqrestore(&iommu->lock, flags);
346
347 return 0;
348 }
349
350 /*
351 * Command send function for invalidating a device table entry
352 */
353 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
354 {
355 struct iommu_cmd cmd;
356 int ret;
357
358 BUG_ON(iommu == NULL);
359
360 memset(&cmd, 0, sizeof(cmd));
361 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
362 cmd.data[0] = devid;
363
364 ret = iommu_queue_command(iommu, &cmd);
365
366 return ret;
367 }
368
369 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
370 u16 domid, int pde, int s)
371 {
372 memset(cmd, 0, sizeof(*cmd));
373 address &= PAGE_MASK;
374 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
375 cmd->data[1] |= domid;
376 cmd->data[2] = lower_32_bits(address);
377 cmd->data[3] = upper_32_bits(address);
378 if (s) /* size bit - we flush more than one 4kb page */
379 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
380 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
381 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
382 }
383
384 /*
385 * Generic command send function for invalidaing TLB entries
386 */
387 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
388 u64 address, u16 domid, int pde, int s)
389 {
390 struct iommu_cmd cmd;
391 int ret;
392
393 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
394
395 ret = iommu_queue_command(iommu, &cmd);
396
397 return ret;
398 }
399
400 /*
401 * TLB invalidation function which is called from the mapping functions.
402 * It invalidates a single PTE if the range to flush is within a single
403 * page. Otherwise it flushes the whole TLB of the IOMMU.
404 */
405 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
406 u64 address, size_t size)
407 {
408 int s = 0;
409 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
410
411 address &= PAGE_MASK;
412
413 if (pages > 1) {
414 /*
415 * If we have to flush more than one page, flush all
416 * TLB entries for this domain
417 */
418 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
419 s = 1;
420 }
421
422 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
423
424 return 0;
425 }
426
427 /* Flush the whole IO/TLB for a given protection domain */
428 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
429 {
430 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
431
432 INC_STATS_COUNTER(domain_flush_single);
433
434 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
435 }
436
437 /* Flush the whole IO/TLB for a given protection domain - including PDE */
438 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
439 {
440 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
441
442 INC_STATS_COUNTER(domain_flush_single);
443
444 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
445 }
446
447 /*
448 * This function is used to flush the IO/TLB for a given protection domain
449 * on every IOMMU in the system
450 */
451 static void iommu_flush_domain(u16 domid)
452 {
453 unsigned long flags;
454 struct amd_iommu *iommu;
455 struct iommu_cmd cmd;
456
457 INC_STATS_COUNTER(domain_flush_all);
458
459 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
460 domid, 1, 1);
461
462 for_each_iommu(iommu) {
463 spin_lock_irqsave(&iommu->lock, flags);
464 __iommu_queue_command(iommu, &cmd);
465 __iommu_completion_wait(iommu);
466 __iommu_wait_for_completion(iommu);
467 spin_unlock_irqrestore(&iommu->lock, flags);
468 }
469 }
470
471 void amd_iommu_flush_all_domains(void)
472 {
473 int i;
474
475 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
476 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
477 continue;
478 iommu_flush_domain(i);
479 }
480 }
481
482 void amd_iommu_flush_all_devices(void)
483 {
484 struct amd_iommu *iommu;
485 int i;
486
487 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
488 if (amd_iommu_pd_table[i] == NULL)
489 continue;
490
491 iommu = amd_iommu_rlookup_table[i];
492 if (!iommu)
493 continue;
494
495 iommu_queue_inv_dev_entry(iommu, i);
496 iommu_completion_wait(iommu);
497 }
498 }
499
500 /****************************************************************************
501 *
502 * The functions below are used the create the page table mappings for
503 * unity mapped regions.
504 *
505 ****************************************************************************/
506
507 /*
508 * Generic mapping functions. It maps a physical address into a DMA
509 * address space. It allocates the page table pages if necessary.
510 * In the future it can be extended to a generic mapping function
511 * supporting all features of AMD IOMMU page tables like level skipping
512 * and full 64 bit address spaces.
513 */
514 static int iommu_map_page(struct protection_domain *dom,
515 unsigned long bus_addr,
516 unsigned long phys_addr,
517 int prot)
518 {
519 u64 __pte, *pte;
520
521 bus_addr = PAGE_ALIGN(bus_addr);
522 phys_addr = PAGE_ALIGN(phys_addr);
523
524 /* only support 512GB address spaces for now */
525 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
526 return -EINVAL;
527
528 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
529
530 if (IOMMU_PTE_PRESENT(*pte))
531 return -EBUSY;
532
533 __pte = phys_addr | IOMMU_PTE_P;
534 if (prot & IOMMU_PROT_IR)
535 __pte |= IOMMU_PTE_IR;
536 if (prot & IOMMU_PROT_IW)
537 __pte |= IOMMU_PTE_IW;
538
539 *pte = __pte;
540
541 return 0;
542 }
543
544 static void iommu_unmap_page(struct protection_domain *dom,
545 unsigned long bus_addr)
546 {
547 u64 *pte;
548
549 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
550
551 if (!IOMMU_PTE_PRESENT(*pte))
552 return;
553
554 pte = IOMMU_PTE_PAGE(*pte);
555 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
556
557 if (!IOMMU_PTE_PRESENT(*pte))
558 return;
559
560 pte = IOMMU_PTE_PAGE(*pte);
561 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
562
563 *pte = 0;
564 }
565
566 /*
567 * This function checks if a specific unity mapping entry is needed for
568 * this specific IOMMU.
569 */
570 static int iommu_for_unity_map(struct amd_iommu *iommu,
571 struct unity_map_entry *entry)
572 {
573 u16 bdf, i;
574
575 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
576 bdf = amd_iommu_alias_table[i];
577 if (amd_iommu_rlookup_table[bdf] == iommu)
578 return 1;
579 }
580
581 return 0;
582 }
583
584 /*
585 * Init the unity mappings for a specific IOMMU in the system
586 *
587 * Basically iterates over all unity mapping entries and applies them to
588 * the default domain DMA of that IOMMU if necessary.
589 */
590 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
591 {
592 struct unity_map_entry *entry;
593 int ret;
594
595 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
596 if (!iommu_for_unity_map(iommu, entry))
597 continue;
598 ret = dma_ops_unity_map(iommu->default_dom, entry);
599 if (ret)
600 return ret;
601 }
602
603 return 0;
604 }
605
606 /*
607 * This function actually applies the mapping to the page table of the
608 * dma_ops domain.
609 */
610 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
611 struct unity_map_entry *e)
612 {
613 u64 addr;
614 int ret;
615
616 for (addr = e->address_start; addr < e->address_end;
617 addr += PAGE_SIZE) {
618 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
619 if (ret)
620 return ret;
621 /*
622 * if unity mapping is in aperture range mark the page
623 * as allocated in the aperture
624 */
625 if (addr < dma_dom->aperture_size)
626 __set_bit(addr >> PAGE_SHIFT,
627 dma_dom->aperture[0]->bitmap);
628 }
629
630 return 0;
631 }
632
633 /*
634 * Inits the unity mappings required for a specific device
635 */
636 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
637 u16 devid)
638 {
639 struct unity_map_entry *e;
640 int ret;
641
642 list_for_each_entry(e, &amd_iommu_unity_map, list) {
643 if (!(devid >= e->devid_start && devid <= e->devid_end))
644 continue;
645 ret = dma_ops_unity_map(dma_dom, e);
646 if (ret)
647 return ret;
648 }
649
650 return 0;
651 }
652
653 /****************************************************************************
654 *
655 * The next functions belong to the address allocator for the dma_ops
656 * interface functions. They work like the allocators in the other IOMMU
657 * drivers. Its basically a bitmap which marks the allocated pages in
658 * the aperture. Maybe it could be enhanced in the future to a more
659 * efficient allocator.
660 *
661 ****************************************************************************/
662
663 /*
664 * The address allocator core functions.
665 *
666 * called with domain->lock held
667 */
668
669 /*
670 * This function checks if there is a PTE for a given dma address. If
671 * there is one, it returns the pointer to it.
672 */
673 static u64* fetch_pte(struct protection_domain *domain,
674 unsigned long address)
675 {
676 u64 *pte;
677
678 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
679
680 if (!IOMMU_PTE_PRESENT(*pte))
681 return NULL;
682
683 pte = IOMMU_PTE_PAGE(*pte);
684 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
685
686 if (!IOMMU_PTE_PRESENT(*pte))
687 return NULL;
688
689 pte = IOMMU_PTE_PAGE(*pte);
690 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
691
692 return pte;
693 }
694
695 /*
696 * This function is used to add a new aperture range to an existing
697 * aperture in case of dma_ops domain allocation or address allocation
698 * failure.
699 */
700 static int alloc_new_range(struct amd_iommu *iommu,
701 struct dma_ops_domain *dma_dom,
702 bool populate, gfp_t gfp)
703 {
704 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
705 int i;
706
707 #ifdef CONFIG_IOMMU_STRESS
708 populate = false;
709 #endif
710
711 if (index >= APERTURE_MAX_RANGES)
712 return -ENOMEM;
713
714 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
715 if (!dma_dom->aperture[index])
716 return -ENOMEM;
717
718 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
719 if (!dma_dom->aperture[index]->bitmap)
720 goto out_free;
721
722 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
723
724 if (populate) {
725 unsigned long address = dma_dom->aperture_size;
726 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
727 u64 *pte, *pte_page;
728
729 for (i = 0; i < num_ptes; ++i) {
730 pte = alloc_pte(&dma_dom->domain, address,
731 &pte_page, gfp);
732 if (!pte)
733 goto out_free;
734
735 dma_dom->aperture[index]->pte_pages[i] = pte_page;
736
737 address += APERTURE_RANGE_SIZE / 64;
738 }
739 }
740
741 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
742
743 /* Intialize the exclusion range if necessary */
744 if (iommu->exclusion_start &&
745 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
746 iommu->exclusion_start < dma_dom->aperture_size) {
747 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
748 int pages = iommu_num_pages(iommu->exclusion_start,
749 iommu->exclusion_length,
750 PAGE_SIZE);
751 dma_ops_reserve_addresses(dma_dom, startpage, pages);
752 }
753
754 /*
755 * Check for areas already mapped as present in the new aperture
756 * range and mark those pages as reserved in the allocator. Such
757 * mappings may already exist as a result of requested unity
758 * mappings for devices.
759 */
760 for (i = dma_dom->aperture[index]->offset;
761 i < dma_dom->aperture_size;
762 i += PAGE_SIZE) {
763 u64 *pte = fetch_pte(&dma_dom->domain, i);
764 if (!pte || !IOMMU_PTE_PRESENT(*pte))
765 continue;
766
767 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
768 }
769
770 return 0;
771
772 out_free:
773 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
774
775 kfree(dma_dom->aperture[index]);
776 dma_dom->aperture[index] = NULL;
777
778 return -ENOMEM;
779 }
780
781 static unsigned long dma_ops_area_alloc(struct device *dev,
782 struct dma_ops_domain *dom,
783 unsigned int pages,
784 unsigned long align_mask,
785 u64 dma_mask,
786 unsigned long start)
787 {
788 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
789 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
790 int i = start >> APERTURE_RANGE_SHIFT;
791 unsigned long boundary_size;
792 unsigned long address = -1;
793 unsigned long limit;
794
795 next_bit >>= PAGE_SHIFT;
796
797 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
798 PAGE_SIZE) >> PAGE_SHIFT;
799
800 for (;i < max_index; ++i) {
801 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
802
803 if (dom->aperture[i]->offset >= dma_mask)
804 break;
805
806 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
807 dma_mask >> PAGE_SHIFT);
808
809 address = iommu_area_alloc(dom->aperture[i]->bitmap,
810 limit, next_bit, pages, 0,
811 boundary_size, align_mask);
812 if (address != -1) {
813 address = dom->aperture[i]->offset +
814 (address << PAGE_SHIFT);
815 dom->next_address = address + (pages << PAGE_SHIFT);
816 break;
817 }
818
819 next_bit = 0;
820 }
821
822 return address;
823 }
824
825 static unsigned long dma_ops_alloc_addresses(struct device *dev,
826 struct dma_ops_domain *dom,
827 unsigned int pages,
828 unsigned long align_mask,
829 u64 dma_mask)
830 {
831 unsigned long address;
832
833 #ifdef CONFIG_IOMMU_STRESS
834 dom->next_address = 0;
835 dom->need_flush = true;
836 #endif
837
838 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
839 dma_mask, dom->next_address);
840
841 if (address == -1) {
842 dom->next_address = 0;
843 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
844 dma_mask, 0);
845 dom->need_flush = true;
846 }
847
848 if (unlikely(address == -1))
849 address = bad_dma_address;
850
851 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
852
853 return address;
854 }
855
856 /*
857 * The address free function.
858 *
859 * called with domain->lock held
860 */
861 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
862 unsigned long address,
863 unsigned int pages)
864 {
865 unsigned i = address >> APERTURE_RANGE_SHIFT;
866 struct aperture_range *range = dom->aperture[i];
867
868 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
869
870 #ifdef CONFIG_IOMMU_STRESS
871 if (i < 4)
872 return;
873 #endif
874
875 if (address >= dom->next_address)
876 dom->need_flush = true;
877
878 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
879
880 iommu_area_free(range->bitmap, address, pages);
881
882 }
883
884 /****************************************************************************
885 *
886 * The next functions belong to the domain allocation. A domain is
887 * allocated for every IOMMU as the default domain. If device isolation
888 * is enabled, every device get its own domain. The most important thing
889 * about domains is the page table mapping the DMA address space they
890 * contain.
891 *
892 ****************************************************************************/
893
894 static u16 domain_id_alloc(void)
895 {
896 unsigned long flags;
897 int id;
898
899 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
900 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
901 BUG_ON(id == 0);
902 if (id > 0 && id < MAX_DOMAIN_ID)
903 __set_bit(id, amd_iommu_pd_alloc_bitmap);
904 else
905 id = 0;
906 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
907
908 return id;
909 }
910
911 static void domain_id_free(int id)
912 {
913 unsigned long flags;
914
915 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
916 if (id > 0 && id < MAX_DOMAIN_ID)
917 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
918 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
919 }
920
921 /*
922 * Used to reserve address ranges in the aperture (e.g. for exclusion
923 * ranges.
924 */
925 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
926 unsigned long start_page,
927 unsigned int pages)
928 {
929 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
930
931 if (start_page + pages > last_page)
932 pages = last_page - start_page;
933
934 for (i = start_page; i < start_page + pages; ++i) {
935 int index = i / APERTURE_RANGE_PAGES;
936 int page = i % APERTURE_RANGE_PAGES;
937 __set_bit(page, dom->aperture[index]->bitmap);
938 }
939 }
940
941 static void free_pagetable(struct protection_domain *domain)
942 {
943 int i, j;
944 u64 *p1, *p2, *p3;
945
946 p1 = domain->pt_root;
947
948 if (!p1)
949 return;
950
951 for (i = 0; i < 512; ++i) {
952 if (!IOMMU_PTE_PRESENT(p1[i]))
953 continue;
954
955 p2 = IOMMU_PTE_PAGE(p1[i]);
956 for (j = 0; j < 512; ++j) {
957 if (!IOMMU_PTE_PRESENT(p2[j]))
958 continue;
959 p3 = IOMMU_PTE_PAGE(p2[j]);
960 free_page((unsigned long)p3);
961 }
962
963 free_page((unsigned long)p2);
964 }
965
966 free_page((unsigned long)p1);
967
968 domain->pt_root = NULL;
969 }
970
971 /*
972 * Free a domain, only used if something went wrong in the
973 * allocation path and we need to free an already allocated page table
974 */
975 static void dma_ops_domain_free(struct dma_ops_domain *dom)
976 {
977 int i;
978
979 if (!dom)
980 return;
981
982 free_pagetable(&dom->domain);
983
984 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
985 if (!dom->aperture[i])
986 continue;
987 free_page((unsigned long)dom->aperture[i]->bitmap);
988 kfree(dom->aperture[i]);
989 }
990
991 kfree(dom);
992 }
993
994 /*
995 * Allocates a new protection domain usable for the dma_ops functions.
996 * It also intializes the page table and the address allocator data
997 * structures required for the dma_ops interface
998 */
999 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1000 {
1001 struct dma_ops_domain *dma_dom;
1002
1003 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1004 if (!dma_dom)
1005 return NULL;
1006
1007 spin_lock_init(&dma_dom->domain.lock);
1008
1009 dma_dom->domain.id = domain_id_alloc();
1010 if (dma_dom->domain.id == 0)
1011 goto free_dma_dom;
1012 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1013 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1014 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1015 dma_dom->domain.priv = dma_dom;
1016 if (!dma_dom->domain.pt_root)
1017 goto free_dma_dom;
1018
1019 dma_dom->need_flush = false;
1020 dma_dom->target_dev = 0xffff;
1021
1022 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1023 goto free_dma_dom;
1024
1025 /*
1026 * mark the first page as allocated so we never return 0 as
1027 * a valid dma-address. So we can use 0 as error value
1028 */
1029 dma_dom->aperture[0]->bitmap[0] = 1;
1030 dma_dom->next_address = 0;
1031
1032
1033 return dma_dom;
1034
1035 free_dma_dom:
1036 dma_ops_domain_free(dma_dom);
1037
1038 return NULL;
1039 }
1040
1041 /*
1042 * little helper function to check whether a given protection domain is a
1043 * dma_ops domain
1044 */
1045 static bool dma_ops_domain(struct protection_domain *domain)
1046 {
1047 return domain->flags & PD_DMA_OPS_MASK;
1048 }
1049
1050 /*
1051 * Find out the protection domain structure for a given PCI device. This
1052 * will give us the pointer to the page table root for example.
1053 */
1054 static struct protection_domain *domain_for_device(u16 devid)
1055 {
1056 struct protection_domain *dom;
1057 unsigned long flags;
1058
1059 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1060 dom = amd_iommu_pd_table[devid];
1061 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1062
1063 return dom;
1064 }
1065
1066 /*
1067 * If a device is not yet associated with a domain, this function does
1068 * assigns it visible for the hardware
1069 */
1070 static void attach_device(struct amd_iommu *iommu,
1071 struct protection_domain *domain,
1072 u16 devid)
1073 {
1074 unsigned long flags;
1075 u64 pte_root = virt_to_phys(domain->pt_root);
1076
1077 domain->dev_cnt += 1;
1078
1079 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1080 << DEV_ENTRY_MODE_SHIFT;
1081 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1082
1083 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1084 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1085 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1086 amd_iommu_dev_table[devid].data[2] = domain->id;
1087
1088 amd_iommu_pd_table[devid] = domain;
1089 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1090
1091 /*
1092 * We might boot into a crash-kernel here. The crashed kernel
1093 * left the caches in the IOMMU dirty. So we have to flush
1094 * here to evict all dirty stuff.
1095 */
1096 iommu_queue_inv_dev_entry(iommu, devid);
1097 iommu_flush_tlb_pde(iommu, domain->id);
1098 }
1099
1100 /*
1101 * Removes a device from a protection domain (unlocked)
1102 */
1103 static void __detach_device(struct protection_domain *domain, u16 devid)
1104 {
1105
1106 /* lock domain */
1107 spin_lock(&domain->lock);
1108
1109 /* remove domain from the lookup table */
1110 amd_iommu_pd_table[devid] = NULL;
1111
1112 /* remove entry from the device table seen by the hardware */
1113 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1114 amd_iommu_dev_table[devid].data[1] = 0;
1115 amd_iommu_dev_table[devid].data[2] = 0;
1116
1117 /* decrease reference counter */
1118 domain->dev_cnt -= 1;
1119
1120 /* ready */
1121 spin_unlock(&domain->lock);
1122 }
1123
1124 /*
1125 * Removes a device from a protection domain (with devtable_lock held)
1126 */
1127 static void detach_device(struct protection_domain *domain, u16 devid)
1128 {
1129 unsigned long flags;
1130
1131 /* lock device table */
1132 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1133 __detach_device(domain, devid);
1134 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1135 }
1136
1137 static int device_change_notifier(struct notifier_block *nb,
1138 unsigned long action, void *data)
1139 {
1140 struct device *dev = data;
1141 struct pci_dev *pdev = to_pci_dev(dev);
1142 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1143 struct protection_domain *domain;
1144 struct dma_ops_domain *dma_domain;
1145 struct amd_iommu *iommu;
1146 unsigned long flags;
1147
1148 if (devid > amd_iommu_last_bdf)
1149 goto out;
1150
1151 devid = amd_iommu_alias_table[devid];
1152
1153 iommu = amd_iommu_rlookup_table[devid];
1154 if (iommu == NULL)
1155 goto out;
1156
1157 domain = domain_for_device(devid);
1158
1159 if (domain && !dma_ops_domain(domain))
1160 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1161 "to a non-dma-ops domain\n", dev_name(dev));
1162
1163 switch (action) {
1164 case BUS_NOTIFY_UNBOUND_DRIVER:
1165 if (!domain)
1166 goto out;
1167 detach_device(domain, devid);
1168 break;
1169 case BUS_NOTIFY_ADD_DEVICE:
1170 /* allocate a protection domain if a device is added */
1171 dma_domain = find_protection_domain(devid);
1172 if (dma_domain)
1173 goto out;
1174 dma_domain = dma_ops_domain_alloc(iommu);
1175 if (!dma_domain)
1176 goto out;
1177 dma_domain->target_dev = devid;
1178
1179 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1180 list_add_tail(&dma_domain->list, &iommu_pd_list);
1181 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1182
1183 break;
1184 default:
1185 goto out;
1186 }
1187
1188 iommu_queue_inv_dev_entry(iommu, devid);
1189 iommu_completion_wait(iommu);
1190
1191 out:
1192 return 0;
1193 }
1194
1195 static struct notifier_block device_nb = {
1196 .notifier_call = device_change_notifier,
1197 };
1198
1199 /*****************************************************************************
1200 *
1201 * The next functions belong to the dma_ops mapping/unmapping code.
1202 *
1203 *****************************************************************************/
1204
1205 /*
1206 * This function checks if the driver got a valid device from the caller to
1207 * avoid dereferencing invalid pointers.
1208 */
1209 static bool check_device(struct device *dev)
1210 {
1211 if (!dev || !dev->dma_mask)
1212 return false;
1213
1214 return true;
1215 }
1216
1217 /*
1218 * In this function the list of preallocated protection domains is traversed to
1219 * find the domain for a specific device
1220 */
1221 static struct dma_ops_domain *find_protection_domain(u16 devid)
1222 {
1223 struct dma_ops_domain *entry, *ret = NULL;
1224 unsigned long flags;
1225
1226 if (list_empty(&iommu_pd_list))
1227 return NULL;
1228
1229 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1230
1231 list_for_each_entry(entry, &iommu_pd_list, list) {
1232 if (entry->target_dev == devid) {
1233 ret = entry;
1234 break;
1235 }
1236 }
1237
1238 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1239
1240 return ret;
1241 }
1242
1243 /*
1244 * In the dma_ops path we only have the struct device. This function
1245 * finds the corresponding IOMMU, the protection domain and the
1246 * requestor id for a given device.
1247 * If the device is not yet associated with a domain this is also done
1248 * in this function.
1249 */
1250 static int get_device_resources(struct device *dev,
1251 struct amd_iommu **iommu,
1252 struct protection_domain **domain,
1253 u16 *bdf)
1254 {
1255 struct dma_ops_domain *dma_dom;
1256 struct pci_dev *pcidev;
1257 u16 _bdf;
1258
1259 *iommu = NULL;
1260 *domain = NULL;
1261 *bdf = 0xffff;
1262
1263 if (dev->bus != &pci_bus_type)
1264 return 0;
1265
1266 pcidev = to_pci_dev(dev);
1267 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1268
1269 /* device not translated by any IOMMU in the system? */
1270 if (_bdf > amd_iommu_last_bdf)
1271 return 0;
1272
1273 *bdf = amd_iommu_alias_table[_bdf];
1274
1275 *iommu = amd_iommu_rlookup_table[*bdf];
1276 if (*iommu == NULL)
1277 return 0;
1278 *domain = domain_for_device(*bdf);
1279 if (*domain == NULL) {
1280 dma_dom = find_protection_domain(*bdf);
1281 if (!dma_dom)
1282 dma_dom = (*iommu)->default_dom;
1283 *domain = &dma_dom->domain;
1284 attach_device(*iommu, *domain, *bdf);
1285 DUMP_printk("Using protection domain %d for device %s\n",
1286 (*domain)->id, dev_name(dev));
1287 }
1288
1289 if (domain_for_device(_bdf) == NULL)
1290 attach_device(*iommu, *domain, _bdf);
1291
1292 return 1;
1293 }
1294
1295 /*
1296 * If the pte_page is not yet allocated this function is called
1297 */
1298 static u64* alloc_pte(struct protection_domain *dom,
1299 unsigned long address, u64 **pte_page, gfp_t gfp)
1300 {
1301 u64 *pte, *page;
1302
1303 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1304
1305 if (!IOMMU_PTE_PRESENT(*pte)) {
1306 page = (u64 *)get_zeroed_page(gfp);
1307 if (!page)
1308 return NULL;
1309 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1310 }
1311
1312 pte = IOMMU_PTE_PAGE(*pte);
1313 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1314
1315 if (!IOMMU_PTE_PRESENT(*pte)) {
1316 page = (u64 *)get_zeroed_page(gfp);
1317 if (!page)
1318 return NULL;
1319 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1320 }
1321
1322 pte = IOMMU_PTE_PAGE(*pte);
1323
1324 if (pte_page)
1325 *pte_page = pte;
1326
1327 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1328
1329 return pte;
1330 }
1331
1332 /*
1333 * This function fetches the PTE for a given address in the aperture
1334 */
1335 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1336 unsigned long address)
1337 {
1338 struct aperture_range *aperture;
1339 u64 *pte, *pte_page;
1340
1341 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1342 if (!aperture)
1343 return NULL;
1344
1345 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1346 if (!pte) {
1347 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1348 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1349 } else
1350 pte += IOMMU_PTE_L0_INDEX(address);
1351
1352 return pte;
1353 }
1354
1355 /*
1356 * This is the generic map function. It maps one 4kb page at paddr to
1357 * the given address in the DMA address space for the domain.
1358 */
1359 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1360 struct dma_ops_domain *dom,
1361 unsigned long address,
1362 phys_addr_t paddr,
1363 int direction)
1364 {
1365 u64 *pte, __pte;
1366
1367 WARN_ON(address > dom->aperture_size);
1368
1369 paddr &= PAGE_MASK;
1370
1371 pte = dma_ops_get_pte(dom, address);
1372 if (!pte)
1373 return bad_dma_address;
1374
1375 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1376
1377 if (direction == DMA_TO_DEVICE)
1378 __pte |= IOMMU_PTE_IR;
1379 else if (direction == DMA_FROM_DEVICE)
1380 __pte |= IOMMU_PTE_IW;
1381 else if (direction == DMA_BIDIRECTIONAL)
1382 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1383
1384 WARN_ON(*pte);
1385
1386 *pte = __pte;
1387
1388 return (dma_addr_t)address;
1389 }
1390
1391 /*
1392 * The generic unmapping function for on page in the DMA address space.
1393 */
1394 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1395 struct dma_ops_domain *dom,
1396 unsigned long address)
1397 {
1398 struct aperture_range *aperture;
1399 u64 *pte;
1400
1401 if (address >= dom->aperture_size)
1402 return;
1403
1404 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1405 if (!aperture)
1406 return;
1407
1408 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1409 if (!pte)
1410 return;
1411
1412 pte += IOMMU_PTE_L0_INDEX(address);
1413
1414 WARN_ON(!*pte);
1415
1416 *pte = 0ULL;
1417 }
1418
1419 /*
1420 * This function contains common code for mapping of a physically
1421 * contiguous memory region into DMA address space. It is used by all
1422 * mapping functions provided with this IOMMU driver.
1423 * Must be called with the domain lock held.
1424 */
1425 static dma_addr_t __map_single(struct device *dev,
1426 struct amd_iommu *iommu,
1427 struct dma_ops_domain *dma_dom,
1428 phys_addr_t paddr,
1429 size_t size,
1430 int dir,
1431 bool align,
1432 u64 dma_mask)
1433 {
1434 dma_addr_t offset = paddr & ~PAGE_MASK;
1435 dma_addr_t address, start, ret;
1436 unsigned int pages;
1437 unsigned long align_mask = 0;
1438 int i;
1439
1440 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1441 paddr &= PAGE_MASK;
1442
1443 INC_STATS_COUNTER(total_map_requests);
1444
1445 if (pages > 1)
1446 INC_STATS_COUNTER(cross_page);
1447
1448 if (align)
1449 align_mask = (1UL << get_order(size)) - 1;
1450
1451 retry:
1452 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1453 dma_mask);
1454 if (unlikely(address == bad_dma_address)) {
1455 /*
1456 * setting next_address here will let the address
1457 * allocator only scan the new allocated range in the
1458 * first run. This is a small optimization.
1459 */
1460 dma_dom->next_address = dma_dom->aperture_size;
1461
1462 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1463 goto out;
1464
1465 /*
1466 * aperture was sucessfully enlarged by 128 MB, try
1467 * allocation again
1468 */
1469 goto retry;
1470 }
1471
1472 start = address;
1473 for (i = 0; i < pages; ++i) {
1474 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1475 if (ret == bad_dma_address)
1476 goto out_unmap;
1477
1478 paddr += PAGE_SIZE;
1479 start += PAGE_SIZE;
1480 }
1481 address += offset;
1482
1483 ADD_STATS_COUNTER(alloced_io_mem, size);
1484
1485 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1486 iommu_flush_tlb(iommu, dma_dom->domain.id);
1487 dma_dom->need_flush = false;
1488 } else if (unlikely(iommu_has_npcache(iommu)))
1489 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1490
1491 out:
1492 return address;
1493
1494 out_unmap:
1495
1496 for (--i; i >= 0; --i) {
1497 start -= PAGE_SIZE;
1498 dma_ops_domain_unmap(iommu, dma_dom, start);
1499 }
1500
1501 dma_ops_free_addresses(dma_dom, address, pages);
1502
1503 return bad_dma_address;
1504 }
1505
1506 /*
1507 * Does the reverse of the __map_single function. Must be called with
1508 * the domain lock held too
1509 */
1510 static void __unmap_single(struct amd_iommu *iommu,
1511 struct dma_ops_domain *dma_dom,
1512 dma_addr_t dma_addr,
1513 size_t size,
1514 int dir)
1515 {
1516 dma_addr_t i, start;
1517 unsigned int pages;
1518
1519 if ((dma_addr == bad_dma_address) ||
1520 (dma_addr + size > dma_dom->aperture_size))
1521 return;
1522
1523 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1524 dma_addr &= PAGE_MASK;
1525 start = dma_addr;
1526
1527 for (i = 0; i < pages; ++i) {
1528 dma_ops_domain_unmap(iommu, dma_dom, start);
1529 start += PAGE_SIZE;
1530 }
1531
1532 SUB_STATS_COUNTER(alloced_io_mem, size);
1533
1534 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1535
1536 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1537 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1538 dma_dom->need_flush = false;
1539 }
1540 }
1541
1542 /*
1543 * The exported map_single function for dma_ops.
1544 */
1545 static dma_addr_t map_page(struct device *dev, struct page *page,
1546 unsigned long offset, size_t size,
1547 enum dma_data_direction dir,
1548 struct dma_attrs *attrs)
1549 {
1550 unsigned long flags;
1551 struct amd_iommu *iommu;
1552 struct protection_domain *domain;
1553 u16 devid;
1554 dma_addr_t addr;
1555 u64 dma_mask;
1556 phys_addr_t paddr = page_to_phys(page) + offset;
1557
1558 INC_STATS_COUNTER(cnt_map_single);
1559
1560 if (!check_device(dev))
1561 return bad_dma_address;
1562
1563 dma_mask = *dev->dma_mask;
1564
1565 get_device_resources(dev, &iommu, &domain, &devid);
1566
1567 if (iommu == NULL || domain == NULL)
1568 /* device not handled by any AMD IOMMU */
1569 return (dma_addr_t)paddr;
1570
1571 if (!dma_ops_domain(domain))
1572 return bad_dma_address;
1573
1574 spin_lock_irqsave(&domain->lock, flags);
1575 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1576 dma_mask);
1577 if (addr == bad_dma_address)
1578 goto out;
1579
1580 iommu_completion_wait(iommu);
1581
1582 out:
1583 spin_unlock_irqrestore(&domain->lock, flags);
1584
1585 return addr;
1586 }
1587
1588 /*
1589 * The exported unmap_single function for dma_ops.
1590 */
1591 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1592 enum dma_data_direction dir, struct dma_attrs *attrs)
1593 {
1594 unsigned long flags;
1595 struct amd_iommu *iommu;
1596 struct protection_domain *domain;
1597 u16 devid;
1598
1599 INC_STATS_COUNTER(cnt_unmap_single);
1600
1601 if (!check_device(dev) ||
1602 !get_device_resources(dev, &iommu, &domain, &devid))
1603 /* device not handled by any AMD IOMMU */
1604 return;
1605
1606 if (!dma_ops_domain(domain))
1607 return;
1608
1609 spin_lock_irqsave(&domain->lock, flags);
1610
1611 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1612
1613 iommu_completion_wait(iommu);
1614
1615 spin_unlock_irqrestore(&domain->lock, flags);
1616 }
1617
1618 /*
1619 * This is a special map_sg function which is used if we should map a
1620 * device which is not handled by an AMD IOMMU in the system.
1621 */
1622 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1623 int nelems, int dir)
1624 {
1625 struct scatterlist *s;
1626 int i;
1627
1628 for_each_sg(sglist, s, nelems, i) {
1629 s->dma_address = (dma_addr_t)sg_phys(s);
1630 s->dma_length = s->length;
1631 }
1632
1633 return nelems;
1634 }
1635
1636 /*
1637 * The exported map_sg function for dma_ops (handles scatter-gather
1638 * lists).
1639 */
1640 static int map_sg(struct device *dev, struct scatterlist *sglist,
1641 int nelems, enum dma_data_direction dir,
1642 struct dma_attrs *attrs)
1643 {
1644 unsigned long flags;
1645 struct amd_iommu *iommu;
1646 struct protection_domain *domain;
1647 u16 devid;
1648 int i;
1649 struct scatterlist *s;
1650 phys_addr_t paddr;
1651 int mapped_elems = 0;
1652 u64 dma_mask;
1653
1654 INC_STATS_COUNTER(cnt_map_sg);
1655
1656 if (!check_device(dev))
1657 return 0;
1658
1659 dma_mask = *dev->dma_mask;
1660
1661 get_device_resources(dev, &iommu, &domain, &devid);
1662
1663 if (!iommu || !domain)
1664 return map_sg_no_iommu(dev, sglist, nelems, dir);
1665
1666 if (!dma_ops_domain(domain))
1667 return 0;
1668
1669 spin_lock_irqsave(&domain->lock, flags);
1670
1671 for_each_sg(sglist, s, nelems, i) {
1672 paddr = sg_phys(s);
1673
1674 s->dma_address = __map_single(dev, iommu, domain->priv,
1675 paddr, s->length, dir, false,
1676 dma_mask);
1677
1678 if (s->dma_address) {
1679 s->dma_length = s->length;
1680 mapped_elems++;
1681 } else
1682 goto unmap;
1683 }
1684
1685 iommu_completion_wait(iommu);
1686
1687 out:
1688 spin_unlock_irqrestore(&domain->lock, flags);
1689
1690 return mapped_elems;
1691 unmap:
1692 for_each_sg(sglist, s, mapped_elems, i) {
1693 if (s->dma_address)
1694 __unmap_single(iommu, domain->priv, s->dma_address,
1695 s->dma_length, dir);
1696 s->dma_address = s->dma_length = 0;
1697 }
1698
1699 mapped_elems = 0;
1700
1701 goto out;
1702 }
1703
1704 /*
1705 * The exported map_sg function for dma_ops (handles scatter-gather
1706 * lists).
1707 */
1708 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1709 int nelems, enum dma_data_direction dir,
1710 struct dma_attrs *attrs)
1711 {
1712 unsigned long flags;
1713 struct amd_iommu *iommu;
1714 struct protection_domain *domain;
1715 struct scatterlist *s;
1716 u16 devid;
1717 int i;
1718
1719 INC_STATS_COUNTER(cnt_unmap_sg);
1720
1721 if (!check_device(dev) ||
1722 !get_device_resources(dev, &iommu, &domain, &devid))
1723 return;
1724
1725 if (!dma_ops_domain(domain))
1726 return;
1727
1728 spin_lock_irqsave(&domain->lock, flags);
1729
1730 for_each_sg(sglist, s, nelems, i) {
1731 __unmap_single(iommu, domain->priv, s->dma_address,
1732 s->dma_length, dir);
1733 s->dma_address = s->dma_length = 0;
1734 }
1735
1736 iommu_completion_wait(iommu);
1737
1738 spin_unlock_irqrestore(&domain->lock, flags);
1739 }
1740
1741 /*
1742 * The exported alloc_coherent function for dma_ops.
1743 */
1744 static void *alloc_coherent(struct device *dev, size_t size,
1745 dma_addr_t *dma_addr, gfp_t flag)
1746 {
1747 unsigned long flags;
1748 void *virt_addr;
1749 struct amd_iommu *iommu;
1750 struct protection_domain *domain;
1751 u16 devid;
1752 phys_addr_t paddr;
1753 u64 dma_mask = dev->coherent_dma_mask;
1754
1755 INC_STATS_COUNTER(cnt_alloc_coherent);
1756
1757 if (!check_device(dev))
1758 return NULL;
1759
1760 if (!get_device_resources(dev, &iommu, &domain, &devid))
1761 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1762
1763 flag |= __GFP_ZERO;
1764 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1765 if (!virt_addr)
1766 return NULL;
1767
1768 paddr = virt_to_phys(virt_addr);
1769
1770 if (!iommu || !domain) {
1771 *dma_addr = (dma_addr_t)paddr;
1772 return virt_addr;
1773 }
1774
1775 if (!dma_ops_domain(domain))
1776 goto out_free;
1777
1778 if (!dma_mask)
1779 dma_mask = *dev->dma_mask;
1780
1781 spin_lock_irqsave(&domain->lock, flags);
1782
1783 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1784 size, DMA_BIDIRECTIONAL, true, dma_mask);
1785
1786 if (*dma_addr == bad_dma_address) {
1787 spin_unlock_irqrestore(&domain->lock, flags);
1788 goto out_free;
1789 }
1790
1791 iommu_completion_wait(iommu);
1792
1793 spin_unlock_irqrestore(&domain->lock, flags);
1794
1795 return virt_addr;
1796
1797 out_free:
1798
1799 free_pages((unsigned long)virt_addr, get_order(size));
1800
1801 return NULL;
1802 }
1803
1804 /*
1805 * The exported free_coherent function for dma_ops.
1806 */
1807 static void free_coherent(struct device *dev, size_t size,
1808 void *virt_addr, dma_addr_t dma_addr)
1809 {
1810 unsigned long flags;
1811 struct amd_iommu *iommu;
1812 struct protection_domain *domain;
1813 u16 devid;
1814
1815 INC_STATS_COUNTER(cnt_free_coherent);
1816
1817 if (!check_device(dev))
1818 return;
1819
1820 get_device_resources(dev, &iommu, &domain, &devid);
1821
1822 if (!iommu || !domain)
1823 goto free_mem;
1824
1825 if (!dma_ops_domain(domain))
1826 goto free_mem;
1827
1828 spin_lock_irqsave(&domain->lock, flags);
1829
1830 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1831
1832 iommu_completion_wait(iommu);
1833
1834 spin_unlock_irqrestore(&domain->lock, flags);
1835
1836 free_mem:
1837 free_pages((unsigned long)virt_addr, get_order(size));
1838 }
1839
1840 /*
1841 * This function is called by the DMA layer to find out if we can handle a
1842 * particular device. It is part of the dma_ops.
1843 */
1844 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1845 {
1846 u16 bdf;
1847 struct pci_dev *pcidev;
1848
1849 /* No device or no PCI device */
1850 if (!dev || dev->bus != &pci_bus_type)
1851 return 0;
1852
1853 pcidev = to_pci_dev(dev);
1854
1855 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1856
1857 /* Out of our scope? */
1858 if (bdf > amd_iommu_last_bdf)
1859 return 0;
1860
1861 return 1;
1862 }
1863
1864 /*
1865 * The function for pre-allocating protection domains.
1866 *
1867 * If the driver core informs the DMA layer if a driver grabs a device
1868 * we don't need to preallocate the protection domains anymore.
1869 * For now we have to.
1870 */
1871 static void prealloc_protection_domains(void)
1872 {
1873 struct pci_dev *dev = NULL;
1874 struct dma_ops_domain *dma_dom;
1875 struct amd_iommu *iommu;
1876 u16 devid;
1877
1878 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1879 devid = calc_devid(dev->bus->number, dev->devfn);
1880 if (devid > amd_iommu_last_bdf)
1881 continue;
1882 devid = amd_iommu_alias_table[devid];
1883 if (domain_for_device(devid))
1884 continue;
1885 iommu = amd_iommu_rlookup_table[devid];
1886 if (!iommu)
1887 continue;
1888 dma_dom = dma_ops_domain_alloc(iommu);
1889 if (!dma_dom)
1890 continue;
1891 init_unity_mappings_for_device(dma_dom, devid);
1892 dma_dom->target_dev = devid;
1893
1894 list_add_tail(&dma_dom->list, &iommu_pd_list);
1895 }
1896 }
1897
1898 static struct dma_map_ops amd_iommu_dma_ops = {
1899 .alloc_coherent = alloc_coherent,
1900 .free_coherent = free_coherent,
1901 .map_page = map_page,
1902 .unmap_page = unmap_page,
1903 .map_sg = map_sg,
1904 .unmap_sg = unmap_sg,
1905 .dma_supported = amd_iommu_dma_supported,
1906 };
1907
1908 /*
1909 * The function which clues the AMD IOMMU driver into dma_ops.
1910 */
1911 int __init amd_iommu_init_dma_ops(void)
1912 {
1913 struct amd_iommu *iommu;
1914 int ret;
1915
1916 /*
1917 * first allocate a default protection domain for every IOMMU we
1918 * found in the system. Devices not assigned to any other
1919 * protection domain will be assigned to the default one.
1920 */
1921 for_each_iommu(iommu) {
1922 iommu->default_dom = dma_ops_domain_alloc(iommu);
1923 if (iommu->default_dom == NULL)
1924 return -ENOMEM;
1925 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1926 ret = iommu_init_unity_mappings(iommu);
1927 if (ret)
1928 goto free_domains;
1929 }
1930
1931 /*
1932 * If device isolation is enabled, pre-allocate the protection
1933 * domains for each device.
1934 */
1935 if (amd_iommu_isolate)
1936 prealloc_protection_domains();
1937
1938 iommu_detected = 1;
1939 force_iommu = 1;
1940 bad_dma_address = 0;
1941 #ifdef CONFIG_GART_IOMMU
1942 gart_iommu_aperture_disabled = 1;
1943 gart_iommu_aperture = 0;
1944 #endif
1945
1946 /* Make the driver finally visible to the drivers */
1947 dma_ops = &amd_iommu_dma_ops;
1948
1949 register_iommu(&amd_iommu_ops);
1950
1951 bus_register_notifier(&pci_bus_type, &device_nb);
1952
1953 amd_iommu_stats_init();
1954
1955 return 0;
1956
1957 free_domains:
1958
1959 for_each_iommu(iommu) {
1960 if (iommu->default_dom)
1961 dma_ops_domain_free(iommu->default_dom);
1962 }
1963
1964 return ret;
1965 }
1966
1967 /*****************************************************************************
1968 *
1969 * The following functions belong to the exported interface of AMD IOMMU
1970 *
1971 * This interface allows access to lower level functions of the IOMMU
1972 * like protection domain handling and assignement of devices to domains
1973 * which is not possible with the dma_ops interface.
1974 *
1975 *****************************************************************************/
1976
1977 static void cleanup_domain(struct protection_domain *domain)
1978 {
1979 unsigned long flags;
1980 u16 devid;
1981
1982 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1983
1984 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1985 if (amd_iommu_pd_table[devid] == domain)
1986 __detach_device(domain, devid);
1987
1988 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1989 }
1990
1991 static int amd_iommu_domain_init(struct iommu_domain *dom)
1992 {
1993 struct protection_domain *domain;
1994
1995 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1996 if (!domain)
1997 return -ENOMEM;
1998
1999 spin_lock_init(&domain->lock);
2000 domain->mode = PAGE_MODE_3_LEVEL;
2001 domain->id = domain_id_alloc();
2002 if (!domain->id)
2003 goto out_free;
2004 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2005 if (!domain->pt_root)
2006 goto out_free;
2007
2008 dom->priv = domain;
2009
2010 return 0;
2011
2012 out_free:
2013 kfree(domain);
2014
2015 return -ENOMEM;
2016 }
2017
2018 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2019 {
2020 struct protection_domain *domain = dom->priv;
2021
2022 if (!domain)
2023 return;
2024
2025 if (domain->dev_cnt > 0)
2026 cleanup_domain(domain);
2027
2028 BUG_ON(domain->dev_cnt != 0);
2029
2030 free_pagetable(domain);
2031
2032 domain_id_free(domain->id);
2033
2034 kfree(domain);
2035
2036 dom->priv = NULL;
2037 }
2038
2039 static void amd_iommu_detach_device(struct iommu_domain *dom,
2040 struct device *dev)
2041 {
2042 struct protection_domain *domain = dom->priv;
2043 struct amd_iommu *iommu;
2044 struct pci_dev *pdev;
2045 u16 devid;
2046
2047 if (dev->bus != &pci_bus_type)
2048 return;
2049
2050 pdev = to_pci_dev(dev);
2051
2052 devid = calc_devid(pdev->bus->number, pdev->devfn);
2053
2054 if (devid > 0)
2055 detach_device(domain, devid);
2056
2057 iommu = amd_iommu_rlookup_table[devid];
2058 if (!iommu)
2059 return;
2060
2061 iommu_queue_inv_dev_entry(iommu, devid);
2062 iommu_completion_wait(iommu);
2063 }
2064
2065 static int amd_iommu_attach_device(struct iommu_domain *dom,
2066 struct device *dev)
2067 {
2068 struct protection_domain *domain = dom->priv;
2069 struct protection_domain *old_domain;
2070 struct amd_iommu *iommu;
2071 struct pci_dev *pdev;
2072 u16 devid;
2073
2074 if (dev->bus != &pci_bus_type)
2075 return -EINVAL;
2076
2077 pdev = to_pci_dev(dev);
2078
2079 devid = calc_devid(pdev->bus->number, pdev->devfn);
2080
2081 if (devid >= amd_iommu_last_bdf ||
2082 devid != amd_iommu_alias_table[devid])
2083 return -EINVAL;
2084
2085 iommu = amd_iommu_rlookup_table[devid];
2086 if (!iommu)
2087 return -EINVAL;
2088
2089 old_domain = domain_for_device(devid);
2090 if (old_domain)
2091 detach_device(old_domain, devid);
2092
2093 attach_device(iommu, domain, devid);
2094
2095 iommu_completion_wait(iommu);
2096
2097 return 0;
2098 }
2099
2100 static int amd_iommu_map_range(struct iommu_domain *dom,
2101 unsigned long iova, phys_addr_t paddr,
2102 size_t size, int iommu_prot)
2103 {
2104 struct protection_domain *domain = dom->priv;
2105 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2106 int prot = 0;
2107 int ret;
2108
2109 if (iommu_prot & IOMMU_READ)
2110 prot |= IOMMU_PROT_IR;
2111 if (iommu_prot & IOMMU_WRITE)
2112 prot |= IOMMU_PROT_IW;
2113
2114 iova &= PAGE_MASK;
2115 paddr &= PAGE_MASK;
2116
2117 for (i = 0; i < npages; ++i) {
2118 ret = iommu_map_page(domain, iova, paddr, prot);
2119 if (ret)
2120 return ret;
2121
2122 iova += PAGE_SIZE;
2123 paddr += PAGE_SIZE;
2124 }
2125
2126 return 0;
2127 }
2128
2129 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2130 unsigned long iova, size_t size)
2131 {
2132
2133 struct protection_domain *domain = dom->priv;
2134 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2135
2136 iova &= PAGE_MASK;
2137
2138 for (i = 0; i < npages; ++i) {
2139 iommu_unmap_page(domain, iova);
2140 iova += PAGE_SIZE;
2141 }
2142
2143 iommu_flush_domain(domain->id);
2144 }
2145
2146 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2147 unsigned long iova)
2148 {
2149 struct protection_domain *domain = dom->priv;
2150 unsigned long offset = iova & ~PAGE_MASK;
2151 phys_addr_t paddr;
2152 u64 *pte;
2153
2154 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2155
2156 if (!IOMMU_PTE_PRESENT(*pte))
2157 return 0;
2158
2159 pte = IOMMU_PTE_PAGE(*pte);
2160 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2161
2162 if (!IOMMU_PTE_PRESENT(*pte))
2163 return 0;
2164
2165 pte = IOMMU_PTE_PAGE(*pte);
2166 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2167
2168 if (!IOMMU_PTE_PRESENT(*pte))
2169 return 0;
2170
2171 paddr = *pte & IOMMU_PAGE_MASK;
2172 paddr |= offset;
2173
2174 return paddr;
2175 }
2176
2177 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2178 unsigned long cap)
2179 {
2180 return 0;
2181 }
2182
2183 static struct iommu_ops amd_iommu_ops = {
2184 .domain_init = amd_iommu_domain_init,
2185 .domain_destroy = amd_iommu_domain_destroy,
2186 .attach_dev = amd_iommu_attach_device,
2187 .detach_dev = amd_iommu_detach_device,
2188 .map = amd_iommu_map_range,
2189 .unmap = amd_iommu_unmap_range,
2190 .iova_to_phys = amd_iommu_iova_to_phys,
2191 .domain_has_cap = amd_iommu_domain_has_cap,
2192 };
2193
connection oriented routing - ARCHIVE NO UPDATES HERE