src/soc/amd/cezanne/fsp_s_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <amdblocks/apob_cache.h>
   5 #include <device/pci.h>
   6 #include <fsp/api.h>
   7 #include <program_loading.h>
   8
   9 static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
  10 {
  11         scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
  12 }
  13
  14 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
  15 {
  16         FSP_S_CONFIG *scfg = &supd->FspsConfig;
  17
  18         fsp_assign_vbios_upds(scfg);
  19
  20         /*
  21          * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
  22          * before FSP-S was loaded, we would introduce contention onto the SPI bus and
  23          * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
  24          * no SPI operations, we can read the APOB while FSP-S executes.
  25          */
  26         start_apob_cache_read();
  27         /*
  28          * We enqueue the payload to be loaded after the APOB. This might cause a bit of
  29          * bus contention when loading uCode and OPROMs, but since those calls happen at
  30          * different points in the boot state machine it's a little harder to sequence all the
  31          * async loading correctly. So in order to keep the complexity down, we enqueue the
  32          * payload preload here. The end goal will be to add uCode and OPROM preloading
  33          * before the payload so that the sequencing is correct.
  34          *
  35          * While FSP-S is executing, it's not currently possible to enqueue other transactions
  36          * because FSP-S doesn't call `thread_yield()`. So the payload will start loading
  37          * right after FSP-S completes.
  38          */
  39         if (!acpi_is_wakeup_s3())
  40                 payload_preload();
  41 }