src/soc/amd/cezanne/root_complex.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpigen.h>
   4 #include <amdblocks/alib.h>
   5 #include <amdblocks/data_fabric.h>
   6 #include <amdblocks/ioapic.h>
   7 #include <amdblocks/root_complex.h>
   8 #include <arch/ioapic.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <soc/iomap.h>
  12 #include <static.h>
  13 #include <stdint.h>
  14 #include "chip.h"
  15
  16 #define DPTC_TOTAL_UPDATE_PARAMS        4
  17
  18 struct dptc_input {
  19         uint16_t size;
  20         struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
  21 } __packed;
  22
  23 #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow)                    \
  24         {                                                                       \
  25                 .size = sizeof(struct dptc_input),                              \
  26                 .params = {                                                     \
  27                         {                                                       \
  28                                 .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID,       \
  29                                 .value = _thermctllmit,                         \
  30                         },                                                      \
  31                         {                                                       \
  32                                 .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID,       \
  33                                 .value = _sustained,                            \
  34                         },                                                      \
  35                         {                                                       \
  36                                 .id = ALIB_DPTC_FAST_PPT_LIMIT_ID,              \
  37                                 .value = _fast,                                 \
  38                         },                                                      \
  39                         {                                                       \
  40                                 .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID,              \
  41                                 .value = _slow,                                 \
  42                         },                                                      \
  43                 },                                                              \
  44         }
  45
  46 static void acipgen_dptci(void)
  47 {
  48         const struct soc_amd_cezanne_config *config = config_of_soc();
  49
  50         /* Normal mode DPTC values. */
  51         struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
  52                 config->sustained_power_limit_mW,
  53                 config->fast_ppt_limit_mW,
  54                 config->slow_ppt_limit_mW);
  55         acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
  56 }
  57
  58 static void root_complex_fill_ssdt(const struct device *device)
  59 {
  60         if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
  61                 acipgen_dptci();
  62 }
  63
  64 static const char *gnb_acpi_name(const struct device *dev)
  65 {
  66         return "GNB";
  67 }
  68
  69 struct device_operations cezanne_root_complex_operations = {
  70         /* The root complex has no PCI BARs implemented, so there's no need to call
  71            pci_dev_read_resources for it */
  72         .read_resources         = noop_read_resources,
  73         .set_resources          = noop_set_resources,
  74         .enable_resources       = pci_dev_enable_resources,
  75         .acpi_name              = gnb_acpi_name,
  76         .acpi_fill_ssdt         = root_complex_fill_ssdt,
  77 };
  78
  79 static const struct domain_iohc_info iohc_info[] = {
  80         [0] = {
  81                 .fabric_id = IOMS0_FABRIC_ID,
  82                 .misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
  83         },
  84 };
  85
  86 const struct domain_iohc_info *get_iohc_info(size_t *count)
  87 {
  88         *count = ARRAY_SIZE(iohc_info);
  89         return iohc_info;
  90 }
  91
  92 static const struct non_pci_mmio_reg non_pci_mmio[] = {
  93         { 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  94         { 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  95         { 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  96         /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
  97            tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
  98            resource. */
  99         { 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
 100         { 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 101         { 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 102         { 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
 103         { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
 104 };
 105
 106 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
 107 {
 108         *count = ARRAY_SIZE(non_pci_mmio);
 109         return non_pci_mmio;
 110 }