src/soc/amd/stoneyridge/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __STONEYRIDGE_CHIP_H__
   4 #define __STONEYRIDGE_CHIP_H__
   5
   6 #include <stddef.h>
   7 #include <stdint.h>
   8 #include <commonlib/helpers.h>
   9 #include <drivers/i2c/designware/dw_i2c.h>
  10 #include <gpio.h>
  11 #include <soc/i2c.h>
  12 #include <acpi/acpi_device.h>
  13
  14 #define MAX_NODES 1
  15 #if CONFIG(AMD_APU_MERLINFALCON)
  16 #define MAX_DRAM_CH 2
  17 #define MAX_DIMMS_PER_CH 2
  18 #else /* AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON */
  19 #define MAX_DRAM_CH 1
  20 #define MAX_DIMMS_PER_CH 2
  21 #endif
  22
  23 #define STONEY_I2C_DEV_MAX 4
  24
  25 struct soc_amd_stoneyridge_config {
  26         u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
  27         enum {
  28                 DRAM_CONTENTS_KEEP,
  29                 DRAM_CONTENTS_CLEAR
  30         } dram_clear_on_reset;
  31
  32         enum {
  33                 /* Do not enable UMA in the system. */
  34                 UMAMODE_NONE,
  35                 /* Enable UMA with a specific size. */
  36                 UMAMODE_SPECIFIED_SIZE,
  37                 /* Let AGESA determine the proper size. Non-legacy requires
  38                  * the resolution to be specified PLATFORM_CONFIGURATION */
  39                 UMAMODE_AUTO_LEGACY,
  40                 UMAMODE_AUTO_NON_LEGACY,
  41         } uma_mode;
  42
  43         /* Used if UMAMODE_SPECIFIED_SIZE is set. */
  44         size_t uma_size;
  45
  46         /*
  47          * If sb_reset_i2c_peripherals() is called, this devicetree register
  48          * defines which I2C SCL will be toggled 9 times at 100 KHz.
  49          * For example, should we need I2C0 and  I2C3 have their peripheral
  50          * devices reset by toggling SCL, use:
  51          *
  52          * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
  53          */
  54         u8 i2c_scl_reset;
  55         struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
  56         u8 stapm_percent;
  57         u32 stapm_time_ms;
  58         u32 stapm_power_mw;
  59         /*
  60          * This specifies the LVDS/eDP power-up sequence time for the delay
  61          * between VaryBL and BLON.
  62          * 0 - Use the VBIOS default (default). The video BIOS default is 32ms.
  63          * n - Values other than zero specify a setting of (4 * n) milliseconds
  64          *     time delay.
  65          */
  66         u8 lvds_poseq_varybl_to_blon;
  67         u8 lvds_poseq_blon_to_varybl;
  68 };
  69
  70 #endif /* __STONEYRIDGE_CHIP_H__ */