src/soc/amd/stoneyridge/i2c.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpimmio.h>
   4 #include <amdblocks/i2c.h>
   5 #include <soc/iomap.h>
   6 #include <soc/i2c.h>
   7 #include <static.h>
   8 #include "chip.h"
   9 #include <drivers/i2c/designware/dw_i2c.h>
  10
  11 /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
  12 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
  13         I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
  14         I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
  15         I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
  16         I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
  17 };
  18
  19 static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = {
  20         { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" },
  21         { I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" },
  22         { I2C_MASTER_MODE, APU_I2C2_BASE, "I2CC" },
  23         { I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" },
  24 };
  25
  26 void reset_i2c_peripherals(void)
  27 {
  28         const struct soc_amd_stoneyridge_config *cfg = config_of_soc();
  29         struct soc_i2c_peripheral_reset_info reset_info;
  30
  31         reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
  32         reset_info.i2c_scl = i2c_scl_pins;
  33         reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
  34         sb_reset_i2c_peripherals(&reset_info);
  35 }
  36
  37 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
  38 {
  39         *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
  40         return i2c_ctrlr;
  41 }
  42
  43 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
  44 {
  45         const struct soc_amd_stoneyridge_config *config = config_of_soc();
  46
  47         *num_buses = ARRAY_SIZE(config->i2c);
  48         return config->i2c;
  49 }
  50
  51 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
  52 {
  53         /* Do nothing. */
  54 }