src/soc/amd/stoneyridge/psp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/hpet.h>
   4 #include <device/pci_ops.h>
   5 #include <device/pci_def.h>
   6 #include <soc/pci_devs.h>
   7 #include <soc/northbridge.h>
   8 #include <soc/southbridge.h>
   9 #include <amdblocks/psp.h>
  10
  11 void soc_enable_psp_early(void)
  12 {
  13         u32 base, limit;
  14         u16 cmd;
  15
  16         /* Open a posted hole from 0x80000000 : 0xfed00000-1 */
  17         base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
  18         limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
  19         pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
  20         pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
  21
  22         /* Preload a value into BAR and enable it */
  23         pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
  24         pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
  25
  26         /* Enable memory access and master */
  27         cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
  28         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  29         pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
  30 };