src/soc/amd/stoneyridge/sata.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <device/pci_ops.h>
   6 #include <amdblocks/sata.h>
   7 #include <soc/southbridge.h>
   8
   9 void soc_enable_sata_features(struct device *dev)
  10 {
  11         u8 *ahci_ptr;
  12         u32 misc_ctl, cap_cfg;
  13
  14         u32 temp;
  15
  16         /* unlock the write-protect */
  17         misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
  18         misc_ctl |= SATA_MISC_SUBCLASS_WREN;
  19         pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
  20
  21         /* set the SATA AHCI mode to allow port expanders */
  22         ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
  23                 pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
  24
  25         cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
  26         cap_cfg |= SATA_CAPABILITY_SPM;
  27         write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
  28
  29         /* lock the write-protect */
  30         temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
  31         temp &= ~SATA_MISC_SUBCLASS_WREN;
  32         pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
  33 };